ICM7226A, ICM7226B T ODUC T T E PR E ODUC L R O P S E T OB U BSTIT LE SU M7216 IC POSSIB 8-Digit, Multi-Function, Frequency Counter/Timer May 2001 itle M7 6A, M72 B) bt (8git, ltincn, ency unte ime Features Description • CMOS Design for Very Low Power The ICM7226 is a fully integrated Universal Counter and LED display driver. It combines a high frequency oscillator, a decade timebase counter, an 8-decade data counter and latches, a 7-segment decoder, digit multiplexer and segment and digit drivers which can directly drive large LED displays. The counter inputs accept a maximum frequency of 10MHz in frequency and unit counter modes and 2MHz in the other modes. Both inputs are digital inputs. In many applications, amplification and level shifting will be required to obtain proper digital signals for these inputs. • Output Drivers Directly Drive Both Segments of Large 8-Digit LED Displays Digits and • Measures Frequencies from DC to 10MHz; Periods from 0.5µs to 10s • Stable High Frequency Oscillator uses either 1MHz or 10MHz Crystal • Both Common Anode and Common Cathode Available • Control Signals Available Interfacing for External Systems The ICM7226 can function as a frequency counter, period counter, frequency ratio (fA/fB) counter, time interval counter or as a totalizing counter. The devices require either a 10MHz or 1MHz quartz crystal timebase, or if desired an external timebase can also be used. For period and time interval, the 10MHz timebase gives a 0.1µs resolution. In period average and time interval average, the resolution can be in the nanosecond range. In the frequency mode, the user can select accumulation times of 0.01s, 0.1s, 1s and 10s. With a 10s accumulation time, the frequency can be displayed to a resolution of 0.1Hz. There is 0.2s between measurements in all ranges. Control signals are provided to enable gating and storing of prescaler data. • Multiplexed BCD Outputs Applications • Frequency Counter utho ) eyrds ter- • Period Counter • Unit Counter • Frequency Ratio Counter • Time Interval Counter Leading zero blanking has been incorporated with frequency display in kHz and time in µs. The display is multiplexed at a 500Hz rate with a 12.2% duty cycle for each digit. The ICM7226A is designed for common anode displays with typical peak segment currents of 25mA, and the ICM7226B is designed for common cathode displays with typical segment currents of 12mA. In the display off mode, both digit drivers and segment drivers are turned off, allowing the display to be used for other functions. Part Number Information rpoion, minctor ency unte ime PART NUMBER TEMP. RANGE ( oC) PACKAGE PKG. NO. ICM7226AlJL -25× to 85 40 Ld CERDIP F40.6 ICM7226BlPL -25× to 85 40 Ld PDIP E40.6 git, truntan, w wer, ta 1-888-INTERSIL or 321-724-7143 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001 1 File Number 3169.2 ICM7226A, ICM7226B Pinouts ICM7226A COMMON ANODE (CERDIP) TOP VIEW CONTROL INPUT 1 40 INPUT A INPUT B 2 39 HOLD MEASUREMENT IN PROGRESS 3 38 BUF OSC OUT FUNCTION 4 37 NC (NOTE 1) STORE 5 36 OSC OUT BCD 4 6 35 OSC IN BCD 8 7 34 NC (NOTE 1) DP 8 33 EXT OSC IN SEG e 9 32 RST OUT SEG g 10 31 EXT RANGE SEG a 11 30 D1 VSS 12 29 D2 SEG d 13 28 D3 SEG b 14 27 D4 SEG c 15 26 D5 SEG f 16 25 VDD BCD 2 17 24 D6 BCD 1 18 23 D7 RST INPUT 19 22 D8 EXT DP IN 20 21 RANGE ICM7226B COMMON CATHODE (PDIP) TOP VIEW CONTROL INPUT 1 40 INPUT A INPUT B 2 39 HOLD MEASUREMENT IN PROGRESS 3 38 BUF OSC OUT FUNCTION 4 37 NC (NOTE 1) STORE 5 36 OSC OUT BCD 4 6 35 OSC IN BCD 8 7 34 NC (NOTE 1) D1 8 33 EXT OSC IN D3 9 32 RST OUT D2 10 31 EXT RANGE D4 11 30 DP OUT VSS 12 29 SEG g D5 13 28 SEG e D6 14 27 SEG a D7 15 26 SEG d D8 16 25 VDD BCD 2 17 24 SEG b BCD 1 18 23 SEG c RST INPUT 19 22 SEG f EXT DP IN 20 21 RANGE NOTE: 1. For maximum frequency stability, connect to VDD or VSS . 2 ICM7226A, ICM7226B Functional Block Diagram 8 DECODER 8 DIGIT DRIVERS REFERENCE COUNTER +10 3 3 RANGE CONTROL LOGIC EXT OSC INPUT OSC INPUT 10 4 OR 10 5 OSC SELECT STORE AND RESET LOGIC 100Hz OSC OUTPUT RANGE SELECT LOGIC CONTROL LOGIC 6 RESET INPUT INPUT A 4 INPUT B 4 4 DP LOGIC OVERFLOW 4 4 4 4 EXT DP INPUT 4 DATA LATCHES 8 STORE OUTPUT MUX D INPUT CONTROL LOGIC CONTROL INPUT RESET MAIN EN COUNTER ÷103 CL INPUT CONTROL LOGIC RANGE INPUT EXT RANGE INPUT 5 BUF OSC OUTPUT DIGIT OUTPUTS (8) CL DECODER AND LZB LOGIC 4 Q 7 SEGMENT DRIVERS 8 SEGMENT OUTPUTS (8) MAIN FF R FUNCTION INPUT 4 FN CONTROL LOGIC 4 BCD OUTPUTS (4) RESET OUTPUT 6 MEAS IN PROGRESS OUTPUT STORE OUTPUT HOLD INPUT 3 ICM7226A, ICM7226B Absolute Maximum Ratings Thermal Information Maximum Supply Voltage (VDD - VSS). . . . . . . . . . . . . . . . . . . . 6.5V Maximum Digit Output Current . . . . . . . . . . . . . . . . . . . . . . . . 400mA Maximum Segment Output Current . . . . . . . . . . . . . . . . . . . . . 60mA Voltage On Any Input or Output Terminal (Note 1) . . . . . . . . . . . . . . VDD +0.3V to VSS -0.3V Thermal Resistance (Typical, Note 2) θJA ( oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 45 9 PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A Maximum Junction Temperature CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Destructive latchup may occur if input signals are applied before the power supply is established or if inputs or outputs are forced to voltages exceeding VDD or VSS by 0.3V. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5.0V, TA = 25oC, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 2 5 mA 4.75 - 6.0 V -25oC to 85oC 4.75V < VDD < 6.0V, Figure 9 Function = Frequency, Ratio, Unit Counter 10 14 - MHz Function = Period, Time Interval 2.5 - - MHz -25oC to 85oC 2.5 - - MHz 250 - - ns 0.1 - 10 MHz 2000 - - µS Operating Supply Current, IDD Display Off, Unused Inputs to VSS Supply Voltage Range (VDD -VSS), VSUPPLY -25oC to 85oC, INPUT A, INPUT B Frequency at fMAX Maximum Frequency INPUT A, Pin 40, fA(MAX) Maximum Frequency INPUT B, Pin 2, fB(MAX) 4.75V < VDD < 6.0V, Figure 10 Minimum Separation INPUT A to INPUT B, Time Interval Function -25oC to 85oC 4.75V < VDD < 6.0V, Figure 1 Oscillator Frequency and External Oscillator Frequency, -25oC to 85oC 4.75V < VDD < 6.0V fOSC Oscillator Transconductance, gM VDD -4.75V, TA = 85oC Multiplex Frequency, fMUX fOSC = 10MHz - 500 - Hz Time Between Measurements fOSC = 10MHz - 200 - ms Input Rate of Charge, dVIN/dt Inputs A, B - 15 - mV/µs -25oC to 85oC - - 1.0 V 3.5 - - V - - 20 µA Input Voltages: Pins 2, 19, 33, 39, 40, 35 Input Low Voltage, VIL Input High Voltage, VlH Pins 2, 39, 40, Input Leakage, A, B, IILK Input Resistance to VDD Pins 19, 33, RIN VIN = VDD -1.0V 100 400 - kΩ Input Resistance to VSS Pin 31, RIN VIN = +1.0V 50 100 - kΩ Low Output Current, Pins 3, 5-7, 17, 18, 32, 38, IOL VOL = +0.4V 400 - - µA High Output Current, Pins 5-7, 17, 18, 32, H OL VOH = +2.4V 100 - - µA High Output Current, Pins 3, 38, HOL VOH = VDD -0.8V 265 - - µA Low Output Current, IOL VO = +1.5V 25 35 - mA High Output Current, IOH VO = VDD -1.0V - 100 - µA Output Current ICM7226A Segment Driver: Pins 8-11, 13-16 4 ICM7226A, ICM7226B Electrical Specifications VDD = 5.0V, TA = 25oC, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage, VIL - - 0.8 V Input High Voltage, VIH 2.0 - - V VIN = +1.0V 50 100 - kΩ Low Output Current, IOL VO = +1.0V - -0.3 - mA High Output Current, IOH VO = VDD -2.0V 150 180 - mA - - 10 µA 10 15 - mA Input Low Voltage, VIL - - VDD-2.0 V Input High Voltage, VIH VDD-0.8 - - V VIN = VDD -1.0V 100 360 - kΩ Low Output Current, IOL VO = +1.0V 50 75 - mA High Output Current, IOH VO = VDD -2.5V - 100 - µA Multiplex Inputs: Pins 1, 4, 20, 21 Input Resistance to VSS, RIN Digit Driver: Pins 22-24, 26-30 ICM7226B Segment Driver: Pins 22-24, 26-30 Leakage Current, IL VO = VSS High Output Current, IOH VO = VDD -2.0V Multiplex Inputs: Pins 1, 4, 20, 21 Input Resistance to VSS, RIN Digit Driver: Pins 8-11, 13-16 NOTES: 1. Assumes all leads soldered or welded to PC board and free air flow. 2. Typical values are not tested. Timing Waveform 40ms STORE 30ms TO 40ms 60ms RESET 40ms UPDATE 190ms TO 200ms FUNCTION: TIME INTERVAL UPDATE PRIMING MEASUREMENT INTERVAL MEASUREMENT IN PROGRESS INPUT A PRIMING EDGES INPUT B 250ns MIN MEASURED INTERVAL (FIRST) NOTE: MEASURED INTERVAL (LAST) 1. If range is set to 1 event, first and last measured interval will coincide. FIGURE 1. WAVEFORMS FOR TIME INTERVAL MEASUREMENT (OTHERS ARE SIMILAR, BUT WITHOUT PRIMING PHASE) 5 ICM7226A, ICM7226B Typical Performance Curves 200 300 TA = 25oC 4.5 ≤ VDD ≤ 6.0V VDD = 5.5V 50 200 VDD = 4.5V IDIG (mA) IDIGIT (mA) VDD = 5.0V 100 100 50 25 oC 85oC -20oC 0 0 0 1 2 0 3 1 FIGURE 2. ICM7226B TYPICAL IDIGIT vs VOUT 30 2 3 VDD-VOUT (V) VOUT (V) FIGURE 3. ICM7226A TYPICAL IDIG vs VDD-V OUT 80 4.5 ≤ VDD ≤ 6.0V TA = 25 oC -20oC VDD = 5.5V 25oC 60 VDD = 5.0V 20 ISEG (mA) ISEG (mA) 85oC VDD = 4.5V 40 10 20 0 0 0 1 2 3 0 1 VDD-VOUT (V) 2 FIGURE 4. ICM7226B TYPICAL ISEG vs VDD-V OUT FIGURE 5. ICM7226A TYPICAL ISEG vs VOUT 200 80 -20oC VDD = 5.0V VDD = 5.0V -20oC 25 oC 25 oC 60 ISEG (mA) IDIGIT (mA) 150 85oC 100 85oC 40 20 50 0 3 VOUT (V) 0 0 1 2 0 3 1 2 VOUT (V) VOUT (V) FIGURE 6. ICM7226B TYPICAL IDIGIT vs VOUT FIGURE 7. ICM7226A TYPICAL ISEG vs VOUT 6 3 ICM7226A, ICM7226B Typical Performance Curves (Continued) 20 fA (MAX) FREQUENCY UNIT COUNTER, FREQUENCY RATIO MODES FREQUENCY (MHz) 15 10 fA (MAX) fB (MAX) PERIOD TIME INTERVAL MODES 5 TA = 25oC 0 3 4 5 6 VDD-VSS (V) FIGURE 8. fA(MAX), fB(MAX) AS A FUNCTION OF SUPPLY Description Both inputs are digital inputs with a typical switching threshold of 2.0V at VDD = 5.0V and input impedance of 250kΩ. For optimum performance, the peak-to-peak input signal should be at least 50% of the supply voltage and centered about the switching voltage. When these inputs are being driven from TTL logic, it is desirable to use a pullup resistor. The circuit counts high to low transitions at both inputs INPUTS A and B The signal to be measured is applied to INPUT A in frequency period, unit counter, frequency ratio and time interval modes. The other input signal to be measured is applied to INPUT B in frequency ratio and time interval. fA should be higher than fB during frequency ratio. Note that the amplitude of the input should not exceed the device supply (above the VDD and below the VSS) by more than 0.3V, otherwise the device may be damaged. COUNTED TRANSITIONS Multiplexed Inputs 50ns MIN INPUT A 4.5V 0.5V The FUNCTION, RANGE, CONTROL and EXTERNAL DECIMAL POINT inputs are time multiplexed to select the function desired. This is achieved by connecting the appropriate Digit driver output to the inputs. The function, range and control inputs must be stable during the last half of each digit output, (typically 125µs). The multiplexed inputs are active high for the common anode lCM7226A and active low for the common cathode lCM7226B. tr = tf = 10ns 50ns MIN FIGURE 9. WAVEFORM FOR GUARANTEED MINIMUM fA(MAX) FUNCTION = FREQUENCY, FREQUENCY RATIO, UNIT COUNTER Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of operation is selected, since changes in voltage on the digit drivers can be capacitively coupled through the LED diodes to the multiplex inputs. For maximum noise immunity, a 10kΩ resistor should be placed in series with the multiplexed inputs as shown in the application circuits. MEASURED INTERVAL 250ns MIN INPUT A OR 4.5V INPUT B 0.5V 250ns MIN tr = tf = 10s FIGURE 10. WAVEFORM FOR GUARANTEED MINIMUM fB(MAX) AND fA(MAX) FOR FUNCTION = PERIOD AND TIME INTERVAL 7 ICM7226A, ICM7226B The implementation of different functions is done by routing the different signals to two counters, called “Main Counter” and “Reference Counter”. A simplified block diagram of the device for functions realization is shown in Figure 11. Table 2 shows which signals will be routed to each counter in different cases. The output of the Main Counter is the information which goes to the display. The Reference Counter divides its input to 1, 10, 100 and 1000. One of these outputs will be selected through the range selector and drive the enable input of the Main Counter. This means that the Reference Counter, along with its' associated blocks, directs the Main Counter to begin counting and determines the length of the counting period. Note that Figure 11 does not show the complete functional diagram (See the Functional Block Diagram). After the end of each counting period, the output of the Main Counter will be latched and displayed, then the counter will be reset and a new measurement cycle will begin. Any change in the FUNCTION INPUT will stop the present measurement without updating the display and then initiate a new measurement. This prevents an erroneous first reading after the FUNCTION INPUT is changed. In all cases, the 1-0 transitions are counted or timed. Table 1 shows the functions selected by each digit for these inputs. TABLE 1. MULTIPLEXED INPUT FUNCTIONS INPUT FUNCTION FUNCTION INPUT Pin 4 RANGE INPUT Pin 21 CONTROL INPUT Pin 1 DIGIT Frequency D1 Period D8 Frequency Ratio D2 Time Interval D5 Unit Counter D4 Oscillator Frequency D3 0.01s/1 Cycle D1 0.1s/10 Cycles D2 1s/100 Cycles D3 10s/1K Cycles D4 Enable External Range Input D5 Display Off D4 and Hold TABLE 2. INPUT ROUTING Display Test D8 1MHz Select D2 External Oscillator Enable D1 Frequency (fA) Input A 100Hz (Oscillator ³÷105 or 104) External Decimal Point Enable D3 Period (tA) Oscillator Input A Ratio (fA /fB) Input A Input B Time Interval (A→B) Oscillator Input A Input B Function Input Unit Counter (Count A) Input A Not Applicable The six functions that can be selected are: Frequency, Period, Time Interval, Unit Counter, Frequency Ratio and Oscillator Frequency. Osc. Freq. (fOSC) Oscillator 100Hz (Oscillator ³÷105 or 104) External DP INPUT Pin 20 FUNCTION Decimal point is output for same digit that is connected to this input. INTERNAL CONTROL MAIN COUNTER COUNTER INTERNAL CONTROL 100Hz INPUT A INPUT SELECTOR CLOCK INPUT B REFERENCE COUNTER ÷ 1 ÷ 10 ÷ 100 ÷ 1000 INTERNAL CONTROL INTERNAL OR EXTERNAL OSCILLATOR INPUT A INTERNAL CONTROL RANGE SELECTOR ENABLE INPUT SELECTOR CLOCK MAIN COUNTER FIGURE 11. SIMPLIFIED BLOCK DIAGRAM OF FUNCTIONS IMPLEMENTATION 8 ICM7226A, ICM7226B a 39pF to 100pF capacitor should also be placed between this input and the V DD or VSS (See Figure 19). Frequency - In this mode input A is counted by the Main Counter for a precise period of time. This time is determined by the time base oscillator and the selected range. For the 10MHz (or 1MHz) time base, the resolutions are 100Hz, 10Hz, 1Hz and 0.1Hz. The decimal point on the display is set for kHz reading. Display Off - To disable the display drivers, it is necessary to tie the D4 line to the CONTROL INPUT and have the HOLD input at VDD . While in Display Off mode, the segments and digit drivers are all off, leaving the display lines floating, so the display can be shared with other devices. In this mode, the oscillator continues to run with a typical supply current of 1.5mA with a 10MHz crystal, but no measurements are made and multiplexed inputs are inactive. A new measurement cycle will be initiated when the HOLD input is switched to VSS . Period - In this mode, the timebase oscillator is counted by the Main Counter for the duration of 1, 10, 100 or 1000 (range selected) periods of the signal at input A. A 10MHz timebase gives resolutions of 0.1µs to 0.0001µs for 1000 periods averaging. Note that the maximum input frequency for period measurement is 2.5MHz. Display Test - Display will turn on with all the digits showing 8s and all decimal points also on. The display will be blanked if Display Off is selected at the same time. Frequency Ratio - In this mode, the input A is counted by the Main Counter for the duration of 1, 10, 100 or 1000 (range selected) periods of the signal at input B. The frequency at input A should be higher than input B for meaningful result. The result in this case is unitless and its resolution can go up to 3 digits after decimal point. 1MHz Select - The 1MHz select mode allows use of a 1MHz crystal with the same digit multiplex rate and time between measurement as with a 10MHz crystal. This is done by dividing the oscillator frequency by 104 rather than 105. The decimal point is also shifted one digit to the right in period and time interval, since the least significant digit will be in µs increment rather than 0.1µs increment. Time Interval - In this mode, the timebase oscillator is counted by the Main Counter for the duration of a 1-0 transition of input A until a 1-0 transition of input B. This means input A starts the counting and input B stops it. If other ranges, except 0.01s/1 cycle are selected the sequence of input A and B transitions must happen 10, 100 or 1000 times until the display becomes updated; note this when measuring long time intervals to give enough time for measurement completion. The resolution in this mode is the same as for period measurement. See the Time Interval Measurement section also. External Oscillator Enable - In this mode, the signal at EXT OSC INPUT is used as a timebase instead of the on-board crystal oscillator (built around the OSC INPUT, OSC OUTPUT inputs). This input can be used for an external stable temperature compensated crystal oscillator or for special measurements with any external source. The on-board crystal oscillator continues to work when the external oscillator is selected. This is necessary to avoid hang-up problems, and has no effect on the chip's functional operation. If the on-board oscillator frequency is less than 1MHz or only the external oscillator is used, THE OSC INPUT MUST BE CONNECTED TO THE EXT OSC INPUT providing the timebase has enough voltage swing for OSC INPUT (See Electrical Specifications). If the external timebase is TTL level a pullup resistor must be used for OSC INPUT. The other way is to put a 22MΩ resistor between OSC INPUT and OSC OUTPUT and capacitively couple the EXT OSC INPUT to OSC INPUT. This will bias the OSC INPUT at its threshold and the drive voltage will need to be only 2VP-P. The external timebase frequency must be greater than 100kHz or the chip will reset itself to enable the on-board oscillator. Unit Counter - In this mode, the Main Counter is always enabled. The input A is counted by the Main Counter and displayed continuously. Oscillator Frequency - In this mode, the device makes a frequency measurement on its timebase. This is a self test mode for device functionality check. For 10MHz timebase the display will show 10000.0, 10000.00, 10000.000 and Overflow in different ranges. Range Input The RANGE INPUT selects whether the measurement period is made for 1,10,100 or 1000 counts of the Reference Counter or it is controlled by EXT RANGE input. As it is shown in Table 1, this gives different counting windows for frequency measurement and various cycles for other modes of measurement. External Decimal Point Enable - In this mode, the EX INPUT is enabled. A decimal point will be displayed for digit that its output line is connected to this input (EX INPUT). Digit 8 should not be used since it will override overflow output. Leading zero blanking is effective for digits to the left of selected decimal point. In all functional modes except Unit Counter, any change in the RANGE INPUT will stop the present measurement without updating the display and then initiate a new measurement. This prevents an erroneous first reading after the RANGE INPUT is changed. DP the DP the the Hold Input Control Input Except in the unit counter mode, when the HOLD input is at VDD , any measurement in progress (before STORE goes low) is stopped, the main counter is reset and the chip is held ready to initiate a new measurement as soon as HOLD goes low. The latches which hold the main counter data are not updated, so the last complete measurement is displayed. In unit counter mode when HOLD input is at VDD , the counter is not stopped or reset, but the display is frozen at that instantaneous value. When HOLD goes low the count continues from the new value in the new counter. Unlike the other multiplexed inputs, to which only one of the digit outputs can be connected at a time, this input can be tied to different digit lines to select combination of controls. In this case, isolation diodes must be used in digit lines to avoid crosstalk between them (see Figure 19). The direction of diodes depends on the device version, common anode or common cathode. For maximum noise immunity at this input, in addition to the 10K resistor which was mentioned before, 9 ICM7226A, ICM7226B RST IN Input 190ms TO 200ms MEAS IN PROGRESS The RST IN is provided to reset the Main Counter, stop any measurement in progress, and enable the display latches, resulting in the all zero display. It is suggested to have a capacitor at this input to VSS to prevent any hangup problem on power up. See application circuits. 40ms STORE 30ms TO 40ms 60ms RESET OUT EXT RANGE Input 40ms This input is provided to select ranges other than those provided in the chip. In any mode of measurement the duration of measurement is determined by the EXT RANGE if this input is enabled. This input is sampled at 10ms intervals by the 100Hz reference derived from the timebase. Figure 12 shows the relationship between this input, 100Hz reference signal and MEAS IN PROGRESS. EXT RANGE can change state anywhere during the period of 100Hz reference by will be sampled at the trailing edge of the period to start or stop measurement. FIGURE 13. RESET OUT, STORE AND MEASUREMENT IN PROGRESS OUTPUTS BETWEEN MEASUREMENTS BCD Outputs The BCD representation of each display digit is available at the BCD outputs in a multiplexed fashion. See Table 3 for digits truth table. The BCD output of each digit is available when its corresponding digit output is activated. Note that the digit outputs are multiplexed from D8 (MSD) to D1 (LSD). The positive going (ICM7226A, common anode) or the negative going (ICM7226B, common cathode) digit drive signals lag the BCD data by 2µs to 6µs. This starting edge of each digit drive signal should be used to externally latch the BCD data. Each BCD output drives one low power Schottky TTL load. Leading zero blanking has no effect on the BCD outputs. REFERENCE COUNTER CLOCK MEAS IN PROGRESS tr TABLE 3. TRUTH TABLE BCD OUTPUTS EXT RANGE INPUT FIGURE 12. EXTERNAL RANGE INPUT TO END OF MEASUREMENT IN PROGRESS NUMBER BCD 8 PIN 7 BCD 4 PIN 6 BCD 2 PIN 17 BCD 1 PIN 18 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 This input should not be used for short arbitrary ranges (because of its sampling period), it is provided for very long gating purposes. A way of using the ICM7226 for a short arbitrary range is to feed the gating signal into the INPUT B and run the device in the Frequency Ratio mode. Note that the gating period will be from one positive edge until the next positive edge of INPUT B (0.01s/1 cycle range). MEAS IN PROGRESS, STORE, RST OUT Outputs These outputs are provided for external system interfacing. MEAS IN PROGRESS stays low during measurements and goes high for intervals between measurements. Figure 13 shows the relationship between these outputs for intervals between measurements. All these outputs can drive a low power Schottky TTL. The MEAS IN PROGRESS can drive one ECL load if the ECL device is powered from the same power supply as the ICM7226. BUF OSC OUT Output The BUFFered OSCillator OUTput is provided for use of the on-board oscillator signal, without loading the oscillator itself. This output can drive one low power Schottky TTL load. Care should be taken to minimize capacitive loading on this pin. Decimal Point Position Table 4 shows the decimal point position for different modes of lCM7226 operation. Note that the digit 1 is the least significant digit. Table is given for 10MHz timebase frequency. TABLE 4. DECIMAL POINT POSITIONS RANGE FREQUENCY PERIOD FREQUENCY RATIO TIME INTERVAL UNIT COUNTER OSCILLATOR FREQUENCY 0.01s/1 Cycle D2 D2 D1 D2 D1 D2 0.1s/10 Cycle D3 D3 D2 D3 D1 D3 1s/100 Cycle D4 D4 D3 D4 D1 D4 10s/1K Cycle D5 D5 D4 D5 D1 D5 External N/A N/A N/A N/A N/A N/A 10 ICM7226A, ICM7226B When timing repetitive signals, it is not necessary to “prime” the lCM7226A and lCM7226B as the first alternating signal states automatically prime the device. See Figure 1. Overflow Indication When overflow happens in any measurement it will be indicated on the decimal point of the digit 8. A separate LED indicator can be used. Figure 14 shows how to connect this indicator. During any time interval measurement cycle, the ICM7226A and lCM7226B requires 200ms following B going low to update all internal logic. A new measurement cycle will not take place until completion of this internal update time. Oscillator Considerations a f The oscillator is a high gain complementary FET inverter. An external resistor of 10MΩ or 22MΩ should be connected between the oscillator input and output to provide biasing. The oscillator is designed to work with a parallel resonant 10MHz quartz crystal with a static capacitance of 22pF and a series resistance of less than 35Ω. Among suitable crystals is the 10MHz CTS KNIGHTS ISI-002. b g e c DP d LED overflow indicator connections: Overflow will be indicated on the decimal point output of digit 8. DEVICE For a specific crystal and load capacitance, the required gM can be calculated as follows: CATHODE ANODE ICM7226A Decimal Point D8 ICM7226B D8 Decimal Point C O 2 2 g M = ω C IN C OUT R S 1 + -------- CL C IN C OU T where C L = --------------------------------- C IN + C OUT FIGURE 14. SEGMENT IDENTIFICATION AND DISPLAY FONT Time Interval Measurement CO = Crystal Static Capacitance When in the time interval mode and measuring a single event, the lCM7226A and lCM7226B must first be “primed” prior to measuring the event of interest. This is done by first generating a negative going edge on Channel A followed by a negative going edge on Channel B to start the “measurement interval”. The inputs are then primed ready for the measurement. Positive going edges on A and B, before or after the priming, will be needed to restore the original condition. RS = Crystal Series Resistance CIN = Input Capacitance COUT = Output Capacitance ω = 2πf The required gM should not exceed 50% of the gM specified for the lCM7226 to insure reliable startup. The OSCillator INPUT and OUTPUT pins each contribute about 4pF to CIN and C OUT. For maximum stability of frequency, CIN and COUT should be approximately twice the specified crystal static capacitance. Priming can be easily accomplished using the circuit in Figure 15. SIGNAL A 2 INPUT A 2 INPUT B In cases where non decade prescalers are used, it may be desirable to use a crystal which is neither 10MHz or 1MHz. In that case both the multiplex rate and time between measurements will be different. The multiplex rate is: SIGNAL B VDD VDD PRIME N.O. fOSC fOSC f MUX = ------------------- for 10MHz mode and f MUX = ------------------- for the 4 3 2 × 10 2 × 10 6 2 × 10 1MHz mode. The time between measurements is ------------------- in fOSC 150K 1 1 1 1 10K 5 2 × 10 f OSC 1N914 100K 0.1µF VSS 10nF VSS DEVICE the 10MHz mode and ------------------- in the 1MHz mode. VSS The buffered oscillator output should be used as an oscillator test point or to drive additional logic; this output will drive one low power Schottky TTL load. When the buffered oscillator output is used to drive CMOS or the external oscillator input, a 10kΩ resistor should be added from the buffered oscillator output to VDD . TYPE 1 CD4049B Inverting Buffer 2 CD4070B Exclusive - OR FIGURE 15. PRIMING CIRCUIT, SIGNALS A AND B BOTH HIGH OR LOW The crystal and oscillator components should be located as close to the chip as practical to minimize pickup from other signals. Coupling from the EXTERNAL OSClLLATOR INPUT to the OSClLLATOR OUTPUT or INPUT can cause undesirable shifts in oscillator frequency. Following the priming procedure (when in single event or 1 cycle range) the device is ready to measure one (only) event. 11 ICM7226A, ICM7226B CMOS logic. Therefore, level shifting with discrete transistors may be required to use these outputs as logic signals. External latching should be down on the leading edge of the digit signal. Display Considerations The display is multiplexed at a 500Hz rate with a digit time of 244µs. An interdigit blanking time of 6µs is used to prevent display ghosting (faint display of data from previous digit superimposed on the next digit). Leading zero blanking is provided, which blanks the left hand zeroes after decimal point or any non zero digits. Digits to the right of the decimal point are always displayed. The leading zero blanking will be disabled when the Main Counter overflows. Accuracy In a Universal Counter, crystal drift and quantization errors cause errors. In frequency, period and time interval modes, a signal derived from the oscillator is used in either the Reference Counter or Main Counter, and in these modes, an error in the oscillator frequency will cause an identical error in the measurement. For instance, an oscillator temperature coefficient of 20ppm/oC will cause a measurement error of 20ppm/oC. The lCM7226A is designed to drive common anode LED displays at peak current of 25mA/segment, using displays with VF = 1.8V at 25mA. The average DC current will be greater than 3mA under these conditions. The lCM7226B is designed to drive common cathode displays at peak current of 15mA/segment using displays with VF = 1.8V at 15mA. Resistors can be added in series with the segment drivers to limit the display current, if required. The Typical Performance Curves show the digit and segment currents as a function of output voltage for common anode and common cathode drivers. In addition, there is a quantization error inherent in any digital measurement of ±1 count. Clearly this error is reduced by displaying more digits. In the frequency mode maximum accuracy is obtained with high frequency inputs and in period mode maximum accuracy is obtained with low frequency inputs. As can be seen in Figure 16. In time interval measurements there can be an error of 1 count per interval. As a result there is the same inherent accuracy in all ranges as shown in Figure 17. In frequency ratio measurement can be more accurately obtained by averaging over more cycles of INPUT B as shown in Figure 18. To increase the light output from the displays, VDD may be increased to 6.0V. However, care should be taken to see that maximum power and current ratings are not exceeded. The SEGment and Digit outputs in both the ICM7226A and ICM7226B are not directly compatible with either TTL or 0 FREQUENCY MEASURE MAXIMUM NUMBER OF SIGNIFICANT DIGITS MAXIMUM NUMBER OF SIGNIFICANT DIGITS 0 0.01s 0.1s 1s 10s 2 4 1 CYCLE 10 CYCLES 102 CYCLES 103 CYCLES 6 1 10 10 3 FREQUENCY (Hz) 2 MAXIMUM TIME INTERVAL FOR 103 INTERVALS 3 4 MAXIMUM TIME INTERVAL FOR 102 INTERVALS 5 6 MAXIMUM TIME INTERVAL FOR 10 INTERVALS 7 PERIOD MEASURE fOSC = 10MHz 8 1 8 105 1 107 102 10 10 3 10 4 105 TIME INTERVAL (µs) 106 10 7 10 8 FIGURE 17. MAXIMUM ACCURACY OF TIME INTERVAL MEASUREMENT DUE TO LIMITATIONS OF QUANTIZATION ERRORS FIGURE 16. MAXIMUM ACCURACY OF FREQUENCY AND PERIOD MEASUREMENTS DUE TO LIMITATIONS OF QUANTIZATION ERRORS 0 MAXIMUM NUMBER OF SIGNIFICANT DIGITS 1 RANGE 2 1 CYCLE 10 CYCLES 102 CYCLES 103 CYCLES 3 4 5 6 7 8 1 10 10 2 10 3 10 4 fA /fB 105 106 107 108 FIGURE 18. MAXIMUM ACCURACY FOR FREQUENCY RATIO MEASUREMENT DUE TO LIMITATION OF QUANTIZATION ERRORS 12 ICM7226A, ICM7226B Test Circuit DISPLAY DISPLAY OFF TEST 1MHz VDD = 5.0V EXT OSC IN EXT DP TEST FUNCTION GENERATOR INPUT A FUNCTION GENERATOR EXT OSC D4 D8 D2 D1 CONTROL INPUT D3 D5 1N914s 39pF VSS FUNCTION GENERATOR 10kΩ 1 40 2 39 3 38 4 37 STORE 5 36 BCD C 6 35 BCD D 7 34 DP 8 33 HOLD INPUT B MEAS IN PROGRESS FUNCTION 10K D1 D8 D2 D5 D4 D3 e g a 10MHz CRYSTAL VDD 22MΩ 32 10 31 11 30 EXT RANGE D1 ICM7226A 12 29 D2 d 13 28 D3 b 14 27 D4 c 15 26 D5 f 16 25 BCD B 17 24 D6 BCD A 18 23 D7 19 22 D8 20 21 RESET 6 VDD RST OUT 9 VDD BUF OSC OUT 30pF 39pF VDD VDD 8 CRYSTAL SPECS. = FO 10.00MHz CO 22pF RS 35Ω D1 D2 VDD 5 D3 D4 100kΩ D5 6 D1 D2 D3 D4 100kΩ 8 D5 D6 8 6 D7 a b c d e f g D8 8 DP D8 OVERFLOW D8 D7 DEVICE D6 D5 D4 D3 CATHODE ANODE ICM7226A DP D8 ICM7226B D8 DP D2 NOTE: Overflow will be indicated on the decimal point output of digit 8. FIGURE 19. 13 D1 DENOTES BUS WITH 6 CONDUCTORS ICM7226A, ICM7226B Typical Applications For input frequencies up to 40MHz, the circuit shown in Figure 21 can be used to implement a frequency and period counter. To obtain the correct value when measuring frequency and period, it is necessary to divide the 10MHz oscillator frequency down to 2.5MHz. In doing this the time between measurements is lengthened to 800ms and the display multiplex rate is decreased to 125Hz. The ICM7226 has been designed as a complete stand alone Universal Counter, or used with prescalers and other circuitry in a variety of applications. Since INPUT A and INPUT B are digital inputs, additional circuitry will be required in many applications, for input buffering, amplification, hysteresis, and level shifting to obtain the required digital voltages. For many applications a FET source follower can be used for input buffering, and an ECL 10116 line receiver can be used for amplification and hysteresis to obtain high impedance input, sensitivity and bandwidth. However, cost and complexity of this circuitry can vary widely, depending upon the sensitivity and bandwidth required. When TTL prescalers or input buffers are used, a pull up resistors to VDD should be used to obtain optimal voltage swing at INPUTS A and B. If prescalers aren’t required, the ICM7226 can be used to implement a minimum component Universal Counter as shown in Figure 20. If the input frequency is prescaled by ten, the oscillator frequency can remain at either 10MHz or 1MHz, but the decimal point must be moved. Figure 22 shows use of a ÷10 prescaler in frequency counter mode. Additional logic has been added to enable the ICM7226 to count the input directly in period mode for maximum accuracy. DISPLAY DISPLAY EXT OSC ENABLE BLANK TEST 10kΩ 39pF VDD VDD A IN 100kΩ 1 B IN 10kΩ D1 D8 D2 D5 D4 D3 40 39 3 38 4 37 5 36 6 35 7 34 V+ 8 33 EXT OSC IN 3 10MHz CRYSTAL 22MΩ 39pF 9 32 D2 10 31 D4 11 30 DP 39pF (TYP) V+ 12 29 g D5 13 28 e D6 14 27 a D7 15 26 D8 16 25 17 24 b 18 23 c 19 22 f 20 21 0.1µF D1 V+ D3 RESET D8 1N914s 2 ICM7226B D4 HOLD TYPICAL CRYSTAL PARAMETERS C L 22pF R S 35Ω V+ 8 d VDD 4 D1 100kΩ D2 D3 D4 6 a b c d e f g 8 DP D8 D7 D6 D5 D4 D3 D2 D1 D8 OVERFLOW FIGURE 20. 10MHz UNIVERSAL COUNTER 14 ICM7226A, ICM7226B VDD Q VDD P D ÷2 Q ÷2 CK Q VDD DISPLAY TEST DISPLAY OFF EXT OSC ENABLE 10kΩ D4 D8 3 V+ V+ 3kΩ D P C D1 Q D3 D Q 38 4 37 5 36 6 35 7 34 8 33 9 DP D5 13 28 D6 14 27 g e a D7 15 26 D8 16 25 17 24 b 18 23 c 19 22 f 20 21 74LS74 31 d VDD 4 D1 100kΩ D2 D3 RESET D4 a b c d e f g D8 D2 8 F P DP R 3 8 D8 D7 D6 D5 D4 D3 D2 D1 D8 OVERFLOW FIGURE 21. 40MHz FREQUENCY, PERIOD COUNTER 15 VDD 3kΩ 8 0.1 µF D1 Q VDD VDD Q ÷2 C 39pF (TYP) VDD 29 IC CK2 VDD 10MHz CRYSTAL 22MΩ 30 P Q 39pF 12 V+ D C VDD 11 Q P VDD 32 ICM7226B VDD Q IC ÷2 CK1 D4 B IN C 3 100kΩ D 10 V+ P 39 VDD 74LS74 VDD D2 Q V+ 40 2 A IN VDD HOLD 1N914 D1 VDD 3kΩ 1 CK C VDD 10kΩ D Q C 39pF P ICM7226A, ICM7226B VDD INPUT EXT DISPLAY DISPLAY OSC OFF TEST EN M1 CP ECL11C90 QTTL CE MS 10kΩ 74LS00 VDD 39pF D4 VDD 10kΩ M1 INPUT CP ECL11C90 QTTL CE MS V+ 10kΩ V+ 10kΩ 74LS00 F D1 D8 P D2 R D4 UC V+ 10kΩ 40 2 39 3 38 4 37 5 36 6 35 D1 10 kΩ VDD 8 10MHz CRYSTAL 34 VDD 33 e 9 32 EXT OSC IN 39pF g 10 a 11 30 12 29 d 13 28 b 14 27 D4 c 15 26 D5 f 16 25 17 24 D6 18 23 D7 D2 19 22 D8 20 21 D3 D4 8 8 31 22MΩ 39pF (TYP) VDD D1 VDD D2 D3 8 VDD D1 RANGE 5 D5 100kΩ a b c d e f g DP D8 D8 D7 D6 D5 OVERFLOW FIGURE 22. 100MHz MULTI-FUNCTION COUNTER 16 D3 100kΩ 8 ICM7226A D2 1N914s 7 S6 2 1 D8 HOLD DP 4 0.1µF 1MHz D4 D3 D2 D1 8 ICM7226A, ICM7226B VDD M1 CP ECL11C90 QTTL CE MS INPUT 39pF VDD DISPLAY DISPLAY OFF TEST 10kΩ VDD 10kΩ VDD 2N2222 3kΩ D4 VDD FUNCTION SWITCH OPEN FREQ CLOSED PERIOD VDD 10kΩ F D1 IN CONT 2 OUT CD4016 D1 D8 IN CONT 2 OUT 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 100kΩ HOLD 10kΩ 1N914s VDD 3 10MHz CRYSTAL VDD 22MΩ 39pF (TYP) 39pF 9 D2 10 D4 11 30 DP g e a 32 ICM7226B D1 VDD D3 31 12 29 D5 13 28 D6 14 27 D7 15 26 D8 16 25 17 24 18 23 c 19 22 f 20 21 N.O. 0.1µF 1 D8 VDD VDD d b VDD 8 10kΩ 4 D1 D2 D3 RESET INPUT D4 a b c d e f g 8 2 DP D8 D7 D6 D5 D4 D3 D2 D1 D8 OVERFLOW FIGURE 23. 100MHz FREQUENCY, PERIOD COUNTER 17 ICM7226A, ICM7226B Figure 23 shows the use of a CD4016 analog multiplexer to multiplex the digital outputs back to the FUNCTION Input. Since the CD4016 is a digitally controlled analog transmission gate, no level shifting of the digit output is required. CD4051s or CD4052s could also be used to select the proper inputs for the multiplexed input on the ICM7226 from 2-bit or 3-bit digital inputs. These analog multiplexers may also be used in systems in which the mode of operation is controlled by a microprocessor rather than directly from front panel switches. TTL multiplexers such as the 74LS153 or 74LS251 may also be used, but some additional circuitry will be required to convert the digit output to TTL compatible logic levels. to put the ICM7226 into a hold mode. The HOLD input can also be used to reduce the time between measurements. The circuit shown in Figure 25 puts a short pulse into the HOLD input a short time after STORE goes low. A new measurement will be initiated at the end of the pulse on the HOLD input. This circuit reduces the time between measurements to about 40ms from 200ms; use of the circuit shown in Figure 25 on the circuit shown in Figure 21 will reduce the time between measurements from 800ms to about 160ms. Using LCD Display Figure 26 shows the ICM7226 being interfaced to LCD displays, by using its BCD outputs and 8 digit lines to drive two ICM7211 display drivers. The circuit shown in Figure 24 can be used in any of the circuit applications shown to implement a single measurement mode of operation. This circuit uses the STORE output STORE OUTPUT HOLD INPUT 100kΩ S1 100kΩ S3 VDD VDD VDD 100kΩ 100kΩ S2 STORE OUTPUT VDD FUNCTION S1 Open-Single Meas Mode Enabled S2 Closed-Initiate New Measurement S3 Closed-Hold Input a f b N.O. g e f g e c d +5V 1 a f b g c d FIGURE 25. CIRCUIT FOR REDUCING TIME BETWEEN MEASUREMENTS a b HOLD INPUT HOLD SWITCH FIGURE 24. SINGLE MEASUREMENT CIRCUIT FOR USE WITH ICM7226 a 100pF 100pF SWITCH f 100kΩ e a b f g e c d a b f g e c d c e 22 23 24 26 D8 • • e c d b g c d e c d +5V 1 5 ICM7211 31 32 33 34 f g 28 SEGMENT LINES 5 35 a b g d 28 SEGMENT LINES a f b ICM7211 30 29 28 27 27 28 29 30 7 6 17 18 D5 31 32 33 34 27 28 29 30 D8 • • ICM7226A FIGURE 26. 10MHz UNIVERSAL COUNTER SYSTEM WITH LCD DISPLAY 18 D1 36 35 ICM7226A, ICM7226B All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 19 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369