Statistical Timing of Digital Integrated Circuits Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY http://www.research.ibm.com/people/c/chandu With acknowledgments to the extended timing, modeling, synthesis and methodology teams at IBM Yorktown, Fishkill and Burlington © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 1 ’Tis a pity that this ditty Isn’t pithy nor’s it witty; Rather it’s whimsical, even rhyming, The subject: statistical static timing! © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 2 Propositions 1. Variability is proportionately increasing; therefore, a new paradigm is required 2. Correlations matter 3. Statistical timing tools are rising to the challenge 4. Robustness is an important metric 5. Statistical treatment of variability will pervade all aspects of chip design and manufacturing • ASICs and processors will both benefit © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 3 The problem • Variability is proportionately increasing – manufacturing • FEOL: critical dimensions are scaling faster than our control of them • BEOL: variability dramatically increases the number of independent and significant sources of variation – – – – environmental (Vdd, temperature) fatigue (NBTI, hot electron effect) across-chip (OCV/ACLV, temperature, Vdd) circuit design (PLL jitter, coupling noise, SOI history) – model-to-hardware correlation © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 4 Delay impact of variations Parameter Delay Impact BEOL metal (Metal mistrack, thin/thick wires) -10% Environmental (Voltage islands, IR drop, temperature) ±15 % Device fatigue (NBTI, hot electron effects) ±10% Vt and Tox device family tracking (Can have multiple Vt and Tox device families) ± 5% Model/hardware uncertainty (Per cell type) ± 5% N/P mistrack (Fast rise/slow fall, fast fall/slow rise) ±10% PLL (Jitter, duty cycle, phase error) ±10% +25% [Courtesy Kerim Kalafala] • Requires 220 timing runs or [-65%,+80%] guard band! © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 5 Can you answer these questions about your favorite digital chip? • What does 5% random delay variability on each gate and wire do to your frequency distribution? • What does 5% correlated delay variability do to your frequency distribution? • What % delay variation leads to a hold violation? • How many yield points does OCV/ACLV cost? • What is the shape of your parametric yield curve? • What is the sensitivity of your chip’s frequency to – – – – thickness of a metal level? gate/wire mistracking? N/P mistracking? mistracking between metal levels i and j? © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 6 New paradigm required • ASICs – old paradigm: sign-off is corner- or case-based – would require 220 timing runs to hit all corners – cumbersome, risky and pessimistic all at the same time! • Microprocessors – for the most part, nominal performance is targeted – some ad hoc methods to deal with certain types of mistracking • Both – our design/synthesis methods do not target robustness, nor do our timing tools measure robustness or give credit for robust design • Solution: statistical timing and optimization © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 7 ITRS predictions © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 8 © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 9 © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 10 © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 11 What is a statistical timer? Netlist + assertions Delay and slew models Statistics of the sources of variability Static Statistical timer 1. Yield Slack curve 2. Diagnostics Diagnostics Dependence on sources of variability © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 12 Parametric yield curve Yield ¢ ¢¢ $ $$ Clock frequency © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 13 There’s so much variability That with a high probability We may fall into a trap, And design a piece of … (non-working silicon) © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 14 Importance of correlations • Consider a circuit with 50K latches, each with a setup and hold test, each of which has a 99.99% probability of being met • If all tests are perfectly correlated, yield = 99.99% • If all tests are perfectly independent, yield = 0.005% • The truth is closer to the perfectly correlated case! © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 15 Correlation due to path sharing © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 16 Clock and cell-type correlation © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 17 Voltage island correlation V dd1 V V V dd 4 V V V V V dd7 © Chandu Visweswariah, 2004 dd 2 dd5 dd8 Statistical Timing of Digital Integrated Circuits dd3 dd6 dd9 18 IS U FXU FPU FXU Global correlation IS U FPU ID U ID U LSU L3 Directory/Control IF U BXU © Chandu Visweswariah, 2004 L2 LSU L2 Statistical Timing of Digital Integrated Circuits IF U BXU L2 19 Temperature/Vdd correlation © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 20 Geographical correlation © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 21 [From M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, ICCAD 2000] Types of variability • Global within a die/reticle – metal dimensions – device family strength mistracking – ambient temperature and power supply • Spatial/local correlation across a die/reticle – Leff – junction temperature, Vdd • Independently random – tox – doping effects © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 22 0.8 Probability 1 The max of two unit Gaussians Note! 0.6 0.4 ρ =0 ρ =0.2 ρ =0.4 ρ =0.6 ρ =0.8 ρ =1.0 0.2 0 -2.0 © Chandu Visweswariah, 2004 Delay -1.0 Statistical Timing0.0 1.0 of Digital Integrated Circuits 2.0 23 0.8 Probability 1 Equally critical signals (ρ=0) 0.6 1 2 3 30 0.4 0.2 0 -3.0 -2.0 © Chandu Visweswariah, 2004 Delay -1.0 0.0 1.0 Statistical Timing of Digital Integrated Circuits 2.0 3.0 24 0.8 Probability 1 Equally critical signals (ρ=0.5) 0.6 1 2 3 30 0.4 0.2 0 -3.0 -2.0 © Chandu Visweswariah, 2004 Delay -1.0 0.0 1.0 Statistical Timing of Digital Integrated Circuits 2.0 3.0 25 0.8 Probability 1 Equally critical signals (ρ=1.0) 0.6 1 2 3 30 0.4 0.2 0 -3.0 -2.0 © Chandu Visweswariah, 2004 Delay -1.0 0.0 1.0 Statistical Timing of Digital Integrated Circuits 2.0 3.0 26 0.8 Probability 1 Thirty equally critical signals 0.6 ρ=1 ρ=0.5 ρ=0 0.4 0.2 0 -3.0 -2.0 © Chandu Visweswariah, 2004 Delay -1.0 0.0 1.0 Statistical Timing of Digital Integrated Circuits 2.0 3.0 27 u d e n u t n unc awa ertai re t ntyune d tuned #paths Slack histogram +20 ps © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits slack 28 The sum of n unit Gaussians (ρ=1.0) 0.03 1 2 3 4 5 6 7 8 9 10 Probability 0.04 0.02 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 Statistical Timing of Digital Integrated Circuits 6 8 1029 The sum of n unit Gaussians (ρ=0.5) 0.03 1 2 3 4 5 6 7 8 9 10 Probability 0.04 0.02 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 Statistical Timing of Digital Integrated Circuits 6 8 1030 The sum of n unit Gaussians (ρ=0) 0.03 1 2 3 4 5 6 7 8 9 10 Probability 0.04 0.02 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 Statistical Timing of Digital Integrated Circuits 6 8 1031 ρ =1.0 ρ =0.5 ρ =0.0 Probability 0.02 The sum of 10 unit Gaussians 0.01 0.01 Delay 0.00 -10 -8 © Chandu Visweswariah, 2004 -6 -4 -2 0 2 4 Statistical Timing of Digital Integrated Circuits 6 8 1032 Statistical timing experiment N(10,1) N(10,1) N(10,1) Arrival time=0 Data Latch with zero setup guard time Clock N(10,1) N(10,1) N(10,1) Arrival time=0 • How will slack change with ρ? © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 33 0.8 Probability 1.0 Timing experiment result ρ=1 ρ=0.5 ρ=0 0.6 0.4 0.2 Slack 0.0 -7 -6 -5 -4 -3 -2 -1 0 1 2 © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 3 4 5 6 734 There’s no question: correlation’s a pain Of neat math. formulas, it’s the bain! Though your timer becomes a morass It’s correlation that saves your … (chip) © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 35 Statistical timing tools • Path-based – conduct a nominal timing analysis – list a representative set of critical paths (question: how may paths? question: which paths?) – model the delay of each path as a function of random variables (the underlying sources of variation) – predict the parametric yield curve, as well as generate diagnostics • Block-based – propagate arrival times and required arrival times in the form of probability distributions – linear time – approximate, quick-and-dirty © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 36 Statistical timing tools Path-based Slow and accurate Non-incremental; for sign-off Parameter-space methods More general (usually Monte-Carlo-based) Fabrication-parameter diagnostics © Chandu Visweswariah, 2004 Block-based Quick and dirty Incremental; for (robust) optimization Performance-space methods Assumes symmetry and linearity Criticality probabilities useful to circuit designer Statistical Timing of Digital Integrated Circuits 37 Feasible region in parameter-space t ox Yield improvement or line-tailoring vector JPDF of global parameters Feasible region • Integration of the JPDF over the feasible region is the parametric yield © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits L eff 38 Path-based statistical timing Repeated EinsTimer runs Monte Carlo Parallelepi peds © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 68 hours 855 seconds 141 seconds 39 Block-based statistical timing • Deterministic a • Statistical + c + MAX b a + + c MAX b © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 40 Canonical variational delay model • Correlations are the problem – in a circuit with 1M nodes and 2M edges and 12 timing values per node/edge, we DO NOT want to store or manipulate a 36M x 36M covariance matrix! – instead, parameterize all timing quantities by the sources of variation – first-order canonical model: a0 + a1∆X 1 + a2 ∆X 2 + Λ + an ∆X n + an+1∆Ra Constant (nominal value) © Chandu Visweswariah, 2004 Sensitivities Deviation of global sources of variation from their nominal values Statistical Timing of Digital Integrated Circuits Random uncertainty (deviation from nominal value) 41 Procedure • Express all delays, slews, arrival times, required arrival times and slacks in canonical form • Propagate arrival times forward through the timing graph while preserving correlations • Propagate required arrival times backward while preserving correlations • Slack is the difference of arrival and required arrival times • Each path, node and edge has a probability of being critical; these criticality probabilities can be computed easily • All results are also available in canonical form; these diagnostics are extremely useful! © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 42 Interpreting statistical timing results • Critical path is not unique • Critical paths can be listed in order of probability of being critical – this should be the order in which the timing of paths is “fixed” or optimized • In deterministic timing, slack is identical along the critical path • This property does not hold in the case of statistical timing • Slacks reflect not only timing shortfalls, but also robustness shortfalls © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 43 Probability Latch timing considerations Dat a ar riv © Chandu Visweswariah, 2004 al ti me v i r r a k c Clo Statistical Timing of Digital Integrated Circuits e m i t al 44 Sample comparison to Monte Carlo Monte Carlo, 14 hours CPU time Block-based statistical timer, 18 seconds CPU time Test chip (3K gates) © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 45 Overhead of statistical calculations • Run time – about 20% on batch operation – about 50% on the actual arrival time propagation • Memory – about 100% depending on the number of sources of variation and complexity of the models • Capacity – able to time 2M+ gate ASIC chips on 64-bit machines © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 46 I’m no fool, I’ll be cool Sure, I’ll use this new-fangled tool Without it, I’m afraid I’ll be hit And my chip will be a piece of … (worthless silicon) © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 47 Remember these? • In addition to correctness, power, signal integrity and area, please welcome robustness to variation as a first-class design metric © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 48 First order model Robust design P( x, y ) = mean ∂p ∂2 p 2 + ∆x + 2 ∆x + Λ ∂x ∂2x ∂p ∂ p 2 + ∆y + 2 ∆y + Λ ∂y ∂y • Tremendously valuable if the statistical timer produces timing results in 1st order canonical form: Constant (nominal part) © Chandu Visweswariah, 2004 a0 + a1∆X 1 + a2∆X 2 + Λ + an+1∆Ra Sensitivities Global variations Statistical Timing of Digital Integrated Circuits Random uncertainty 49 Opportunities for robust design • Find out which sources of variation are the biggest yield detractors; quantify robustness of a design • Any commonality between data and clock cancels out to first order – voltage islands, gate types, device types, metal levels used for interconnect, proximity of launching and capturing paths • Robustness-enhancing design decisions – high sensitivity to N/P mistrack resynthesize with fewer tall P stacks, for example – high sensitivity to a particular metal level re-route – high sensitivity to Vt mistrack try to balance use of low/high Vt devices in capturing and launching paths – high sensitivity to wire/gate mistrack try to rebalance delay • Producing timing results in canonical form can help with line tailoring © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 50 The whole design team’s in a funk, With low yields, the company’ll be sunk! Should we heed this statistical bunk? Unrobust designs are a piece of …! (unmanufacturable hardware) © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 51 ASICs vs. microprocessors Microprocessor ASIC Large, less hierarchy Huge, hierarchical Limited abstraction (except for IP blocks on SoCs) No speed binning Requires timing abstraction Library-based Custom circuits + librarybased synthesized macros Focus on worst-case timing with ACLV/OCV penalty Focus on nominal timing © Chandu Visweswariah, 2004 Sorted and binned Statistical Timing of Digital Integrated Circuits 52 3σ BEOL Check front-end corners: possible escapes 2σ 1σ -3σ -2σ -1σ 1σ 2σ 3σ FEOL -1σ 1 GHz -2σ 900 MHz 800 MHz -3σ © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 53 3σ BEOL Check all corners: no escapes, pessimistic 2σ 1σ -3σ -2σ -1σ 1σ 2σ 3σ FEOL -1σ 1 GHz -2σ 900 MHz 800 MHz -3σ © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 600 MHz 54 3σ BEOL Statistical timing: no escapes, less pessimism 2σ 1σ -3σ -2σ -1σ 1σ 2σ 3σ FEOL 1 GHz -2σ 900 MHz 800 MHz -3σ © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 700 MHz -1σ 600 MHz 55 ASIC timing methodology • • • • Checking “all corners” is very pessimistic Checking “all corners” is intractable Statistical timing fits in “naturally” With the same area/power targets and the same tool suite, but a statistical timer to guide the placement, routing and optimization, the estimated performance improvement is of the order of 25% in 90nm technology • Test coverage can be improved by exploiting statistical timing results • With at-speed test, arbitrary performance vs. yield tradeoffs can be made based on business needs © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 56 Possible microprocessor methodology Individual macros Assertions (Mostly) FEOL variability models Other macros (Mostly) BEOL variability models © Chandu Visweswariah, 2004 Robustness budget Update timing and robustness budgets Statistical timing for optimization “Sign-off” statistical timing and abstraction Global wires Unit or chip-level statistical timing for optimization Unit or chip-level statistical “sign-off” timing Statistical Timing of Digital Integrated Circuits 57 Probability Vt variations Good chips Too leaky Too slow Vt • Requires simultaneous power/timing sign-off © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 58 Technology Technologycharacterization characterization ++delay delaymodel modelgeneration generation Canonical Canonicalvariational variational delay delaymodel model MHC, line tailoring Model-to-hardware Model-to-hardwarecorrelation correlation and/or and/orline linetailoring tailoring Statistical Statisticaltiming timing Path Pathreport reportfile filewith withcriticality criticality probabilities probabilities++process processcoverage coverage Test Testvector vectorgeneration generation Path Pathsensitivities sensitivities Correlation Correlationanalysis analysis and anddiagnosis diagnosis At-speed At-speedtest test Good Goodchips chips © Chandu Visweswariah, 2004 Bad Badchips chipswith withfailing failing path pathsignatures signatures Statistical Timing of Digital Integrated Circuits 59 They say an exercise in cryptology Is easier than defining a methodology; If we leave out statistical timing, dude, Our products will all be … (spoilt) © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 60 Propositions 1. Variability is proportionately increasing; therefore, a new paradigm is required 2. Correlations matter 3. Statistical timing tools are rising to the challenge 4. Robustness is an important metric 5. Statistical treatment of variability will pervade all aspects of chip design and manufacturing • ASICs and processors will both benefit © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 61 Quotable quotes* • Statistical thinking will one day be as necessary for efficient (chip-design) citizenship as the ability to read and write. -- H. G. Wells • There are three kinds of lies: lies, damned lies and statistics. -- Disraeli • It ain’t so much the things we don’t know that get us in trouble. It’s the things we know that ain’t so. -- Artemus Ward • Round numbers are always false. -- Samuel Johnson *From “How to Lie with Statistics,” by Darrell Huff, Norton, 1954 © Chandu Visweswariah, 2004 Statistical Timing of Digital Integrated Circuits 62