Design Guide for LLC Converter with ICE2HS01G

Application Note, V1.0, July 2011
Design Guide for LLC Converter
with ICE2HS01G
Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
Edition 2011-07-06
Published by Infineon Technologies Asia Pacific,
168 Kallang Way,
349253 Singapore, Singapore
© Infineon Technologies AP 2010.
All Rights Reserved.
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Design Guide for LLC Converter with ICE2HS01
Revision History:
Previous Version:
2011-07
NA
Design Guide for LLC Converter with ICE2HS01G
License to Infineon Technologies Asia Pacific Pte Ltd
Liu Jianwei
Li Dong
V1.0
AN-PS0057
Page
Table of Content
1 Abstract............................................................................................. 5 2 Design Procedure ............................................................................ 5 2.1 Target Specifications .................................................................................................................... 5 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.4 2.4.1 Design of Power Stage ................................................................................................................. 6 System specifications...................................................................................................................... 6 Selection of resonant factor m ........................................................................................................ 6 Voltage gain .................................................................................................................................... 7 Transformer turns ratio.................................................................................................................... 7 Effective load resistance ................................................................................................................. 7 Resonant network ........................................................................................................................... 7 Transformer design ......................................................................................................................... 9 SR MOSFET ................................................................................................................................. 10 Design of Control Parameters and Protections ....................................................................... 10 Frequency setting: ......................................................................................................................... 10 Minimum/Maximum frequency setting: ......................................................................................... 10 Frequency setting for OCP:........................................................................................................... 11 Dead time ...................................................................................................................................... 12 Softstart time, OLP blanking time and auto-restart time ............................................................... 13 Load pin setting ............................................................................................................................. 13 Current sense ................................................................................................................................ 13 VINS pin setting ............................................................................................................................ 15 Latch off function and burst mode selection ................................................................................. 15 Design of Synchronous Rectification (SR) control ................................................................. 16 On-time control - SRD pin and CL pin ..........................................................................................18 2.4.2 Turn-on delay Ton _ delay - Vres pin ................................................................................................. 20 2.4.3 Advanced Turn off delay Toff _ delay - Delay pin .............................................................................. 21 2.4.4 2.4.5 2.5 A review of the control scheme ..................................................................................................... 21 SR Protections .............................................................................................................................. 22 Design summary ......................................................................................................................... 22 3 Tips on PCB layout ........................................................................ 24 3.1 Star connection for Power stage ...............................................................................................24 3.2 Star connection for IC................................................................................................................. 25 Application Note
4
2011-07-06
1
Abstract
ICE2HS01G is our 2nd generation half-bridge LLC controller designed especially for high efficiency with its
synchronous rectification (SR) control for the secondary side. With its new driving techniques, SR can be
realized for half-bridge LLC converter operated with secondary switching current in both CCM and DCM
conditions. No individual SR controller IC is needed at the secondary side.
A typical application circuit of ICE2HS01G is shown in Figure 1. For best performance, it is suggested to use
half-bridge driver IC in the primary side with ICE2HS01G.
RINS1
CBUS
HV
QPH
RINS2
QSH
Lres
RINS3
HV IC
QPL
VCC
CVCC
GND VCC
Rdelay
CS
RCS1
CL
RCL
ICE2HS01G SRD
Rres1
CCL
RBA2
RSRD
ROVS2
QSRD
Vmc
ROVS1
IC Driver
TD
Vref
QSL
DCS2
RTD
Rmc1
RCS2 CCS2 DCS1
EnA
CEnA
QS1
SHG
Pulse
Trans.
QS2
Rmc2
Vres
Rres2
Timer SS
FREQ
LOAD
Figure 1
CSS
RSS1
CSS1
Coc
RBA1
QS4
Rreg
RFMIN
IC Driver
QS3
RFT1
RT
Roc
SLG
ROCP
CT
Vout
CCS1
VINS HG LG
Delay
REnA
CO1CO2
CRES
OPTO
RFT2
TL431
ROVS3
Typical application circuit
In this application note, the design procedure for LLC resonant converter with ICE2HS01 is presented,
together with an example of a 300W converter with 400VDC. Detailed calculation of the values of the
components around the IC is also included, together with tips on the PCB layout.
2
Design Procedure
2.1
Target Specifications
Application Note
5
2011-07-06
The design example is based on the typical application circuit in Figure 1, where individual resonant
choke is implemented. The target specifications are summarized in Table 1.
Input voltage Vin
400VDC
Output voltage and current Vo , I o
12VDC, 25A
Output power Pin
~ 300W
Efficiency η
>96% at 100% load
>97% at 50% load
>96% at 20% load
Resonant frequency f r
85kHz
Hold up time Th
20ms
Bulk capacitor C out
270uF
Table 1
Target application specifications
2.2
Design of Power Stage
2.2.1
System specifications
The maximum input power can be calculated as:
Pin =
VO * I O
η
=
12 * 25
= 312.5W
0.96
[1]
Based on the required 20ms hold-up time, the minimum input voltage can be given as:
2
Vin _ min = Vin _ nom −
2.2.2
2 Pin Th
2 * 312.5 * 20 * 10 −3
= 400 2 −
= 337.2V
C out
270 *10 −6
[2]
Selection of resonant factor m
In order to achieve the highest efficiency possible, the value of resonant factor m =
Lp
Lr
=
Lm + Lr
is to
Lr
be set as big as possible, so that the magnetizing inductance Lm is big and therefore magnetizing current
is small, which results in low core loss and conduction loss. On the other hand, the magnetizing current
should be big enough to discharge the C ds of primary side MOSFET during the transitions, to realize
ZVS to ensure safe switching and save switching loss. In this design example, m = 13 is selected as a
start. The ZVS of primary side MOSFET will be confirmed later with the determination of the deadtime of
switching.
Application Note
6
2011-07-06
2.2.3
Voltage gain
It is for efficiency optimization to operate the LLC converter around the resonant frequency at nominal
input voltage, where the voltage gain M nom = 1 , on condition that the secondary-side leakage inductance
is neglected due to the implementation of individual resonant choke.
The worst case we need to consider for resonant network and transformer design is the full load
operation at minimum input voltage Vin _ min . The maximum voltage gain at Vin _ min can be calculated as:
Vin _ nom
M max =
Vin _ min
2.2.4
M nom =
400
*1 = 1.19
337.2
[3]
Transformer turns ratio
Assuming the drain-source voltage drop of secondary-side MOSFET V f
= 0.1V , the transformer turns
ratio will be:
n=
Vin _ nom
2(Vo + V f )
2.2.5
M nom =
400
*1 = 16.5
2 * (12 + 0.1)
[4]
Effective load resistance
The effective load resistance can be given as:
Reff =
8
π
2
n2
2.2.6
Vo
8
12
= 2 * 16.5 2 *
= 106Ω
Io π
25
[5]
Resonant network
Defining the normalised frequency to f r is F
=
f
, the load factor of the LLC converter is
fr
Lr
Q=
Cr ,
Reff
the voltage gain of the converter can be written as:
Mj ( F , Q) =
F 2 (m − 1)
( F 2 m − 1) + jF ( F 2 − 1)(m − 1)Q
[6]
Its magnitude is:
G ( F , Q) = Re( Mj ( F , Q)) 2 + Im(Mj ( F , Q)) 2
The graph of voltage gain G Vs
Application Note
[7]
F for different Q can be plotted based on [7] with Mathcad:
7
2011-07-06
1.5
1.413
G( F , 0.22 )
1.325
G( F , 0.267 )
G( F , 0.3 )
1.238
G( F , 0.35 )
G( F , 0.5 )
1.15
G( F , 0.65 )
G( F , 0.8 )
1.063
Line
0.975
0.888
0.8
0.2
0.35
0.5
0.65
0.8
0.95
1.1
1.25
1.4
F
Figure 2
Voltage gain G Vs normalized frequency F
Among the curves, we find that the one with Q = 0.267 can achieve the required peak gain G pk , which
is 8% higher than M max for design margin, i.e.
G pk = 1.08M max = 1.28
From the curve, the corresponding Fmin = 0.35 can be located where G pk = 1.28 is achieved.
Having found the proper Q , we can calculate the C r , Lr and L p as follows:
Cr =
1
1
=
= 66nF
2π * Q * f r * Reff
2π * 0.268 * 85 * 10 3 * 106
[8]
Lr =
1
1
=
= 53uH
2
3 2
(2π * f r ) * C r (2π * 85 * 10 ) * 66 *10 −9
[9]
L p = mLr = 690uH
2.2.6.1
Resonant choke design
The minimum rms voltage across the resonant network is:
Vin _ rms _ min =
2
π
Vin _ min =
2
π
* 337.2 = 151.79V
Then the corresponding rms current flowing through the resonant choke
Application Note
8
[10]
Lr
can be calculated as:
2011-07-06
I in _ rms _ max =
Pin
η * Vin _ rms _ min
=
300
= 2.06 A
0.96 * 151.79
I r _ pk = 2 * I r _ rms = 2.91 A .
The peak current is
[11]
The OCP level is set with about 20% margin:
I ocp _ pk = 1.2 * I r _ pk = 3.49 A
The actual leakage inductance ( Lleak ) measured at primary side with one of the secondary side winding
shorted is around 13uH. Therefore, the inductance for the independent resonant choke is:
Lr _ choke = Lr − Lleak = 40uH
If a magnetic core with specs of RM10/PC95 is selected, where Ae _ min = 90mm , and
2
Bmax is selected
to be 0.08T to reduce core loss, the minimum turns can be given as:
N L min =
2.2.7
Lr _ choke ⋅ I r _ pk
BL max ⋅ AL min
=
40 *10 −6 * 3.49
= 19.4
0.08 * 90 *10 −6
[12]
Transformer design
From Figure 2, the normalized frequency Fmin = 0.35 has been located to achieve maximum gain
G pk = 1.28 . Accordingly the actual minimum frequency f min is:
f min = F * f r = 0.35 * 85 *10 3 = 30kHz
The voltage across the primary winding can be calculated as V p = n(Vo + V f ) . The half switching cycle
period is around: t =
n(Vo + V f )
2 f min
1
. According to Faraday’s law:
2 f min
= N p Ae ΔB
The minimum number of turns at primary side can be found:
N p min =
n(Vo + V f )
[13]
2 f min * Ae ΔB
Where Ae = 161mm with PQ3230 core. ΔB = 0.62T is selected to avoid magnetic saturation.
2
Then N p min can be calculated as:
N p min =
16.5 * (12 + 0.1)
= 33
2 * 30 *10 3 * 161 *10 −6 * 0.62
The number of turns at primary side is selected as
N p min = 33 . The secondary side turns can be
calculated accordingly:
Application Note
9
2011-07-06
Ns =
Np
=2
n
2.2.8
SR MOSFET
The voltage stress on the drain-source of the MOSFET is:
Vds = (Vo + V f ) * 2 = 24.2V
The RMS value of the current flowing through each MOSFET is:
I d _ rms =
π
4
I o = 19.63 A
2.3
Design of Control Parameters and Protections
2.3.1
Frequency setting:
The IC internal circuit provides a regulated 2V voltage at FREQ pin. The effective resistance presented
between the FREQ pin and GND, determines the current flowing out of the FREQ pin, which in turn
defines the switching frequency.
Figure 3 shows the curve illustrating the relationship of Switching Frequency FREQ Vs Effective
Resistor R FREQ connected between the FREQ pin and gound.
Figure 3
FREQ Vs Effective Resistor R FREQ
2.3.2
Minimum/Maximum frequency setting:
Application Note
10
2011-07-06
As discussed in section 2.2.7, the lowest switching f min will be seen in full load operation at Vin _ min . In this
section, how the f min is actually set by the IC is explained.
Based on the definition of oscillator as in the datasheet and the external circuit around pin FREQ in
Figure 1, the minimum switching frequency will be achieved when pin SS is 2V (usually after softstart),
opto-coupler transistor is open and only R F min is connected to pin FREQ. For f min = 30kHz , the
corresponding R FREQ found from Figure 3 is 50kΩ. A standard value resistor of 51kΩ is selected
for R F min .
The maximum operation frequency can possibly be seen when maximum input voltage, say 425V, is
applied, and the converter run in no load condition ( Q = 0 ), if burst mode is disabled. The gain in this
condition can be given as:
M min =
Vin _ nom
Vin _ max
M nom =
400
* 1 = 0.94
425
[14]
From the gain equation, we get:
F 2 (m − 1)
G ( F , Q) =
= M min , (Q = 0)
( F 2 m − 1)
[15]
The corresponding normalized frequency Fmax can be found by:
F=
1
= 2.13
1 − m + mM min
Therefore f max = F * 85kHz = 180kHz .
For 180 kHz switching frequency, the corresponding equivalent resistance Req at FREQ pin is 7.5kΩ
according to Figure 3. Under no load normal operation, pin SS is already 2V after soft start, and collector
of opto-coupler transistor is pulled to ground, therefore
Req = R FMIN // Rreg
The Rreg is calculated to be 8.8kΩ. A standard value resistor of 8.2kΩ is selected for the actual design.
2.3.3
Frequency setting for OCP:
Assuming the maximum rms current during over-current should be limited by the IC to 1.2 times the
maximum normal operation, i.e.
I ocp _ rms = 1.2 I in _ rms _ max = 1.2 * 2.06 = 2.47 A
The corresponding impedance of the resonant network during over-current can be estimated as:
Z ocp =
Vin _ rms
I ocp
=
400 * 2
= 73Ω
π * 2.47
[16]
During over-current, the load impedence is considered to be shorted, and thereofore the impedance of
the resonant network can be calculated as:
Z ocp = j * 2πf ocp * Lr +
Application Note
1
1
= 2πf ocp * Lr −
j * 2πf ocp * C r
2πf ocp * C r
11
[17]
2011-07-06
Solve the equation and find f ocp = 250kHz
Then Req is 5kΩ according to Figure 3. According to the definition of over-current protection,
Req = R FMIN // Rocp ,
Then Rocp can be found as 5.6kΩ.
2.3.4
Dead time
The dead time selection should ensure ZVS of two primary-side MOSFET IPA60R199CP at maximum
switching frequency, where the magnetizing current to charge and discharge C ds is the minimum. The
magnetizing current at the end of each switching cycle can be calculated as:
I mag min =
(VO + Vds ) * N e
(12 + 0.1) * 16.5
=
= 0.288 A
4 L p f ocp
4 * 690 *10 −6 * 250 *10 3
[18]
The required time to charge and discharge the C ds is:
TDEAD
2C dsVinnom 2C dsVinnom 2 *160 * 10 −12 * 400
=
=
=
= 440ns
I mag min
I mag min
0.288
[19]
Then RTD is around 270kΩ according to Figure 4.
Figure 4
TDEAD Vs RTD
Application Note
12
2011-07-06
2.3.5
Softstart time, OLP blanking time and auto-restart time
According to the definition of the softstart of the IC in the datasheet, soft start is implemented by
sweeping the operating frequency from an initial high value until the control loop takes over. The softstart
time depends on a few components, such as the R F min , the value of Rocp and the value of C SS . For a
20ms target rising time of the output voltage, the customer can start with C SS = 2.2uF .
The Timer pin is used to set the blanking time TOLP and restart time Trestart for over load protection. The
RC parallel circuit, CT and RT , are connected to this pin. Based on the definition in the datasheet, the
OLP blanking time with RT = 1MΩ and CT = 1uF can be calculated as:
TOLP = 20ms − RT * CT * ln(1 −
VTH
4
) = 20 − 1000 * 10 6 * 10 −6 * ln(1 − 6
) = 240ms
RT * I BL
10 * 20 * 10 −6
The restart time can be calculated as:
Trestart = − RT * CT * ln(
2.3.6
VTL
0.525
) * 1000 = 2030ms
) = −10 6 * 10 −6 * ln(
VTH
4
Load pin setting
One of the functions of the LOAD pin is to detect the over-load or open-loop faults. Once the voltage at this pin
is higher than 1.8V, IC will start internal and external timer and determine the entering of protection mode. The
resistor divider R FT 1 and R FT 2 should be designed properly to ensure OLP is functional as required. The
bottom resistor
R FT 2 connected to GND pin should be far bigger than the R FMIN , in order not to affect normal
regulation. As an example, assuming R FT 2 = 2 MΩ , the target voltage at Load pin is 1.82V when
overload happens. The reference voltage at frequency pin is 2V. Then the voltage at LOAD pin
R FT 2
* 2 = 1.82V
[20]
R FT 1 + R FT 2
We can find R FT 1 = 0.2 MΩ . A small capacitor of 1nF is usually connected to decouple noise at LOAD
V LOAD =
pin.
2.3.7
Current sense
Application Note
13
2011-07-06
Figure 5
Current sense circuit
Assuming capacitive current divider is adopted as current sense circuit. So C cs1 is chosen to be far less
than C r ,e. g, around C r / 100 , say 470pF. Rcs1 is normally of a few hundred Ω for filtering purpose, say
200Ω.
We can obtain the following equation considering C cs1 and Cr as current divider:
I Ccs1 = I ocp
C cs1
C
≈ I ocp cs1
C cs1 + C r
Cr
[21]
One major design criterion for the current sense is to ensure Over-Current Protection (OCP). Accordingly,
we can also obtain:
I Ccs1 =
π
2
I Rcs 2 =
π
0.8
2 Rcs 2
*
[22]
where 0.8V is the OCP first level.
Then we get:
Rcs 2 =
C
0.8π
0.8π
66 *10 −9
* r =
*
= 70Ω
2 * I ocp Ccs1 2 * 2.47 470 *10 −12
[23]
Rcs2 is chosen as 68Ω.
C cs 2 is selected so that the current loop speed is fast enough and the ripple on CS pin is around 20% of
1
the average value. Rcs 2 * C cs 2 is around
.
f min
1
1
Ccs 2 ≈
=
= 490nF
Rcs 2 * f min 68 * 30 *10 3
Application Note
14
2011-07-06
2.3.8
VINS pin setting
The minimum operation input voltage needs to be specified for LLC resonant converter with the Vins pin.
The typical circuit of mains input voltage sense and process is shown Figure 6.
Figure 6
Mains input voltage sense
The mains input voltage is divided by
RINSH and R INSL . With the internal current source I hys is
connected between VINS and Ground, an adjustable hysteresis between the on and off input voltage can
be created as
Vhys = I hys * RINSH
[24]
Assuming the turn-on bus voltage
typically.The
RINSH =
R INSL =
VINon is 380V typically and the turn-off bus voltage V INoff is 320V
R INSH and R INSL can be calculated as:
VINon − VINoff
I INS
=
380 − 320
= 6MΩ
10 *10 −6
[25]
Vth RINSH
1.25 * 6 * 10 6
=
= 23.5kΩ
Vinoff − Vth
320 − 1.25
A standard resistor value for
[26]
R INSL is 24kΩ.
The blanking time for leaving brown-out is around 500μs and for entering brown-out is around 50μs.
Please note that the calculation above is based on typical specification values of the IC.
2.3.9
Latch off function and burst mode selection
Internally, the EnA pin has a pull-up current source of 100μA. By connecting a resistor outside from this
pin to ground, certain voltage level is set up on this pin. If the voltage level on this pin is pulled down
below certain level during operation, IC is latched. If the external resistor has a negative temperature
coefficient, this pin can be used to implement over- temperature protection (OTP). In this design, R EnA is
selected at 1MΩ to set the pin voltage to be 2V level and no OTP is designed.
Application Note
15
2011-07-06
In addition to the latch-off enable function, this pin is also built for the selection of burst mode enable or
not during configuration before softstart. If the burst mode is enabled, the gate drives will be disabled if
LOAD pin voltage falls below 0.12V. However, if burst mode is not selected, the gate drives will not be
stopped by LOAD pin voltage.
The selection block works only after the first time IC VCC increases above UVLO. After CVCC is higher
than turn on threshod, a current source I sele , in addition to the I EnA , is turned on to charge the capacitor
C EnA . After 26μs, IC will compare the voltage on EnA pin and 1.0V, if voltage on EnA pin is higher than
1.0V, the burst mode function will be enabled. As the voltage on EnA pin depends on R EnA and C EnA , by
selecting different capacitance value, whether this IC works with burst mode can be decided.
With R EnA = 1MΩ and C EnA = 1nF , the voltage at EnA pin at the time of 26us can be calculated as:
VEnA = I sele * REnA (1 − e
−
26*10−6
RC
−6
) = 100 *10 *10 * (1 − e
Therefire burst mode will be enabled. If
6
−
26*10−6
106 *10−9
) = 2.56V > 1.0V
C EnA is set to be 10n F, V EnA = 0.26V < 1.0V @ 26us thus burst
mode will be disabled.
After the selection is done, the current source
I sele is turned off. A blanking time of 320μs is given before
IC starts to sense the EnA pin voltage latch off enable purpose. This blanking time is used to let the EnA
pin votlage be stablized to avoid mistriggering of Latch-off Enable function.
2.4
Design of Synchronous Rectification (SR) control
Synchronous Rectification (SR) in a half-bridge LLC resonant converter is one of the key factor to achieve
high efficiency. SR control is a major benefit we offer with our new LLC controller IC ICE2HS01G.
Before going into details of SR control of the IC, it’s necessary to understand the ideal SR switching
mechanism for two typical working conditions, i.e. when operation frequency( f sw ) is below ( f sw < f r )
and above the resonant frequency (
f sw > f r ).Figure 7 illustrates the waveforms of V HG (primary high side
gate), V LG (primary low side gate), VSHG ( secondary high side gate), VSLG (secondary low side gate),
I SH (current flowing through secondary high side MOSFET), I SL ( current flowing through secondary low
side MOSFET) and I PRI (current flowing through primary resonant tank).
Application Note
16
2011-07-06
Figure 7
Waveforms for LLC converter with
f sw > f r (left) and f sw < f r (right)
It can be seen from the waveforms in Figure 7 (left) that to ensure safe switching, the switch-on of the SR
MOSFET (see VSLG ) need to be a certain time AFTER the switch-on of the primary side switch(see V LG );
while switch-off of the SR MOSFET(see VSLG ) needs to be certain time BEFORE the switch-off of primary
side switch(see V LG ), in order to compensate the propagation delay of the gate signals from IC to the
actual MOSFET. In this operation condition (
f sw > f r ), the SR MOSFET conduction period (on-time)
depends on the primary gate switching frequency.
From Figure 7 (right), the current flowing through the SR MOSFET (see I SL ) goes to zero before the
switch-off of the primary switch. To avoid the current going into negative, the SR MOSFET need to be
turn off just before the current goes to zero. In this condition, the SR MOSFET on-time is almost constant
and nearly half of the resonant period.
The control of SR in ICE2HS01G consists of four main parts: on-time control, turn-on delay, advanced
turn-off delay and protections, with the block diagram shown in Figure 8.
Application Note
17
2011-07-06
Figure 8
Synchronous rectification control block diagram
2.4.1
On-time control - SRD pin and CL pin
With ICE2HS01’s control scheme, SR MOSFET ‘s turning-off depends on two conditions - turning-off of
the primary gate and the “off” instruction from SR on-time block, where the maximum on-time Ton _ max is
preset. Whichever “off” instruction comes first will trigger the turn-off of the SR MOSFET.
As illustrated in the previous chapter, the
Ton _ max depends on the resonant frequency when LLC
f sw < f r ). Considering the primary side dead time TDEAD
and the SR gate turn-on delay Ton _ delay ( will be discussed later section 2.4.2), we can preset Ton _ max with
converter operates below resonant frequency (
a safe value as below:
Ton _ max <
1
− TDEAD − Ton _ delay = 5.88 − 0.32 − 0.25 = 5.31us
2 f res
To achieve higher efficiency, a bigger
[27]
Ton _ max is an advantage, because bigger on-time means longer SR
MOSFET conduction time and less body diode conduction time, which reduces conduction loss. In actual
design, Ton _ max can be fine-tuned by looking at the similar waveforms in Figure 7, as long as safe
switching is guaranteed.
Application Note
18
2011-07-06
From Figure 9 below,
RSRD is selected to be 66kΩ to achieve Ton _ max = 5.31us . Usually customer
should start with a smaller SR on time for safety and then adjust it to achieve higher efficiency.
Figure 9
SR on time versus SRD resistance
A simple constant on time control does not provide the best efficiency of LLC HB converter for the whole
load range. In fact, the actual resonant period of secondary current reduces when the output load
decreases or input voltage increases. The primary winding current can reflects this change. The current
sense circuit can be designed to get such information and input to CS pin. In ICE2HS01G, a function
called current level (CL) pin is implemented. During heavy load and low input voltage, the CL pin voltage
( VCL ) is clamped at same voltage of SRD pin, 2V. Therefore, the SR on time in such conditions is
determined by RSRD only and is equal to
Ton _ max . In case of light load, with low CS voltage( VCS ), the
VCL is reduced to be lower than 2V and extra current will be drawn from SRD pin, thereby the actual SR
on time is reduced. The relationship between VCS and VCL is shown in Figure 10(top). The resistor RCL
can be adjusted to find the suitable reducing speed of SR on time for either better reliability or better
efficiency. RCL is normally around 10 times RSRD , which is 680kΩ in this design. Below is the detailed
calculation for the 300W design example:
We obtain the VCS for full load condition, based on the circuit in Figure 5:
Vcs =
2 Rcs 2 * I in _ rms _ max Ccs1 2 * 68 * 2.06 470 *10 −12
*
=
*
= 0.635V
Cr
66 *10 −9
π
π
The corresponding VCL is clamped at 2V according to Figure 10(top) and the SR on time is
Then for
Ton _ max .
VCS = 0.4V where VCL is exactly 2V, the corresponding load is 63% of the full load, which is
around 16A output current(Figure 10, bottom).
Application Note
19
2011-07-06
With
VCS < 0.4V, VCL starts to drop below 2V, extra current is drawn from SRD pin, thereby the actual
SR on time is reduced with the load decreased.
For filter purpose,
C CL is chosen to be 47nF.
Figure 10
SR on time versus SRD resistance
2.4.2
Turn-on delay Ton _ delay - Vres pin
When the input voltage is higher than resonant voltage, the LLC converter secondary switches are
working in CCM condition. Certain recovery time of the SR MOSFET body diode is required depending on
the current to turn-off. For better performance, the other SR MOSFET should be turn on after the
recovery phase. The turn-on delay function is built in ICE2HS01G for such purpose. When the sensed
input voltage at VINS pin is higher than the reference voltage set by Vres pin according to the resonant
voltage, SR turn-on delay is added, i.e, the SR MOSFETs are turn on 250ns after the corresponding
primary MOSFETs are turned on.
The nominal bus voltage at resonant point is:
Vres = 2n * (VO + V f ) = 2 * 16.5 * (12 + 0.1) = 399.3V
[28]
The corresponding voltage at VINS pin is 1.59V. To allow the turn-on delay for input voltage above this
resonant point, we can set the voltage divider Rres1 and Rres 2 connected at VRES pin accordingly. We
= 12kΩ , and Rres 2 can be calculated to be 5.2kΩ. To disable the turn-on delay during normal
operation, we can set the voltage at Vres to be 1.07x1.59=1.7V. Accordingly, Rres1 = 12kΩ ,
and Rres 2 = 6.2kΩ .
select Rres1
Application Note
20
2011-07-06
2.4.3
Advanced Turn off delay Toff _ delay - Delay pin
Advanced turn-off delay time of the SR MOSFET
Toff _ delay , normally is determined by the propagate
delay and transition time in the actual converter system. The value of
pin. For example, if the delay time required is 220ns, a
Toff _ delay can be set by the Delay
Rdelay = 33kΩ need to connect at Delay pin
according to the curve below.
Figure 11
Turn-off delay time versus Rdelay
2.4.4
A review of the control scheme
After all the SR related parameters have been set, such as maximum on-time
Ton _ max , turn-on
delay Ton _ delay , advanced turn-off delay Toff _ delay , simplified typical waveforms can be drawn in Figure 12
for the two conditions when
f sw > f r and f sw < f r .
From the waveforms on the left, the switch-on of the SR MOSFET is
Ton _ delay after the switch-on of the
primary side switch; while switch-off of the SR MOSFET is in advance with
Toff _ delay to the switch-off of
primary side switch. Under this operation condition, the SR MOSFET’s on-time changes with the primary
side MOSFET gate switching.
From the waveforms on the right, the SR MOSFET on-time is almost constant and equal to Ton _ max ,
which is independent of the primary side MOSFET turn-off.
In actual operation, the
f sw doesn’t have to be monitored. SR MOSFET will be turned off by whichever
signal comes first – the turning-off of the primary gate, or the falling edge of
Application Note
21
Ton _ max .
2011-07-06
Figure 12
Waveforms for LLC converter with
2.4.5
SR Protections
f sw > f r (left) and f sw < f r (right)
As the SR control in ICE2HS01G is realized with indirect method, there are some cases that the SR can
not work properly. In this cases, the SR gate drive will be disabled. Once the condition is over, IC will
restart the SR with SRSoftstart.
During softstart, the SR is disabled.When the softstart pin voltage is higher than 1.9V for 20ms, SR will be
enabled with SRSoftstart.
When LOAD pin voltage is lower than 0.2V, IC will disable the SR immediately. If LOAD pin voltage is
higher than 0.7V, IC will resume SR with SRSoftstart.
During over-current protection phase, if the softstart pin voltage is lower than 1.8V, SR will be disabled.
The SR will resume with softstart 10ms after SS pin voltage is higher than 1.9V again.
In over-current protection, if the CS pin voltage is higher than 0.9V, SR is disabled. SR will be enabled
with SRSoftstart after CS pin voltage is lower than 0.6V.
All the above four conditions are built inside the IC. If IC detects such a condition, IC will disable SR and
pull down the voltage on SRD pin to zero.
When the CS voltage suddenly drops from 0.55V to below 0.30V within 1ms, the SR gate is turned off for
1ms, after 1ms, SR operation is enabled again with SRsoftstart.
If some fault conditions are not reflected on the four conditions mentioned above but can be detected
outside with other measures, the SR can also be disabled and enabled with softstart from outside. This is
implemented on SRD pin as well. The internal SRD reference voltage has limited current source
capability. If a transistor QSRD is connected as shown in typical application circuit, the voltage on SRD
pin can be pulled to zero if this transistor is turned on, which will stop the SR. If the SRD voltage is
released and increases above 1.75V, SR is enabled with softstart.
2.5
Design summary
Figure 13 and 14 show the final schematic for the power stage and control circuit for the 300W LLC
converter.
Application Note
22
2011-07-06
C103
2n2/Y1
SGND
P_VBUS
RT100 5R
C100
+
S_HD
270uF/450V
P_PGND
P_HG
P_VCC
Q100
IPA60R199CP C102
33nF/630V
R100
10R
R101
10k
P_HS
Q101
015N04
S_HG
1R0
R103
10k
S_HS
L100
40uH//RM10
P_VCC
+
R102
TR100
PQ3230
12V
C104
10u/25V
P_SGND
C105
100n/25V
P_VCr
P_SGND
Q102
IPA60R199CP
R104
P_PLG
S_LD
C106
33nF/630V
10R
R107
R105
10k
S_LG
C107 +
C108 +
0m47/16V
0m47/16V
C109 +
C110 +
0m47/16V 0m47/16V
C111 +
0m47/16V
Q103
015N04
1R0
R108
10k
P_PGND
S_PGND
C112
100n
P_SHG
P_SLG
R110
R112
10R
NC
R109
10R
Q107
BC546
NC
D100
S_LS
R106
1N4148
12V
1k0
IC300
NC
Q106
BC557
R114 ZD100
430R 5V1
EE13
Q104
BC546
R111
TR101
Q105
BC557
D101
R113
1k0
1N4148
C113
1u0
C116
100n
NC
INA
OUTA
GND
VDD
INB
OUTB
12V
+ C121
10u
100n
3
1
2
C120
NC
R124
NC
+
1
C119
1u
R122
820
R125
3k6
IC101
TL431
Power stage circuit of the half-bridge LLC converter
R202 10R
R200
10R
R201
11k
P_VCC
C204
C205
100n
100n
OUT HVG Vboot
IC200
LIN
R203
11k
P_HG
LVG
P_VBUS
P_GND
P_VCC
P_LS
NC
P_LG
P_Vreg
Reg GND
P_HS
P_HG
NC
P_VCr
NC
NC
P_SLG
P_SHG
HIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
J?
GND
Figure 13
4
R117
3k9
C114 47n
2
C118
1n0
ZD102
9v1
R120
3k01
3
P_Vreg
2k2
R121
0R
R118
56R
C115
100p
S_LG
R116
560
R123
IC100
SFH617A-3
R119
11k
S_HG
C122
UCC27324_1
12V
R115 ZD101
430R 5V1
C117
10n
P_LG
C201
100n
P_HS
IC-ST-L6385
CON16R
P_Vreg
Figure 14
R219
NC
P_VCC
C207
C200
HG
100n
100n
SS
LG
LOAD
SHG
FREQ
SLG
Delay
GND
TD
SRD
Vmc
CL
Vref
IC201 CS
Vres
VINS
R223
R220
0R
P_SHG
P_VBUS
R224
R209 R211
154k/1%154k/1%
P_SLG
C208
R210
680k C206
47nF
470p/1kV
R212
200R
D201
1N4148
R225
1M5/1% 1M5/1%
R222
6k2
33k/1%
R215
2M0
C212
NC
R216
51k/1%
C210
1n0
C211
2.2u
R218
C203
820p
R217
NC
C209
1u
R214
1M0
R213
1M0
R205
0M2
R221
12k
R208
261k
R206 5k6/1%
VCC
EnA
P_VCr
R207 8k2/1%
Timer
R226
1M5/1% 1M5/1%
C213
R227
24k
10n
R228
68R
D202
1N4148
C214
470n
Control circuit of the half-bridge LLC converter
Application Note
23
2011-07-06
3
Tips on PCB layout
In order to avoid crosstalk on the board between power and signal path, and to keep the IC GND pin as
“clean” from noise as possible, the PCB layout must be taken care of properly. Below are some
suggestions as reference and customer can modify based on their own experience.
3.1
Star connection for Power stage
1. Connect IC VCC Ecap ground to both buck cap. ground and IC VCC ground (please refer to
the red curves in the circuit diagram below)
2. Connect driver IC input ground to IC VCC Ecap ground
3. Connect driver IC output ground to low side MOS source with short path
4. A 100nF filtering cap should be located just near IC VCC & IC GND (refer to the purple arrow)
5. The 100nF filtering cap ground should be inserted between VCC Ecap ground and IC ground
6. Connect driver IC VCC to VCC Ecap(refer to the green curve)
7. Connect driver IC high side output source to half bridge midpoint directly with short path
8. A 100nF filtering cap should be located just near driver IC VCC and IC GND(refer to the blue
arrow)
shorted
Figure 15
PCB layout tips
Application Note
24
2011-07-06
3.2
Star connection for IC
1. Connect the following ground directly back to Vcc 100nF cap ground (please refer to the red
curves in the circuit diagram below)
•
FREQ pin resistor ground
•
Delay pin resistor ground
•
SRD resistor ground
2. Connetc the following ground with R F min ground(refer to the green curves)
•
SS cap ground
•
Opto-coupler ground
3. Connect SR pulse transformer and driving circuit ground to VCC Ecap ground(refer to the yellow
curve)
4. Put 100nF ceramic cap to driver supply (refer to the blue arrow)
5. Connect all other ground using ground plane or ground track back to IC VCC 100nF cap ground
or VCC E cap ground
shorted
Figure 16
PCB layout tips
Application Note
25
2011-07-06
References
[1]
Infineon Technologies: ICE2HS01 - High Performance Resonant Mode Controller for Half-bridge
LLC Resonant Converter; datasheet Ver 2.0; Infineon Technologies; Munich; Germany; May. 2010.
Application Note
26
2011-07-06
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