Data Sheet

TDA8034HN
Low power smart card interface
Rev. 3.3 — 20 May 2015
Product data sheet
1. General description
The TDA8034HN is a cost-effective analog interface for asynchronous and synchronous
smart cards operating at 5 V, 3 V or 1.8 V. Using few external components, the
TDA8034HN provides all supply, protection and control functions between a smart card
and the microcontroller.
2. Features and benefits
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Integrated circuit smart card interface in an HVQFN24 package
5 V, 3 V or 1.8 V smart card supply
Very low power consumption in Deep Shutdown mode
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)
VCC regulation:
 5 V, 3 V or 1.8 V  5 % using two low ESR multilayer ceramic capacitors: one of
220 nF and one of 470 nF
 current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to
20 MHz, with controlled rise and fall times and filtered overload detection of
approximately 120 mA
Thermal and short-circuit protection for all card contacts
Automatic activation and deactivation sequences triggered by a short-circuit, card
take-off, overheating, falling VDD, VDD(INTF) or VDDP
Enhanced card-side ElectroStatic Discharge (ESD) protection of > 8 kV
External clock input up to 26 MHz connected to pin XTAL1
Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with
synchronous frequency changes of fxtal, 1⁄2 fxtal, 1⁄4 fxtal or 1⁄8 fxtal
Non-inverted control of pin RST using pin RSTIN
Compatible with ISO 7816, NDS and EMV 4.2 payment systems
Supply supervisor for killing spikes during power on and off:
 using a fixed threshold
 using an external resistor bridge with threshold adjustment
Built-in debouncing on card presence contacts (typically 8 ms)
Multiplexed status signal using pin OFFN
TDA8034HN
NXP Semiconductors
Low power smart card interface
3. Applications
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

Pay TV
Electronic payment
Identification
Bank card readers
4. Quick reference data
Table 1.
Quick reference data
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
power supply voltage
pin VDDP; regulator input
VCC = 5 V
4.85
5
5.5
V
VCC = 3 V and 1.8 V
3
3.3
5.5
V
2.7
3.3
3.6
V
Supply
VDDP
VDD
supply voltage
pin VDD
VDD(INTF)
interface supply voltage
pin VDD(INTF)
1.6
3.3
VDD + 0.3
V
IDD
supply current
shutdown mode
-
-
35
A
deep shutdown mode
-
-
12
A
active mode
-
-
2
mA
IDDP
IDD(INTF)
power supply current
interface supply current
shutdown mode; fxtal stopped
-
-
5
A
active mode; fCLK = 1⁄2 fxtal;
no load
-
-
1.5
mA
shutdown mode
-
-
6
A
active mode
-
-
2
mA
4.75
5.0
5.25
V
Card supply voltage: pin VCC[1]
VCC
supply voltage
active mode; ICC < 65 mA DC
5 V card
3 V card
2.85
3.05
3.15
V
1.8 V card
1.71
1.83
1.89
V
5 V card
4.65
5.0
5.25
V
3 V card
2.76
-
3.20
V
active mode; current pulses of
15 nA/s at ICC < 200 mA,
t < 400 ns; 1.8 V card
1.66
-
1.94
V
active mode; current pulses of
40 nA/s at ICC < 200 mA;
t < 400 ns
Vripple(p-p)
peak-to-peak ripple voltage
from 20 kHz to 200 MHz
-
-
350
mV
ICC
supply current
VCC = 0 V to 5 V, 3 V or 1.8 V
-
-
65
mA
tdeact
deactivation time
see Figure 8 on page 11
35
90
250
s
Ptot
total power dissipation
Tamb = 25 C to +85 C
-
-
0.25
W
Tamb
ambient temperature
25
-
+85
C
General
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Low power smart card interface
[1]
To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of
either 100 nF or one 220 nF and one 470 nF.
5. Ordering information
Table 2.
Ordering information
Type number
Package
TDA8034HN/C1
Name
Description
Version
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4  4  0.85 mm
SOT616-1
6. Block diagram
10 μF
100 nF
100 nF
VDD
VDDP
GND
12
17
16
VDD(INTF)
SUPPLY
R1
PORADJ 18
(1)
VOLTAGE
SENSE
R2
PRESN
INTERNAL
OSCILLATOR
INTERNAL
REFERENCE
CLKUP
ALARMN
EN1
8
VCC
LDO
PVCC
15 VCC
470 nF
RSTIN
CMDVCCN
OFFN
CLKDIV1
CLKDIV2
VCC_SEL2
VCC_SEL1
I/OUC
3
SEQUENCER
EN4
5
19
6
AUX2UC
14 RST
CLOCK
GENERATOR
13 CLK
EN3
LEVEL
SHIFTER
CLOCK
CIRCUIT
CLK
EN2
CARD
CONNECTOR
7
C5
C1
C6
C2
C7
C3
C8
C4
2
CRYSTAL
OSCILLATOR
4
THERMAL
PROTECTION
20
TDA8034HN
AUX1UC
RESET
GENERATOR
220 nF
I/O
TRANSCEIVER
9 I/O
10 AUX1
21
I/O
TRANSCEIVER
I/O
TRANSCEIVER
11 AUX2
22
1
100 nF
23
24
XTAL1
XTAL2
VDD(INTF)
001aal136
ALARMN, CLKUP, EN1, PVCC, EN4, EN3, EN2 and CLK are internal signals.
(1) Optional external resistor bridge, if not required connect pin PORADJ to VDD(INTF)
Fig 1.
Block diagram
TDA8034HN
Product data sheet
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Low power smart card interface
7. Pinning information
19 OFFN
20 I/OUC
21 AUX1UC
22 AUX2UC
terminal 1
index area
23 XTAL1
24 XTAL2
7.1 Pinning
VDD(INTF)
1
18 PORADJ
VCC_SEL2
2
17 VDD
RSTIN
3
VCC_SEL1
4
CMDVCCN
5
14 RST
CLKDIV1
6
13 CLK
16 VDDP
15 VCC
GND 12
9
I/O
AUX2 11
8
PRESN
AUX1 10
7
CLKDIV2
TDA8034HN
Transparent top view
Fig 2.
001aal137
Pin configuration
7.2 Pin description
Table 3.
Pin description
Symbol
Pin Supply
VDD(INTF)
1
VCC_SEL2 2
Type[1] Description
VDD(INTF) P
interface supply voltage
VDD(INTF) I
5 V or 3 V VCC voltage selection control signal:
active LOW: VCC = 3 V when pin VCC_SEL1 is HIGH
active HIGH: VCC = 5 V
3
VDD(INTF) I
microcontroller card reset input; active HIGH
VCC_SEL1 4
VDD(INTF) I
1.8 V VCC voltage selection control signal:
RSTIN
active LOW: VCC = 1.8 V
active HIGH: disables 1.8 V selection
CMDVCCN 5
VDD(INTF) I
microcontroller start activation sequence input; active LOW
CLKDIV1
6
VDD(INTF) I
sets the clock frequency on pin CLK in association with pin CLKDIV2; see Table 4
CLKDIV2
7
VDD(INTF) I
sets the clock frequency on pin CLK in association with pin CLKDIV1; see Table 4
PRESN
8
VDD(INTF) I
card presence contact input; active LOW[2]
I/O
9
VCC
I/O
card input/output data line (C7)[3]
AUX1
10
VCC
I/O
auxiliary card input/output data line (C4)[3]
AUX2
11
VCC
I/O
auxiliary card input/output data line (C8)[3]
GND
12
-
G
ground
CLK
13
VCC
O
card clock (C3)
RST
14
VCC
O
card reset (C2)
VCC
15
VCC
P
card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin VCC
and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 m
TDA8034HN
Product data sheet
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Low power smart card interface
Table 3.
Pin description …continued
Symbol
Pin Supply
Type[1] Description
VDDP
16
VDDP
P
low-dropout regulator input supply voltage
VDD
17
VDD
P
digital supply voltage
PORADJ
18
VDD(INTF) I
power-on reset threshold adjustment input using an optional external resistor bridge
OFFN
19
VDD(INTF) O
NMOS interrupt to microcontroller[4]; active LOW; see Section 8.10 on page 11
I/OUC
20
VDD(INTF) I/O
microcontroller input/output data line[5]
AUX1UC
21
VDD(INTF) I/O
auxiliary microcontroller input/output data line[5]
AUX2UC
22
VDD(INTF) I/O
auxiliary microcontroller input/output data line[5]
XTAL1
23
VDD
I
crystal connection input
XTAL2
24
VDD
O
crystal connection output
[1]
I = input, O = output, I/O = input/output, G = ground and P = power supply.
[2]
If pin PRESN is LOW, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter
this, the TDA8034HN has a built-in debouncing timer (typically 8 ms).
[3]
Uses an internal 11 k pull-up resistor connected to pin VCC.
[4]
Uses an internal 20 k pull-up resistor connected to pin VDD(INTF).
[5]
Uses an internal 10kW pull-up resistor connected to pin VDD(INTF)
8. Functional description
Remark: Throughout this document the ISO 7816 terminology conventions have been
adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
The power supply voltage ranges are as follows:
• VDDP: 4.85 V to 5.5 V when VCC_SEL2 is HIGH (VCC = 5 V)
• VDDP: 3 V to 5.5 V when VCC_SEL2 is LOW (VCC = 3 V) or when VCC_SEL1 is LOW
(VCC = 1.8 V)
• VDD: 2.7 V to 3.6 V
All interface signals to the system controller are referenced to VDD(INTF). All card contacts
remain inactive during power up or power down. After powering up the device, pin OFFN
remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power
down, pin OFFN goes LOW when VDDP falls below the falling threshold voltage (Vth).
The internal oscillator frequency (fosc(int)) is only used during the activation sequences.
When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low
frequency mode to reduce power consumption.
This device has a Low Drop-Off (LDO) voltage regulator connected to pin VCC, and is
used instead of a DC-to-DC converter. It ensures a minimum VCC of 4.75 V and that the
power supply voltage on pin VDDP does not fall below 4.85 V when pin VCC_SEL2 is
HIGH, for a maximum load current of 65 mA.
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
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Low power smart card interface
8.2 Voltage supervisor
VDD(INTF)
R1
PORADJ
R2
VDD
VDD
REFERENCE
VOLTAGE
VDDP
VCC_SEL2
001aal138
Fig 3.
Voltage supervisor circuit
The voltage supervisor monitors the voltage of the VDDP, VDD and VDD(INTF) supplies
providing both Power-On Reset (POR) and supply drop-out detection during a card
session. The supervisor threshold voltages for VDDP and VDD are set internally, and for
VDD(INTF) externally by pin PORADJ. As long as VDD is less than Vth + Vhys, the IC remains
inactive irrespective of the command line levels. After VDD has reached a level higher than
Vth + Vhys, the IC remains inactive for the duration of tw. The output of the supervisor is
sent to a digital controller in order to reset the TDA8034HN. This defined reset pulse of
approximately 8 ms, i.e. (tw = 1024  1⁄fosc(int)low), is used internally to maintain the IC in
the Shutdown mode during the supply voltage power on; see Figure 4. A deactivation
sequence is performed when either VDD, VDDP or VDD(INTF) falls below Vth.
Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int)
parameter.
Vth + Vhys
Vth
VDD
ALARMN
(internal signal)
tw
power on
tw
supply dropout
power off
001aak993
Fig 4.
TDA8034HN
Product data sheet
Voltage supervisor waveforms
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8.3 Clock circuits
The clock signal from pin CLK to the card is either supplied by an external clock signal
connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and
XTAL2. The TDA8034HN automatically detects if an external clock is connected to
XTAL1, eliminating the need for a separate pin to select the clock source.
Automatic clock source detection is performed on each activation command (falling edge
of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is
checked during a time window defined by the internal oscillator. If a clock is detected, the
internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator
is started. When an external clock is used, it is mandatory that the clock is applied to pin
XTAL1 before the falling edge of the signal on pin CMDVCCN.
DIGITAL
enclkin
clkxtal
MULTIPLEXER
CRYSTAL
XTAL1
XTAL2
001aak992
enclkin and clkxtal are internal signal names.
Fig 5.
Basic layout for using an external clock
The clock frequency is selected using pins CLKDIV1 and CLKDIV1 to be either fxtal, 1⁄2 fxtal
or 1⁄4 fxtal or 1⁄8 fxtal as shown in Table 4.
Remark: The levels on both pins must not be allowed to change simultaneously but
should be separated by a minimum of 10 ns.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of fxtal on pin CLK should be between 45 % and 55 %. If an external clock
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.
When the frequency of the clock signal on pin CLK is either fxtal, 1⁄2 fxtal, 1⁄4 fxtal or 1⁄8 fxtal,
the frequency dividers guarantee a duty cycle between 45 % and 55 %.
Table 4.
TDA8034HN
Product data sheet
Clock configuration
Pin CLKDIV1 level
Pin CLKDIV2 level
Pin CLK frequency
LOW
LOW
1⁄ f
8 xtal
LOW
HIGH
1⁄ f
4 xtal
HIGH
HIGH
1⁄ f
2 xtal
HIGH
LOW
fxtal
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Low power smart card interface
8.4 Input and output circuits
When pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and
VCC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is
referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC  VDD(INTF).
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay td,
the logic 0 present on the master-side is sent to the slave-side. When the master-side
returns logic 1, the slave-side sends logic 1 during time delay (tw(pu)). After this sequence,
both master and slave sides return to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8034HN
capable of delivering more than 1 mA, up to an output voltage of 0.9VCC, at a load of
80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the
internal pull-up resistor value and load current. The current sent to and received from the
card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
8.5 Shutdown mode
After a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode,
ensuring only the minimum number of circuits are active while the TDA8034HN waits for
the microcontroller to start a session.
• all card contacts are inactive. The impedance between the contacts and GND is
approximately 200 .
• pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 k pull-up
resistor connected to VDD(INTF)
• the voltage generators are stopped
• the voltage supervisor is active
• the internal oscillator runs at its lowest frequency (fosc(int)low)
8.6 Deep shutdown mode
When the smart card reader is inactive, the TDA8034HN will enter Deep shutdown mode
if pin CMDVCCN is forced HIGH and pins VCC_SEL1 and VCC_SEL2 are LOW. In Deep
shutdown mode, all circuits are disabled and pin OFFN follows the status of pin PRESN.
Changing the status of either pin CMDVCCN, VCC_SEL1 or VCC_SEL2 exits Deep
shutdown mode; see Figure 6.
TDA8034HN
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deactivation
sequence
CMDVCCN
VCC_SEL1
VCC_SEL2
shutdown
mode
(internal pin)
shutdown
activation
shutdown
deep shutdown
activation
debounce
OFFN
PRESN
VCC
001aal139
Fig 6.
Shutdown and Deep shutdown mode activation/deactivation
8.7 Activation sequence
The following device activation sequence is applied when using an external clock; see
Figure 7:
1. Pin CMDVCCN is pulled LOW (t0).
2. The internal oscillator is triggered (t0).
3. The internal oscillator changes to high frequency (t1).
4. VCC rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2).
5. Pins I/OUC, AUX1UC and AUX2UC are driven HIGH (t3).
6. The clock on pin CLK is applied to the C3 contact (t4).
7. Pin RST is enabled (t5).
Calculation of the time delays is as follows:
•
•
•
•
•
t1 = t0 + 384  1⁄fosc(int)low
t2 = t1
t3 = t1 + 17T / 2
t4 = driven by host controller; > t3 and < t5
t5 = t1 + 23T / 2
Remark: The value of period T is 64 times the period interval of the internal oscillator at
high frequency (1⁄fosc(int)high); t3 is called td(start) and t5 is called td(end).
TDA8034HN
Product data sheet
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CMDVCCN
XTAL1
VCC
I/O
ATR
CLK
> 200 ns
RSTIN
RST
I/OUC
OSCINT
low frequency
t0
high frequency
t1 = t2
t4
td(start)
td(end) = tact
001aal140
OSCINT = internal oscillator.
Fig 7.
Activation sequence at t3
8.8 Deactivation sequence
When a session ends, the microcontroller sets pin CMDVCCN HIGH. The TDA8034HN
then executes an automatic deactivation sequence by counting the sequencer back to the
inactive state (see Figure 8) as follows:
1. Pin RST is pulled LOW (t11).
2. The clock is stopped, pin CLK is LOW (t12).
3. Pins I/OUC, AUX1UC and AUX2UC are pulled LOW (t13).
4. VCC falls to 0 V (t14). The deactivation sequence is completed when VCC reaches its
inactive state.
5. VCC < 0.4 V (tdeac)
6. All card contacts become low-impedance to GND. However, pins I/OUC, AUX1UC
and AUX2UC remain pulled up to VDD using the 11 k resistor.
7. The internal oscillator returns to its low frequency mode.
Calculation of the time delays is as follows:
•
•
•
•
•
TDA8034HN
Product data sheet
t11 = t10 + 3T / 64
t12 = t11 + T / 2
t13 = t11 + T
t14 = t11 + 3T / 2
tdeac = t11 + 3T / 2 + VCC fall time
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Low power smart card interface
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.
 25 s).
CMDVCC
RST
CLK
I/O
VCC
XTAL1
low frequency
high frequency
OSCINT
t10 t11
t12
t13
t14
tdeact
001aak995
OSCINT = internal oscillator.
Fig 8.
Deactivation sequence
8.9 VCC regulator
The VCC buffer is able to continuously deliver up to 65 mA at VCC = 5 V, 3 V, or 1.8 V.
The VCC buffer has an internal overload protection with a threshold value of approximately
120 mA. This detection is internally filtered, enabling spurious current pulses up to
200 mA with a duration of a few milliseconds to be drawn by the card without causing
deactivation. However, the average current value must stay below maximum; see Table 8.
8.10 Fault detection
The following conditions are monitored by the fault detection circuit:
•
•
•
•
•
•
Short-circuit or high current on pin VCC
Card removal during transaction
VDDP falling
VDD falling
VDD(INTF) falling
Overheating
Fault detection monitors two different situations:
• Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in
the reader and HIGH if the card is in the reader. Any voltage drop on VDD is detected
by the voltage supervisor. This generates an internal power-on reset pulse but does
not act upon the pin OFFN signal. The card is not powered-up and short-circuits or
overheating are not detected.
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
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Low power smart card interface
• In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault
detection circuit triggers the automatic emergency deactivation sequence (see
Figure 9). When the microcontroller resets pin CMDVCCN to HIGH, after the
deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN
returns to HIGH. This check identifies the fault as either a hardware problem or a card
removal incident.
On card insertion or removal, bouncing can occur in the PRESN signal. This depends on
the type of card presence switch in the connector (normally open or normally closed) and
the mechanical characteristics of the switch. To correct for this, a debouncing feature is
integrated in to the TDA8034HN. This feature operates at a typical duration of 8 ms
(tdeb = 640  (1⁄fosc(int)low). Figure 10 on page 13 shows the operation of the debouncing
feature.
On card insertion, pin OFFN goes HIGH after the debounce time has elapsed. When the
card is extracted, the automatic card deactivation sequence is performed on the first
HIGH/LOW transition on pin PRESN. After this, pin OFFN goes LOW.
OFFN
PRESN
RST
CLK
I/O
VCC
XTAL1
high frequency
OSCINT
t10
Fig 9.
TDA8034HN
Product data sheet
t12
t13
tdeact
low frequency
t14
001aal141
Emergency deactivation sequence after card removal
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PRESN
OFFN
CMDVCCN
tdeb
tdeb
(1)
VCC
(2)
001aal411
(1) Deactivation caused by card withdrawal.
(2) Deactivation caused by short-circuit.
Fig 10. Operation of debounce feature with pins OFFN, CMDVCCN, PRESN and VCC
9. Limiting values
Remark: All card contacts are protected against any short-circuit to any other card
contact. Stress beyond the levels indicated in Table 5 can cause permanent damage to
the device. This is a short-term stress rating only and under no circumstances implies
functional operation under long-term stress conditions.
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDDP
power supply voltage
pin VDDP
0.3
+6
V
VDD
supply voltage
pin VDD
0.3
+4.6
V
VDD(INTF)
interface supply voltage
pin VDD(INTF)
0.3
+4.6
V
VI
input voltage
pins CMDVCCN, CLKDIV1, CLKDIV2,
VCC_SEL1, VCC_SEL2, RSTIN, OFFN,
PORADJ, XTAL1, XTAL2, I/OUC, AUX1UC,
AUX1UC
0.3
+4.6
V
card contact pins PRESN, I/O, RST, AUX1,
AUX2 and CLK
0.3
+6
V
55
+150
C
-
0.25
W
Tstg
storage temperature
Ptot
total power dissipation
Tj
junction temperature
-
+125
C
Tamb
ambient temperature
25
+85
C
VESD
electrostatic discharge voltage
Human Body Model (HBM) on card pins I/O,
RST, VCC, AUX1, AUX2, CLK; within typical
application
8
+8
kV
Human Body Model (HBM); all other pins(1)
2
+2
kV
Machine Model (MM); all pins
200
+200
V
Field Charged Device Model (FCDM); all
pins
500
+500
V
[1]
TDA8034HN
Product data sheet
Tamb = 25 C to +85 C
The PRESN pin supports ESD HBM discharge up to 7kV
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 20 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 30
TDA8034HN
NXP Semiconductors
Low power smart card interface
10. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Package name
Parameter
Conditions
Typ
Unit
Rth(j-a)
HVQFN24
thermal resistance from junction to ambient
in free air
53
K/W
11. Characteristics
Table 7.
Characteristics of IC supply voltage
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
power supply voltage
pin VDDP
VCC = 5 V
4.85
5
5.5
V
VCC = 3 V or 1.8 V
3
3.3
5.5
V
Supply
VDDP
VDD
supply voltage
2.7
3.3
3.6
V
VDD(INTF)
interface supply voltage pin VDD(INTF)
1.6
3.3
VDD + 0.3
V
IDD
supply current
shutdown mode
-
-
35
A
deep shutdown mode
-
-
12
A
active mode
-
-
2
mA
-
-
5
A
IDDP
pin VDD
power supply current
shutdown mode
fxtal stopped
active mode
IDD(INTF)
fCLK = 1⁄2 fxtal; no load
-
-
1.5
mA
fCLK = 1⁄2 fxtal; ICC = 65 mA
-
-
70
mA
-
-
6
A
-
-
2
mA
pin VDD falling
2.30
2.40
2.50
V
pin VDDP falling;
VCC = 5 V
3.00
4.10
4.40
V
1.20
1.24
1.29
V
pin VDD
50
100
150
mV
pin VDDP; VCC = 5 V
100
200
350
mV
5.1
8
10.2
ms
pin PORADJ < 0.5 V
0.1
+4
+10
A
pin PORADJ > 1 V
1
-
+1
A
550
-
830
nF
interface supply current shutdown mode
active mode
Vth
threshold voltage
no external resistors on pin
PORADJ
external resistors on pin
PORADJ
Vhys
hysteresis voltage
tw
pulse width
IL
leakage current
Card supply voltage: pin VCC
Cdec
no external resistors on pin
PORADJ
[1]
decoupling capacitance connected to VCC
TDA8034HN
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 20 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 30
TDA8034HN
NXP Semiconductors
Low power smart card interface
Table 7.
Characteristics of IC supply voltage …continued
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Vo
output voltage
Shutdown mode
no load
Min
Typ
Max
Unit
0.1
-
+0.1
V
0.1
-
+0.3
V
-
-
1
mA
5 V card
4.75
5.0
5.25
V
3 V card
2.85
3.05
3.15
V
1.8 V card
1.71
1.83
1.89
V
4.65
5.0
5.25
V
Io = 1 mA
Io
output current
Shutdown mode; pin VCC
connected to ground
VCC
supply voltage
active mode; ICC < 65 mA
DC
active mode; current pulses
of 40 nA/s at ICC < 200 mA;
t < 400 ns
5 V card
3 V card
Vripple(p-p) peak-to-peak ripple
voltage
ICC
supply current
SR
slew rate
2.76
-
3.20
V
active mode; current pulses
of 15 nA/s at ICC < 200 mA,
t < 400 ns;1.8 V card
1.66
-
1.94
V
20 kHz to 200 MHz
-
-
350
mV
VCC = 0 V to 5 V, 3 V or
1.8 V
-
-
65
mA
VCC shorted to ground
90
120
150
mA
5 V card
0.055
0.18
0.3
V/s
3 V card
0.040
0.18
0.3
V/s
1.8 V card
0.025
0.18
0.3
V/s
Crystal oscillator: pins XTAL1 and XTAL2
Cext
external capacitance
pins XTAL1 and XTAL2
(depending on the crystal or
resonator specification)
-
-
15
pF
fxtal
crystal frequency
card clock reference; crystal
oscillator
2
-
26
MHz
fext
external frequency
external clock on pin XTAL1
0
-
26
MHz
VIL
LOW-level input
voltage
crystal oscillator
0.3
-
+0.3VDD
V
external clock
0.3
-
+0.3VDD(INTF)
V
VIH
HIGH-level input
voltage
crystal oscillator
0.7VDD
-
VDD + 0.3
V
external clock
0.7VDD(INTF)
-
VDD(INTF) + 0.3
V
-
-
200
ns
200
-
400
ns
Data lines: pins I/O, I/OUC, AUX1, AUX2, AUXIUC and AUX2UC
td
delay time
tw(pu)
pull-up pulse width
fio
input/output frequency
on data lines
-
-
1
MHz
Ci
input capacitance
on data lines
-
-
10
pF
TDA8034HN
Product data sheet
falling edge on pins I/O and
I/OUC or vise versa
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TDA8034HN
NXP Semiconductors
Low power smart card interface
Table 7.
Characteristics of IC supply voltage …continued
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Data lines to the card: pins I/O, AUX1and
Vo
output voltage
Io
output current
VOL
LOW-level output
voltage
VOH
HIGH-level output
voltage
VIL
LOW-level input
voltage
VIH
HIGH-level input
voltage
Min
Typ
Max
Unit
AUX2[3]
Shutdown mode
no load
0
-
0.1
V
Io = 1 mA
0
-
0.3
V
Shutdown mode; pin I/O
grounded
-
-
1
mA
IOL = 1 mA
0
-
0.3
V
IOL  15 mA
VCC  0.4
-
VCC
V
no DC load
0.9VCC
-
VCC + 0.1
V
IOH < 40 A; 5 V or 3 V
0.75VCC
-
VCC + 0.1
V
IOH < 20 A; 1.8 V
0.75VCC
-
VCC + 0.1
V
IOH  15 mA
0
-
0.4
V
0.3
-
+0.8
V
VCC = 5 V
0.6VCC
-
VCC + 0.3
V
VCC = 3 V or 1.8 V
0.7VCC
-
VCC + 0.3
V
pin I/O
-
50
-
mV
Vhys
hysteresis voltage
IIL
LOW-level input current pin I/O; VIL = 0 V
-
-
600
A
IIH
HIGH-level input
current
pin I/O; VIH = VCC
-
-
10
A
tr(i)
input rise time
VIL maximum to
VIH minimum
-
-
1.2
s
tr(o)
output rise time
CL  80 pF; 10 % to 90 %;
0 V to VCC
-
-
0.1
s
tf(i)
input fall time
VIL maximum to
VIH minimum
-
-
1.2
s
tf(o)
output fall time
CL  80 pF; 10 % to 90 %;
0 V to VCC
-
-
0.1
s
Rpu
pull-up resistance
connected to VCC
7
9
11
k
Ipu
pull-up current
VOH = 0.9VCC; C = 80 pF
8
6
4
mA
Data lines to the system: pins I/OUC, AUX1UC and
AUX2UC[4]
VOL
LOW-level output
voltage
IOL = 1 mA
0
-
0.3
V
VOH
HIGH-level output
voltage
no DC load
0.9VDD(INTF)
-
VDD(INTF) + 0.1
V
IOH  40 A; VDD(INTF) > 2 V
0.75VDD(INTF) -
VDD(INTF) + 0.1
V
IOH  20 A; VDD(INTF) < 2 V
0.75VDD(INTF) -
VDD(INTF) + 0.1
V
VIL
LOW-level input
voltage
0.3
-
+0.3VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7VDD(INTF)
-
VDD(INTF) + 0.3
V
Vhys
hysteresis voltage
pin I/OUC
-
0.14VDD(INTF)
-
V
IIH
HIGH-level input
current
VIH = VDD(INTF)
-
-
10
A
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 30
TDA8034HN
NXP Semiconductors
Low power smart card interface
Table 7.
Characteristics of IC supply voltage …continued
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
IIL
Conditions
Min
Typ
Max
Unit
LOW-level input current VIL = 0 V
-
-
600
A
Rpu
pull-up resistance
connected to VDD(INTF)
8
10
12
k
tr(i)
input rise time
VIL maximum to
VIH minimum
-
-
1.2
s
tr(o)
output rise time
CL  30 pF; 10 % to 90 %;
0 V to VDD(INTF)
-
-
0.1
s
tf(i)
input fall time
VIL maximum to
VIH minimum
-
-
1.2
s
tf(o)
output fall time
CL  30 pF; 10 % to 90 %;
0 V to VDD(INTF)
-
-
0.1
s
Ipu
pull-up current
VOH = 0.9VDD; C = 30 pF
1
-
-
mA
Shutdown mode
100
150
200
kHz
active state
2
2.7
3.2
MHz
no load
0
-
0.1
V
Io = 1 mA
0
-
0.3
V
Internal oscillator
fosc(int)
internal oscillator
frequency
Reset output to the card: pin RST
Vo
output voltage
Shutdown mode
Io
output current
Shutdown mode; pin RST
grounded
-
-
1
mA
td
delay time
between pins RSTIN and
RST; RST enabled
-
-
2
s
VOL
LOW-level output
voltage
IOL = 200 A; VCC = 5 V
0
-
0.3
V
IOL = 200 A; VCC = 3 V or
1.8 V
0
-
0.2
V
current limit IOL = 20 mA
VCC  0.4
-
VCC
V
HIGH-level output
voltage
IOH = 200 A
0.9VCC
-
VCC
V
current limit IOH = 20 mA
0
-
0.4
V
tr
rise time
CL = 100 pF
-
-
0.1
s
tf
fall time
CL = 100 pF
-
-
0.1
s
no load
0
-
0.1
V
Io = 1 mA
0
-
0.3
V
VOH
Clock output to the card: pin CLK
Vo
output voltage
Shutdown mode
Io
output current
Shutdown mode; pin CLK
grounded
-
-
1
mA
VOL
LOW-level output
voltage
IOL = 200 A
0
-
0.3
V
current limit IOL = 70 mA
VCC  0.4
-
VCC
V
HIGH-level output
voltage
IOH = 200 A
0.9VCC
-
VCC
V
current limit IOH = 70 mA
0
-
0.4
V
rise time
CL = 30 pF
[5]
-
-
16
ns
CL = 30 pF
[5]
-
-
16
ns
VOH
tr
tf
fall time
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 30
TDA8034HN
NXP Semiconductors
Low power smart card interface
Table 7.
Characteristics of IC supply voltage …continued
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCLK
frequency on pin CLK
operational
0
-
20
MHz
45
-
55
%
VCC = 5 V
0.2
-
-
V/ns
VCC = 3 V or 1.8 V
0.12
-
-
V/ns

duty cycle
CL = 30 pF
SR
slew rate
rise and fall; CL = 30 pF
[5]
Control inputs: pins CLKDIV1, CLKDIV2, RSTIN, VCC_SEL1 and
VCC_SEL2[6]
VIL
LOW-level input
voltage
0.3
-
0.3VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7 VDD(INTF)
-
VDD(INTF) + 0.3
V
Vhys
hysteresis voltage
-
0.14VDD(INTF)
-
V
IIL
LOW-level input current VIL = 0 V
-
-
1
A
IIH
HIGH-level input
current
-
-
1
A
control input
VIH = VDD(INTF)
Control input: pin CMDVCCN[6]
VIL
LOW-level input
voltage
0.3
-
0.3VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7VDD(INTF)
-
VDD(INTF) + 0.3
V
Vhys
hysteresis voltage
-
0.14VDD(INTF)
-
V
IIL
LOW-level input current VIL = 0 V
-
-
1
A
IIH
HIGH-level input
current
-
-
1
A
-
-
100
Hz
5 V card
30
-
-
ms
3 V card
-
-
15
ms
control input
VIH = VDD(INTF)
fCMDVCCN frequency on pin
CMDVCCN
tw
pulse width
Card detection input: pin PRESN[6][7]
VIL
LOW-level input
voltage
0.3
-
0.3VDD(INTF)
V
VIH
HIGH-level input
voltage
0.7VDD(INTF)
-
VDD(INTF) + 0.3
V
Vhys
hysteresis voltage
-
0.14VDD(INTF)
-
V
IIL
LOW-level input current 0 V < VIL < VDD(INTF)
-
-
5
A
IIH
HIGH-level input
current
0 V < VIH < VDD(INTF)
-
-
5
A
-
0.3
V
pin PRESN
OFFN output[8]
VOL
LOW-level output
voltage
IOL = 2 mA
0
VOH
HIGH-level output
voltage
IOH = 15 A
0.75VDD(INTF) -
-
V
Rpu
pull-up resistance
connected to VDD(INTF)
16
24
k
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
20
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 30
TDA8034HN
NXP Semiconductors
Low power smart card interface
[1]
To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of
one 220 nF and one 470 nF.
[2]
Using decoupling capacitors of one 220 nF 20 % and one 470 nF 20 %.
[3]
Using the integrated 9 k pull-up resistor connected to VCC.
[4]
Using the integrated 10 k pull-up resistor connected to VDD(INTF).
[5]
The transition time and the duty factor definitions are shown in Figure 11 on page 19;  = t1 / (t1 + t2).
[6]
Pins PRESN and CMDVCCN are active LOW; pin RSTIN is active HIGH; see Table 4 for states of pins CLKDIV1 and CLKDIV2.
[7]
Pin PRESN has an integrated current source of 1.25 A to VDD(INTF).
[8]
Pin OFFN is an NMOS drain, using an internal 20 k pull-up resistor connected to VDD(INTF).
Table 8.
Protection characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOlim
output current limit
pin I/O
15
-
+15
mA
pin VCC
135
175
225
mA
pin CLK
70
-
+70
mA
pin RST
20
-
+20
mA
Isd
shutdown current
pin VCC
90
120
150
mA
Tsd
shutdown temperature
at die
-
150
-
C
Table 9.
Timing characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tact
activation time
see Figure 7 on page 10
2090
-
4160
s
tdeact
deactivation time
see Figure 8 on page 11
35
90
250
s
td
delay time
CLK sent to card using an external clock
td(start) = t3; see Figure 7 on page 10
2090
-
4112
s
td(end) = t5; see Figure 7 on page 10
2120
-
4160
s
3.2
4.5
6.4
ms
tdeb
debounce time
pin PRESN
tr
tf
90 %
VOH
90 %
(VOH + VOL) / 2
10 %
10 %
t1
VOL
t2
001aai973
Fig 11. Definition of output and input transition times
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
19 of 30
TDA8034HN
NXP Semiconductors
Low power smart card interface
12. Application information
VDD(INTF)
MICROCONTROLLER
VDD
CLKDIV1
OFFN
I/OUC
AUX1UC
2
17
3
16
TDA8034HN
4
15
5
14
GND
6
13
8
CLKDIV2
7
9 10 11 12
CARD
CONNECTOR
C5
C1
C6
C2
C7
C3
C8
C4
PORADJ
VDD
C2
VDD
VDDP
100 nF
VCC
RST
VDDP
CLK
C3
100 nF
GND
CMDVCCN
18
AUX2
RSTIN
VCC_SEL1
24 23 22 21 20 19
AUX1
VCC_SEL2
R2
1
I/O
100 nF
VDD(INTF)
PRESN
C1
AUX2UC
VDD(INTF)
XTAL1
XTAL2
R1
C4
10 μF
C6
220 nF
C5
470 nF
R4
0Ω
001aal142
Fig 12. Application diagram
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
20 of 30
TDA8034HN
NXP Semiconductors
Low power smart card interface
13. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT616-1
terminal 1
index area
A
A1
E
c
detail X
e1
C
1/2
e
e
12
y
y1 C
v M C A B
w M C
b
7
L
13
6
e
e2
Eh
1/2
1
e
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT616-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 13. Package outline SOT616-1 (HVQFN24)
TDA8034HN
Product data sheet
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Rev. 3.3 — 20 May 2015
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14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Product data sheet
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14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 14) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 11.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 14.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 14. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 12.
TDA8034HN
Product data sheet
Abbreviations
Acronym
Description
EMV
Europay MasterCard VISA
ESD
ElectroStatic Discharge
ESR
Equivalent Series Resistor
FCDM
Field Charged Device Model
HBM
Human Body Model
LDO
Low Drop-Out
MM
Machine Model
NMOS
Negative-channel Metal-Oxide Semiconductor
POR
Power-On Reset
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16. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice-
Supersedes
TDA8034HN v.3.3
20150520
Product data sheet
-
TDA8034HN v3.2
Modifications:
TDA8034HN v.3.2
Modifications:
TDA8034HN v.3.1
Modifications:
TDA8034HN v.3.0
Modifications:
TDA8034HN v.2.0
Modifications:
TDA8034HN_1
TDA8034HN
Product data sheet
•
•
Section 2 “Features and benefits”: ESD value updated
Table 5 “Limiting values”: VESD values updated
20140325
•
•
Product data sheet
-
TDA8034HN v.3.0
Table 1 “Quick reference data”: values added
Table 7 “Characteristics of IC supply voltage”: values added
Figure 1 “Block diagram”: Figure note (1) changed
Product data sheet
-
TDA8034HN v.2.0
Table 2 “Ordering information”: type number updated into TDA8034HN/C1
Table 3 “Pin description”: Table note [2] corrected
20101112
•
TDA8034HN v.3.1
Section 2 “Features and benefits”: typos corrected
20110117
•
•
-
Change of descriptive title
20110905
•
•
•
Product data sheet
Product data sheet
-
TDA8034HN_1
Table 3 “Pin description”:
Table note [4] VDD changed into VDD(INTF)
Table note [5] added
IOUC, AUX1UC, AUX2UC referenced to new note [5]
20100205
Product data sheet
-
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-
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TDA8034HN
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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19. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Clock configuration . . . . . . . . . . . . . . . . . . . . . .7
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13
Thermal characteristics . . . . . . . . . . . . . . . . . .14
Characteristics of IC supply voltage . . . . . . . .14
Protection characteristics . . . . . . . . . . . . . . . .19
Timing characteristics . . . . . . . . . . . . . . . . . . .19
SnPb eutectic process (from J-STD-020D) . . .23
Lead-free process (from J-STD-020D) . . . . . .23
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision history . . . . . . . . . . . . . . . . . . . . . . . .25
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Product data sheet
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20. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4
Voltage supervisor circuit . . . . . . . . . . . . . . . . . . . .6
Voltage supervisor waveforms . . . . . . . . . . . . . . . .6
Basic layout for using an external clock. . . . . . . . .7
Shutdown and Deep shutdown mode
activation/deactivation . . . . . . . . . . . . . . . . . . . . . .9
Activation sequence at t3. . . . . . . . . . . . . . . . . . .10
Deactivation sequence . . . . . . . . . . . . . . . . . . . . 11
Emergency deactivation sequence after card
removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operation of debounce feature with pins OFFN,
CMDVCCN, PRESN and VCC . . . . . . . . . . . . . . .13
Definition of output and input transition times . . .19
Application diagram . . . . . . . . . . . . . . . . . . . . . . .20
Package outline SOT616-1 (HVQFN24) . . . . . . .21
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
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Product data sheet
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21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
17.4
18
19
20
21
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 6
Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Input and output circuits . . . . . . . . . . . . . . . . . . 8
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 8
Deep shutdown mode. . . . . . . . . . . . . . . . . . . . 8
Activation sequence . . . . . . . . . . . . . . . . . . . . . 9
Deactivation sequence . . . . . . . . . . . . . . . . . . 10
VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . 11
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal characteristics . . . . . . . . . . . . . . . . . 14
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information. . . . . . . . . . . . . . . . . . 20
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Soldering of SMD packages . . . . . . . . . . . . . . 22
Introduction to soldering . . . . . . . . . . . . . . . . . 22
Wave and reflow soldering . . . . . . . . . . . . . . . 22
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Contact information. . . . . . . . . . . . . . . . . . . . . 27
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 20 May 2015
Document identifier: TDA8034HN
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