INTERSIL 5962F9860201VXC

ACS05MS
Data Sheet
Radiation Hardened Hex Inverter with
Open Drain Outputs
The Radiation Hardened ACS05MS is a Hex Inverter with
open drain outputs. This device inverts a HIGH level on each
input to a LOW level on the corresponding Y output. A LOW
level on the input causes the corresponding Y output to enter
a high impedance state, which can be pulled HIGH through a
resistor to VCC . All inputs are buffered and the outputs are
designed for balanced propagation delay and transition times.
November 1998
File Number
4542
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD (Si)
- SEU Immunity . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm2)
The ACS05MS is fabricated on a CMOS Silicon on Sapphire
(SOS) process, which provides an immunity to Single Event
Latch-up and the capability of highly reliable performance in
any radiation environment. These devices offer significant
power reduction and faster performance when compared to
ALSTTL types.
• Input Logic Levels. . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Applications
Detailed Electrical Specifications for the ACS05MS are
contained in SMD 5962-98602. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MKT. NUMBER
5962F9860201VCC
ACS05DMSR-03
ACS05D/SAMPLE-03
ACS05D/SAMPLE-03
5962F9860201VXC
ACS05KMSR-03
ACS05K/SAMPLE-03
5962F9860201V9A
TEMP. RANGE (oC)
PACKAGE
DESIGNATOR
-55 to 125
14 Ld SBDIP
CDIP2-T14
25
14 Ld SBDIP
CDIP2-T14
-55 to 125
14 Ld Flatpack
CDFP4-F14
ACS05K/SAMPLE-03
25
14 Ld Flatpack
CDFP4-F14
ACS05HMSR-03
25
Die
N/A
Pinouts
ACS05MS
(SBDIP)
TOP VIEW
A1 1
ACS05MS
(FLATPACK)
TOP VIEW
14 VCC
Y1 2
13 A6
A1
1
14
VCC
Y1
2
13
A6
A2
3
12
Y6
Y2
4
11
A5
A2 3
12 Y6
Y2 4
11 A5
A3
5
10
Y5
A3 5
10 Y5
Y3
6
9
A4
GND
7
8
Y4
Y3 6
9 A4
GND 7
8 Y4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
ACS05MS
Die Characteristics
PASSIVATION:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
SPECIAL INSTRUCTIONS:
Bond VCC First
METALLIZATION:
ADDITIONAL INFORMATION:
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
Worst Case Current Density: <2.0 x 105 A/cm2
Transistor Count: 46
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS05MS
Y1
(2)
A1
(1)
VCC
(14)
A6
(13)
A2 (3)
(12) Y6
Y2 (4)
(11) A5
NC
NC
(10) Y5
A3 (5)
(6)
Y3
(7)
GND
(8)
Y4
(9)
A4
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