AN1002: 200W, 470kHz, Telecom Power Supply Using ISL6551 Full-Bridge Controller and ISL6550 Supervisor and Monitor

200W, 470kHz, Telecom Power Supply Using ISL6551 FullBridge Controller and ISL6550 Supervisor and Monitor
®
Application Note
AN1002
August 2002
Author: Chun Cheung
Abstract
This application note highlights design considerations for a 200W, 470kHz, telecom power supply using Intersil’s ISL6551 ZVS
Full-Bridge Controller and ISL6550 Supervisor And Monitor. The zero-voltage switching technique of the ISL6551 is presented in
detail. A step-by-step design procedure for a [email protected] with 88% efficiency converter based on these two chips,
incorporating both ZVS full bridge and current doubler topologies, is described. A few tips for design and debugging are then listed.
Finally, experimental results with discussion gives users a deeper understanding of the performance of the reference design and
the advantages of the ISL6550 and ISL6551.
Introduction
In medium to high power applications with extreme efficiency
requirements, the full-bridge topology is probably the best
choice. Besides great transformer utilization with this
topology, higher efficiency and lower EMI levels are the
major benefits if utilizing circuit parasitics, which include
output capacitance of the bridge FETs, primary capacitance
of the transformer, and leakage inductance, to achieve zerovoltage transitions (ZVT). In the conventional full bridge
converter, these advantages cannot be realized without
employing a significant amount of soft-switching/resonant
circuitry which adds cost and circuit board real estate.
Intersil’s ISL6551 full-bridge controller implements a unique
control algorithm, rather than the traditional phase-shifted
control technique introduced by TI’s UC3875, to achieve
ZVS with few components. In addition, the ISL6551
integrates additional sophisticated features such as Leading
Edge Blanking, Latching Shutdown Input, Enable Input,
Current Share Support, Fast Short-Circuit Shutdown,
Synchronous Drive Signals, and Power Good Indication that
the UC3875 does not provide. The ISL6551 enables a
complete and sophisticated power supply solution and can
save board space and engineering effort as well as cost.
This application note provides detailed design
considerations of a 200W telecom power supply reference
design employing both Intersil’s ISL6551 full-bridge
controller and ISL6550 Supervisor and Monitor while taking
advantage of both ZVS full-bridge and current doubler
topologies, as shown in Figure 1.
An alternative secondary rectification technique for push-pull
and bridge converters is introduced by Laszlo Balogh in his
paper [2]. This technique offers potential benefits of better
distributed power dissipation in densely packed power
supplies and in medium to high power and/or high output
current applications [2].
This converter is designed to meet the specification of an
industry-standard half brick. Most of the converter circuits
are placed in the central 2.50”x2.45” area and limited within
0.5” height, and all other unnecessary components such as
test point connectors and I/O connectors are placed beyond
this area. To easily modify the evaluation board for a broader
base of applications, additional circuits are designed in and
1
magnetics components are not integrated with the PCB. This
expands the area of the evaluation board when compared to
a standard half-brick design. This DC/DC converter accepts
a wide range input of 36V to 75V and generates a DACadjustable wide range output of 2.64V to 3.63V with
31.918mV step. An ultra high efficiency of 88% at 3.312V
with a fully loaded 60A output has been achieved.
+
QA
+
Vp
Vin
Lo
QC
T
+
QB
Q1
Co
Vs
-
Vo
Q2
QD
FIGURE 1. FULL BRIDGE + CURRENT DOUBLER TOPOLOGIES
This application note first introduces the unique ZVS
technique of the ISL6551. The Supervisor and Monitor
ISL6550 chip is then briefly introduced. Thereafter, a stepby-step design procedure for the reference design is
followed, including power train component selection,
component power dissipation calculations, magnetics design
parameter calculations, and control loop design. A few tips
for design and debugging are listed. Finally, experimental
results of the evaluation board are discussed. Term
Definitions, Block Diagram, Schematics, Layout, Bill of
Materials, References, and Preliminary Specifications of the
Reference Design are included at the end of this paper.
Intersil ZVS Full Bridge Controller:
ISL6551
The diagonal bridge switches are turned on together in a
conventional full bridge converter which alternatively places
the input voltage, VIN, across the primary of the transformer
for a period of Ton, as shown in Figure 2. The limiting factor
of achieving optimum efficiency in this circuit is the hard
switching nature of the operation, which causes significant
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Application Note 1002
are driven at a fixed 50% duty cycle and the two lower
switches (QB & QD) are PWM-controlled on the trailing edge
while the leading edge employs resonant delay. Figure 4
shows the drive signals of four bridge FETs and three
options for synchronous rectification. The basic control
principle of the ISL6551 is different from that of the
UC3875’s phase-shift control which varies the phase
between two 50% duty cycle control signals [1], requiring
additional circuitry to derive the synchronous control signals
and therefore adding cost.
switching losses in high frequency, high input voltage, and
/or high current applications. The switching losses can be
reduced by employing snubbers, or quasi- or fully resonant,
soft-switching circuits [1].
A
D
C
ON
FIGURE 2. CONVENTIONAL FULL BRIDGE PWM
WAVEFORMS
28 VDD
18 ON/OFF
In the ISL6551, rather than driving both of the diagonal full
bridge switches together, the two upper switches (QA & QC)
BANDGAP
REFERENCE
BGREF
8
PKILIM
7
11 CSS
ON
VP
16 LATSD
The ISL6551 is a ZVS full bridge controller that Intersil has
designed for medium to high power AC/DC and DC/DC
applications with ultra high efficiency requirements. The
ISL6551 includes many integrated features for a more
complete and sophisticated telecom or off-line power supply
solution. The internal architecture of the IC is shown in
Figure 4. Detailed ZVS operation of the ISL6551 will be
presented by describing switching actions of the power train
at each time interval in the following sections. Refer to the
device datasheet for the operation of the integrated features.
B
SHUTDOWN
UVLO
LATCH
SOFT
START
SHUTDOWN
27
VDDP1
24
UPPER1
23
UPPER2
26
VDDP2
LOWER1
DRIVER
22
LOWER1
LOWER2
DRIVER
21
LOWER2
UPPER1
DRIVER
R_LEB
9
R_RESDLY
4
ISENSE
6
R_RA
5
CT
2
RD
3
RESODLY
UPPER2
DRIVER
LEB
EAO 14
RAMP
ADJUST
CLOCK
GENERATOR
PWM
LOGIC
ERROR
AMP
EAI 13
EANI 12
CURRENT
SHARE
DC OK
25 PGND
20 SYNC1
NOTE: Pin numbers in the diagram refer to the SOIC package.
19 SYNC2
CS_COMP
VSS
15 SHARE
10
1
17 DCOK
Circuits Referenced to VSS
External Single Point Connection Required
FIGURE 3. ISL6551 INTERNAL STRUCTURE
2
Circuits Referenced to PGND
Application Note 1002
CLOCK
UP1
QA
UP2
QC
QB
LOW1
QD
LOW2
VP
Q1
SYNC1
1
Q2
SYNC2
LOW1’
Q1
2
LOW2’
Q2
SYNC2
Q1
3
SYNC1
Q2
T0
T1
T2
T3
T4
T0-T1=LOWER RIGHT-LEG POWER TRANSFER PERIOD
T1-T2=UPPER LEFT-TO-RIGHT FREEWHEELING PERIOD
T2-T3=Q1-TO-Q2 DEADTIME (FREEWHEELING)
T3-T4=LOWER LEFT-LEG RESONANT PERIOD
T5
T6
T7
T8=T0
T4-T5=LOWER LEFT-LEG POWER TRANSFER PERIOD
T5-T6=UPPER RIGHT-TO-LEFT FREEWHEELING PERIOD
T6-T7=Q2-TO-Q1 DEADTIME (FREEWHEELING)
T7-T8=LOWER RIGHT-LEG RESONANT PERIOD
In the above Figure, T0 through T8 are exaggerated only for demonstration purposes. There are three possible
synchronous rectification drive schemes:
1. Existing Synchronous Drive Signals (Sync1 & Sync2) + Non-inverting High Current Drivers (such as MIC4422)- The
Synchronous Fets (Q1 & Q2) are turned off together at the dead time and turned on alternatively every clock period;
2. Lower Drive Signals + Proper Delay + Inverting High Current Drivers (such as MIC4421)- The corresponding
synchronous FET is turned off whenever a voltage is across the secondary winding;
3. Existing Synchronous Drive Signals + Inverting High Current Drivers- The synchronous FETs are turned on together at
the dead time and turned on alternately every clock period.
FIGURE 4. DRIVE SIGNALS TIMING DIAGRAM
3
Application Note 1002
Vin
---------N
0
---------– Vin
N
Io
-----, Fsw
2
VS
/ Lo
Vo )
(Vs-
ILO1
Vo/Lo
Vo/Lo
ILO2
)
-Vo
(Vs
/Lo
)/ L o
2V o
(Vs-
2Vo/L
Io
-----, Fsw
2
o
Io, Fclock
ILO
Vo
(Vs-
IS
WORST CASE
)/Lo
Io
----2
Vo/Lo
0
Lo
Vo)/
(Vs-2
Io
----2
2Vo/Lo
Io
IQ1
WORST CASE
(Vs-2
IQ2
Io
2Vo/Lo
Lo
Vo)/
WORST CASE
IMAG
Vin/
-V i n
g
Lma
/ Lm
ag
ag
n/Lm
o+Vi
L
/N
)
o
(Vs-V
IP
WORST CASE
Vo/NLo
Imag
----------------2
– Imag
----------------2
Io
--------2N
0
Io
2N
– --------SYNC1
Q1
1
SYNC2
Q2
LOW1’
Q1
2
LOW2’
Q2
SYNC2
Q1
3
SYNC1
T0-RESDLY
Q2
T1
T0
T2
T3
T4
T0-T1=LOWER RIGHT-LEG POWER TRANSFER PERIOD
T1-T2=UPPER LEFT-TO-RIGHT FREEWHEELING PERIOD
T2-T3=Q1-TO-Q2 DEADTIME (FREEWHEELING)
T3-T4=LOWER LEFT-LEG RESONANT PERIOD
T5
T6
T7
T8=T0
T4-T5=LOWER LEFT-LEG POWER TRANSFER PERIOD
T5-T6=UPPER RIGHT-TO-LEFT FREEWHEELING PERIOD
T6-T7=Q2-TO-Q1 DEADTIME (FREEWHEELING)
T7-T8=LOWER RIGHT-LEG RESONANT PERIOD
In the above figure, T0 through T8 are exaggerated only for demonstration purposes. The slope of each waveform is in
an approximation. For a more accurate representation, losses should be included. The worst case happens at only
Q1 or Q2 carrying the load current during the freewheeling period. The current distribution through Q1 and Q2 is different
in these three drive schemes. Case 2 is the best option since both of its synchronous FETs are turned on during the freewheeling period. Note that VS is in the case of no primary leakage inductance, otherwise, delay would be induced, as
illustrated in the experimental results.
FIGURE 5. CURRENT WAVEFORMS
4
Application Note 1002
T0 -->T1, QA-to-QD Power Transfer (Active) Period
[Figure 6]
transformer and the output capacitance CC of QC are
discharged to from VIN to zero voltage (~diode drop).
QA = QD = ON, QB = QC= OFF
QA= ON, QD = OFF, QB = QC = OFF
+
QA
DA
QC
CA
QA
DA
CC
-
Vp
Vin
+
DC
Lk
QC
+
CC
-
Cp
Vp
Vin
Lk
-
DB
T
QD
DD
CB
QB
CD
-
Vs
+
Cp
T
QB
DC
CA
-
Vo
+
DB
D1
Co
Lo2
DD
CD
-
Lo1
Q1
QD
CB
Vs
Vo
+
Lo1
Q1
D1
Co
Lo2
Q2
Q2
D2
D2
SYNCHRONOUS FETS
Q1
Q2
OFF
SYNC DRIVE
ON
OFF
ON
OFF
INV_LOW DRIVE
ON
ON
ON
OFF
INV_SYNC DRIVE
ON
OFF
SYNCHRONOUS FETS
Q1
Q2
SYNC DRIVE
ON
INV_LOW DRIVE
INV_SYNC DRIVE
FIGURE 6. QA-TO-QD POWER TRANSFER PERIOD
When QD is turned on, QA has been already turned on in
the previous period, the resonant delay. In this transfer
(active) period, the full input voltage (VIN) is across the
primary of the transformer, and VIN/N is across the
secondary of the transformer once the primary current
catches the reflected output current. The primary current first
flows from QD to QA due to the prior resonant current and
then reverses in direction until the current reaches zero and
starts ramping up at a rate determined by VIN, the
magnetizing inductance, and the output inductance.
Simultaneously, Q2 should stay off for eliminating shootthrough currents, and Q1 is turned on to reduce conduction
losses; the current through the Lo2 is positive ramp, and the
current through the Lo1 is negative ramp. The ON-time of
QD is a function of VIN, Vo, the transformer turns ratio N,
and the output load Io. QD is turned off when the peak of the
modified current ramp signal hits the error voltage, and the
freewheeling period then begins.
T1 --> T2, QA-to-QC Clamped Freewheeling
(Passive) Period [Figure 7]
Once QD is turned off by trailing edge pulse width
modulation, the primary current continues flowing into the
output capacitance (Coss) CD of QD, which will be charged
up from the switch Rds(on) Drop to VIN - Diode Drop.
Simultaneously, the primary capacitance (Cp) of the
5
FIGURE 7. QA-TO-QC CLAMPED FREEWHEELING PERIOD
This transition is accomplished using the energy stored in the
leakage inductance of the transformer, the magnetizing
inductance, the reflected output inductance, and any external
commutating inductance. After the transition, the primary
current flows in the same direction and the real freewheeling
period begins. One end of the transformer is shorted to VIN by
the channel of QA, and the other end is clamped to VIN by the
body diode of QC, which is the only path that the primary
current can go through. The losses due to the body diode
conduction at the freewheeling period could be significant if
the primary current (the lumped sum of the magnetizing
current and the reflected secondary winding freewheeling
current), is relatively high. These conduction losses can be
minimized by employing the maximum allowable turns ratio of
the main transformer, i.e, the maximum allowable duty cycle
in the design. In some applications, shunting upper switches
with Schottky diodes might be another possible way to reduce
the conduction losses. For a wide range input application, if a
pre-regulator is implemented, then a fixed, high duty cycle
(~100%) post full-bridge regulator can be achieved and the
freewheeling time is minimized. The power dissipation of the
upper FETs can be therefore reduced significantly.
Three different synchronous rectification drive schemes can
be implemented with the ISL6551 as shown in Figures 4 and
5. The INV_LOW DRIVE scheme is the one that would
provide an additional path for the secondary freewheeling
Application Note 1002
current since both Q1 and Q2 are turned on during the
freewheeling time, which could reduce the conduction losses
and the reflected output current in the primary. The amount
of the load current split into Q1 and Q2 depends on the
voltage drop across the secondary winding, the Rds(on) of
Q1 & Q2, and/or the body diode drop of Q1 & Q2. The
optimum performance of the converter happens when the
load current is split into both turned-on Q1 and Q2 evenly. In
reality, the body diode drop at one of upper FETs, the
leakage inductance, and the shorted primary winding force
one of the synchronous FETs to carry the majority of the
output current while the other conducts a minority of the
load.
T3 --> T4, Lower Left-Leg (QB) Resonant Period
[Figure 9]
QA = OFF, QC = ON, QB = QD = OFF
+
QA
DA
QC
DC
CA
CC
-
Vp
Vin
Lk
+
Cp
T
QB
-
DB
QD
DD
CB
CD
-
T2 --> T3, Q1-to-Q2 Dead Time Period
[Figure 8]
Vs
Vo
+
Lo1
Co
Q1
D1
Lo2
Q2
QA= ON, QD = OFF, QB = QC = OFF
D2
+
QA
DA
QC
DC
CA
CC
-
Vp
Vin
Lk
SYNCHRONOUS FETS
+
Cp
Q1
Q2
SYNC DRIVE
OFF
ON
INV_LOW DRIVE
OFF
ON
INV_SYNC DRIVE
OFF
ON
T
QB
-
DB
QD
DD
CB
CD
-
Vs
FIGURE 9. LOWER LEFT-LEG RESONANT PERIOD
Vo
+
Lo1
Co
Q1
D1
Lo2
Q2
D2
SYNCHRONOUS FETS
Q1
Q2
SYNC DRIVE
OFF
OFF
INV_LOW DRIVE
ON
ON
INV_SYNC DRIVE
ON
ON
FIGURE 8. Q1-TO-Q2 DEAD TIME PERIOD
The dead time is used to prevent simultaneous conduction
of QC and QD, which would cause shoot-through currents.
The dead time is still part of the freewheeling period. The
drive control signals for the power switches therefore do not
change states while the drive signals of the synchronous
FETs change levels. In the SYNC DRIVE scheme, both Q1
and Q2 now are turned off and the load current freewheels
through the body diodes of both FETs. This introduces high
conduction losses in high output current applications.
Shunting both synchronous FETs with schottky diodes can
reduce the losses. In the INV_SYNC DRIVE scheme, both
Q1 and Q2 are turned on, therefore, schottky diodes are not
required, so are not in the INV_LOW DRIVE scheme.
6
The dead time period is followed by the lower left-leg
resonant period. It begins with QA turned off and QC turned
on. At the beginning of this transition, the input voltage is
applied first across the commutating inductance (leakage
and any external inductances), i.e, the real primary stays
zero until the current through these inductors changes in
direction in the next time interval. This can be seen in the
voltage waveforms across the primary winding and the
secondary winding, discussed in the EXPERIMENTAL
RESULTS section on pages 24-25. The direction of the
current through the primary winding remains the same as
that in the previous time interval. The current flows into the
transformer primary capacitance (Cp) and the output
capacitance (Coss) CA of QA, which will be charged up from
zero voltage (~Rds(on) Drop) to VIN. Simultaneously, the
output capacitance CB of QB is discharged to from VINRds(on) Drop to zero voltage (~diode drop). This transition is
accomplished with the energy stored in the primary
inductance (including leakage inductance, magnetizing
inductance, and any external inductance). It takes a longer
time to complete this transition than the one reaching the
freewheeling period since the energy stored in the resonant
inductances decreases due to the conduction losses of the
power switches and the primary current is decaying in the
freewheeling period. Once QB is clamped to zero voltage by
its own body diode, QB is turned on at zero voltage (ZVS
transition). Another power transfer period is followed by the
other diagonal power switches (QC-to-QB). The rest of the
Application Note 1002
discussion (Figures 10 to 13) is just the repetition of another
half cycle.
T4 --> T5, QC-to-QB Power Transfer Period
[Figure 10]
QB = QC = ON, QA = QD = OFF
+
QA
DA
QC
DC
CA
CC
-
Vp
Vin
Lk
+
Cp
discharged from VIN to zero voltage (~diode drop). This
transition is accomplished using the energy stored in the
leakage inductance of the transformer, the magnetizing
inductance, the reflected output inductance, and any
external commutating inductance. After the transition, the
primary current flows in the same direction and the real
freewheeling period begins. One end of the transformer is
shorted to VIN by the channel of QC, and the other end is
clamped to VIN by the body diode of QA, which is the only
path that the primary current can go through. Refer to the
T1-->T2 period for more detailed discussion.
T
QB
-
DB
QB = OFF, QC = ON, QA = QD = OFF
QD
DD
CB
CD
-
Vs
+
Vo
+
QA
Lo1
DA
QC
DC
CA
Q1
D1
CC
Co
Lo2
-
Vp
Vin
Q2
Lk
+
Cp
D2
T
QB
-
SYNCHRONOUS FETS
Q1
Q2
SYNC DRIVE
OFF
ON
INV_LOW DRIVE
OFF
ON
INV_SYNC DRIVE
OFF
ON
DB
QD
DD
CB
CD
-
Vs
Q1
Vo
+
Lo1
D1
Co
Lo2
Q2
D2
FIGURE 10. QC-TO-QB POWER TRANSFER PERIOD
When QB is turned on, QC has been already turned on in
the previous period, the resonant delay. In this transfer
(active) period, the full input voltage (VIN) is across the
primary of the transformer, and VIN/N is across the
secondary of the transformer once the primary current
catches the reflected output active current. The primary
current first flows from QB to QC due to the prior resonant
current and then reverses in direction until the current
reaches zero and starts ramping up at a rate determined by
VIN, the magnetizing inductance, and the output inductance.
Simultaneously, Q1 should stay off for eliminating shootthrough currents, and Q2 is turned on to reduce conduction
losses; the current through the Lo1 is a positive ramp, and
the current through Lo2 is a negative ramp. The ON-time of
QB is a function of VIN, Vo, the transformer turns ratio N,
and the output load Io. QB is turned off when the peak of the
modified current ramp signal hits the error voltage, and
another freewheeling period then begins.
T5 -->T6, QC-to-QA Clamped Freewheeling Period
(Passive) [Figure 11]
Once QB is turned off, the primary current continues flowing
into the output capacitance (Coss) CB of QB, which will be
charged up from the switch Rds(on) Drop to VIN + Diode
Drop. Simultaneously, the primary capacitance (Cp) of the
transformer and the output capacitance CA of QA are
7
SYNCHRONOUS FETS
Q1
Q2
SYNC DRIVE
OFF
ON
INV_LOW DRIVE
ON
ON
INV_SYNC DRIVE
OFF
ON
FIGURE 11. QC-TO-QA CLAMPED FREEWHEELING PERIOD
T6 --> T7, Q2-to-Q1 Dead Time Period
[Figure 12]
The dead time is used to prevent simultaneous conduction
of QA and QB, which would cause shoot-through currents.
The dead time period is still part of the freewheeling period,
the drive control signals for the power switches therefore do
not change states while the drive signals of the synchronous
FETs change levels. In the SYNC DRIVE scheme, both Q1
and Q2 now are turned off, the load current free wheels
through the body diodes of both FETs, which introduces high
conduction losses in high output current applications.
Shunting both synchronous FETs with schottky diodes can
reduce the losses. In the INV_SYNC DRIVE scheme, both
Q1 and Q2 are turned on, therefore, schottky diodes are not
required, so are not in the INV_LOW DRIVE scheme.
Application Note 1002
QB = OFF, QC = ON, QA = QD = OFF
QC = OFF, QA = ON, QB = QD = OFF
+
+
QA
DA
QC
DC
CA
QA
DA
CC
-
Vp
Vin
Lk
QC
+
CC
-
Cp
Vp
Vin
Lk
-
DB
T
QD
DD
CB
QB
CD
-
Vs
+
Cp
T
QB
DC
CA
-
Vo
+
DB
QD
DD
CB
CD
-
Lo1
Vs
Vo
+
Lo1
Co
Q1
D1
Co
Lo2
Q1
D1
Lo2
Q2
Q2
D2
D2
SYNCHRONOUS FETS
Q1
Q2
SYNC DRIVE
OFF
ON
INV_LOW DRIVE
ON
ON
INV_SYNC DRIVE
ON
ON
FIGURE 12. DEAD TIME PERIOD
T7 --> T8=To, Lower Right-Leg (QD) Resonant
Period [Figure 13]
The previous dead time period is followed by the lower rightleg resonant period. It begins with QC turned off and QA
turned on. At the beginning of this transition, the input
voltage is applied first across the commutating inductance
(leakage and any external inductances), i.e, the real primary
stays zero until the current through these inductors changes
in direction in the next time interval. This can be seen in the
voltage waveforms across the primary winding and the
secondary winding, discussed in the EXPERIMENTAL
RESULTS section on page 24-25. The direction of the
current through the primary winding remains the same as
that in the previous time interval. The current flows into the
transformer primary capacitance (Cp) and the output
capacitance (Coss) CC of QC, which will be charged up from
zero voltage (~Rds(on) Drop) to VIN. Simultaneously, the
output capacitance CD of QD is discharged to from VINRds(on) Drop to zero voltage (~diode drop). This transition is
accomplished with the energy stored in the primary
inductance (including leakage inductance, magnetizing
inductance, and any external inductance). It takes a longer
time to complete this transition than the one reaching the
freewheeling period since the energy stored in the resonant
inductance decreases due to the conduction losses of the
power switches and the primary current is decaying in the
freewheeling period. Once QD is clamped to zero voltage by
its own body diode, QD is turned on at zero voltage (ZVS
transition). At this point a full operating cycle is completed.
8
SYNCHRONOUS FETS
Q1
Q2
SYNC DRIVE
ON
OFF
INV_LOW DRIVE
ON
OFF
INV_SYNC DRIVE
ON
OFF
FIGURE 13. LOWER RIGHT-LEG RESONANT PERIOD
Intersil Supervisor and Monitor: ISL6550
The ISL6550 is a precision flexible, VID-code-controlled
reference and voltage monitor for high-end microprocessor
and memory power supplies. It monitors various input
signals, and supervises the systems with its outputs. The
ISL6550 saves board space, design time, and system cost.
The internal structure of the ISL550 is shown in Figure 14.
The reference design is implemented with the MLFPpackaged ISL6550, C version. Refer to the device datasheet
for operating details.
In the reference design, the ISL6550 monitors the output
voltage and supervises the ISL6551 full bridge controller.
• The spare operational amplifier of the ISL6550 is used as
a differential amplifier and its output (VOPOUT) is sent to
the inverting input (EAI) of the error amplifier of the
ISL6551. Note that the VOPOUT is limited to 5V.
• The under-voltage delay (UVDLY) prevents false
triggering of the START output during startup, and the
ISL6550 START output is fed to the ON/OFF input of the
ISL6551. In output over-voltage (+8.33%) and undervoltage (-8.33%) conditions, the START is triggered and
latches shutdown the ISL6551 controller. When the VCC
of ISL6550 is below the turn-on/off threshold, the START
is held low and disables the ISL6651 controller.
• The output reference BDAC, which is fed to the noninverting input (EANI) of the error amplifier of the ISL6551,
is programmed by the 5-bit VIDs and the resistor network
that connects to DACHI and DACLO. Note that a 50k total
resistance of the network is recommended and the overall
Application Note 1002
output error should include VREF5 error and external
resistor divider error as well as the internal buffer offset. In
the reference design, the output voltage can be
programmed from 2.64V to 3.63V with 31.918mV step and
+/-3% statics error over full operating conditions.
to +/-40% about the BDAC voltage. In the reference
design, the over/under voltage window is set at +/-8.33%.
• PEN is connected to a mechanical switch to turn on/off the
converter manually. It is also controlled by the circuitries
that monitor the input voltage level and the thermal
condition of the converter.
• The output voltage is sensed by the OVUVSEN, and the
OV-UV windows is centered around the BDAC voltage
and can be programmed with the OVUVTH pin from +/-5%
VREF5
VCC
5
1
Buffered
5V REF
Opamp
VOPM
3
VOPP
2
VOPOUT
4
5V
+
• PGOOD provides an indication if the output voltage is
within over/under voltage limits (+/-8.33%).
17 START
LOGIC BLOCK
see 2A, 2B, 2C below
10uA to 5V
PEN
PEN: H = Enable; L = Disable
16
UVLOCKOUT
(POR)
OVUVSEN 19
POR: H = VDD too low; L = VDD OK
OV
OV: H = Over-Voltage; L = OK
OVUVTH
8
THRESHOLD
PROGRAM
UV
UV/OV hysteresis
See Note
below
18 PGOOD
UV: H = Under-Voltage; L = OK
UVD: H = UV Delay timed out; L = no time-out
R1
DACHI
9
VID4 11
UVDELAY
20 UVDLY
(each VID pin)
10uA to 5V
VID3 12
VID2 13
7
BDAC
VID1 14
R2
VID0 15
R4
DACLO 10
6
GND
R3
2A
2B
PEN
POR
Q
Note: UV/OV
hysteresis = 10%
Note: UV/OV
hysteresis = 40%
PEN
POR
OV
UVD
2C
PEN
POR
Q
Note: UV/OV
hysteresis = 10%
PEN
POR
POR
R
R
Q Q: H = Fault;
L = No Fault
OV
UV
UVD
PEN
S
UV
UVD
PEN
FAULT
LATCH
PEN
POR
Q
UV
NOTE: S input dominates Q
S
FAULT
LATCH
PEN
POR
OV
UV
NOTE: No latch in 2B
POR
OV
UV
NOTE: S input dominates Q
NOTE: Pin numbers in the diagram refer to the SOIC package.
FIGURE 14. ISL6550 INTERNAL STRUCTURE
9
Q Q: H = Fault;
L = No Fault
OV
R5
Application Note 1002
Converter Design
This section presents a step-by-step design procedure for a
48V-to-3.3V, 200W, 470kHz with 88% efficiency converter
using both ISL6551 and ISL6550 for telecom applications
(i.e VIN=36V-to-75V). The converter is designed with
secondary-referenced, peak current-mode control, and both
ZVS full bridge and current doubler topologies.
For simplicity, all calculations in this section neglect the
transitions shown in Figure 5. The worst case current
waveforms are used even in the INV_LOW DRIVE scheme,
unless otherwise stated.
Select Synchronous DRIVE Scheme
The INV_LOW DRIVE scheme for synchronous rectification
is employed in the reference design. This scheme induces
less conduction losses in the synchronous FETs than both
INV_SYNC and SYNC DRIVE schemes, which can be
explained with a few equations (EQ. 1- 6). The terms used in
all equations are defined later in the paper, unless otherwise
stated in the text.
Io 2 = ( IQ1 + IQ2 ) 2 = IQ1 2 + IQ2 2 + 2 • IQ1 • IQ2
(EQ. 1)
IQ1 2 + IQ2 2 ≤ IQ1 2 + IQ2 2 + 2 • IQ1 • IQ2
(EQ. 2)
The power dissipation is the same in the active (transfer)
period but different in the freewheeling period for the three
drive schemes. In both INV_SYNC and SYNC DRIVE
schemes, only one synchronous FET is turned on carrying
all the load current during the freewheeling period. The
conduction losses of each leg in the freewheeling period can
be approximated with EQ. 3:
1–D
Psynfetfr = Io 2 •  ------------- • Rdsonsyn
 2 
(EQ. 3)
In the INV_LOW DRIVE scheme, both synchronous FETs
are turned on and each one carries a portion of the load
current during the freewheeling period. The power
dissipation of each leg in this period is reduced to EQ. 4:
1–D
Psynfetfr = ( IQ1 2 + IQ2 2 ) •  ------------- • Rdsonsyn
 2 
(EQ. 4)
Comparing EQ. 3 to EQ. 4, we note that the INV_LOW
scheme induces less power dissipation in the synchronous
FETs by an amount of EQ. 5:
∆Psynfetfr = 2 • IQ1 • IQ2 • ( 1 – D ) • Rdsonsyn
(EQ. 5)
In addition, the INV_LOW scheme also helps cut down the
conduction losses in the primary FETs since the primary has
less reflected secondary current, which decreases with the
difference between IQ1 and IQ2, as shown in EQ. 6:
10
Is
IQ1 – IQ2
Ip ≈ ----- = --------------------------N
2N
(EQ. 6)
Although the INV_LOW scheme is a better choice from the
power dissipation standpoint, the user should pay special
attention to the impact of having on overlap between both
synchronous FETs during the freewheeling period in current
share, light load, start up, and turn-off operations. Some
discussions are presented in the EXPERIMENTAL
RESULTS section.
Select Switching Frequency and Define Maximum
Available Duty Cycle
Several things are considered when selecting an appropriate
switching frequency for a particular application. The size of
the converter (limited by sizes of magnetics components),
the overall losses of magnetics components, the switching
losses of power MOSFETs, the desired efficiency, the
transient response, and the maximum achievable duty cycle
are all considerations. An iterative process is required,
monitoring changes of the above parameters, to obtain an
optimum switching frequency for a particular application.
Users can use equations presented in this paper to design a
MathCAD worksheet, which will help obtain a rough idea of
the range of optimum frequencies for their applications. Note
that the higher the switching frequency is, the higher the loop
bandwidth (typical 1/10 or higher of the switching frequency)
can be realized, but the lower the maximum duty cycle is
available.
In the initial design of the evaluation board, these
parameters are pre-selected: Fsw=250kHz=Fclock/2,
tDEAD=200ns, and tRESDLY=100ns. The maximum
available duty cycle then can be calculated using EQ. 7
(Dmaxav=85%). The duty cycle defined in this application
note is the ratio of the ON-time interval of a lower FET to one
clock period.
t DEAD – t RESDLY
-
Dmaxav =  1 – ----------------------------------------------

Fclock
(EQ. 7)
Define Turns Ratio
The primary-to-secondary turns ratio of the main transformer
should be chosen as high as possible without exceeding the
maximum available duty cycle (Dmaxav=0.85) at the
minimum line (Vinmin=36V, or the input UV setpoint) and the
rated load (Io=60A) situation. The higher the turns ratio is,
the less the load current is reflected to the primary side, and
the less the power losses are induced by the primary
MOSFETs. The maximum allowable turns ratio can be
calculated with EQ. 8 (Nmax=3.79).
2 • ( Vomax + Vmisc + Vsynfet ) • N
Dmaxav = ------------------------------------------------------------------------------------------------------------ Vinmin – Rdsonpri • Io
----- – Vsynfet • N

N
(EQ. 8)
Application Note 1002
where Vsynfet = Io x Rdsonsyn/2 is the channel drop of the
synchronous FETs at half of the load (assuming that the
output load is split evenly into both synchronous FETs
during the freewheeling period), Vomax is the maximum
output voltage (3.63V), and Vmisc is the sum of the
miscellaneous voltage drops including contact resistance,
winding resistance, PCB copper resistance. The initial guess
of Vmisc is 0.3V for having a safe margin. If the load (Io)
conducts through only one synchronous FET during the
freewheeling period, then EQ. 8 can be simplified to EQ. 9
(Nmax=3.77):
2 • ( Vomax + Vmisc + 2 • V synfet ) • NDmaxav = ---------------------------------------------------------------------------------------------------------Io
Vinmin – Rdsonpri • ----N
(EQ. 9)
With the assumptions of Rdsonpri=25 x1.2mΩ (Tj=500C)
and Rdsonsyn=1.125x1.13mΩ (Tj=500C), EQ. 9 produces
Nmax=3.77. Since the size and height of the converter are
limited to that of a telecom half brick, a planar transformer
with a low number of turns on both the primary and
secondary sides is required. Therefore, 7/2 and 11/3 turns
ratio are preferred choices. A transformer with 7 primary
turns and 2 secondary turns has been used in the reference
design due to the availability of magnetic cores in stock. In
fact, a transformer with 11/3 turns ratio is generally
recommended.
Output Filter Design (Current Doubler)
The output L-C filter is normally defined based on
requirements of the output ripple voltage (70mV) and the
transient response (dVtr=150mV). In general, if the
requirement of the transient response is met, then the output
ripple voltage will be within the limit.
As a rule of thumb, the overall ripple current (dIo) should be
no more than 20% of the rated load, and the output inductor
value (for each one) can be defined by EQ. 10:
2 • ( Vo + 2 • V synfet ) • ( 1 – D -)
Lo = ----------------------------------------------------------------------------------dIo • Fclock
The minimum required output capacitance (Co) can be
estimated by EQ. 13 when limiting the output ripple voltage
contributed by output capacitance to be no more than dVCo.
dIo
1
Co = --------------- • ---------------------------dV Co 8 • Fclock
(EQ. 13)
In addition to meeting the requirements of ESR and Co, the
output capacitors should be able to absorb the output RMS
current, as defined in EQ. 14.
dIo
Iorms = ---------12
(EQ. 14)
The output voltage ripple can be conservatively
approximated by EQ. 15. The first two terms (dVESR and
dVESL) contributed by the equivalent series resistance
(ESR) and the equivalent series inductance (ESL) of the
output capacitors are the dominant ones and are normally
accurate enough to estimate the ripple voltage. The last term
(dVCo) contributed by the output capacitance (Co) is
normally much smaller and can be neglected since the peak
of the dVCo happens at the ripple current across zero and
does not align with the peak of dVESR, as shown in Figure
15. The positive and negative peaks of the overall ripple
voltage (sum of all three components) relative to the DC
level is not symmetric (caused by dVCo and dVESL) unless
the converter operates at 50% duty cycle. This asymmetry
between positive and negative peaks is not a big concern in
most applications since both dVCo and dVESLare generally
very small compared to the ESR portion. Note that the DC
level remains constant. Refer to [6] for more details.
ESL
1
dIo
Voripple ≈ dIo • ESR + ------------ Vs + -------- • ---------------------------Lo
Co 8 • Fclock
(EQ. 15)
+
0
dVESR
(EQ. 10)
dVESL
0
+
-
The ripple current (dI) through each inductor can be
calculated with EQ. 11:
( Vo + 2 • V synfet ) • ( 2 – D )
dI = --------------------------------------------------------------------------Lo • Fclock
dVCo
(EQ. 11)
-
FIGURE 15. OUTPUT RIPPLE VOLTAGE COMPONENTS
The requirement of the transient response is the major factor
of defining the maximum overall ESR of the output
capacitors in EQ. 12. Note that this converter is designed to
meet 150mV transients (dip/overshoot) for a 25% rated load
step (ESR < 10mΩ).
dVtr
ESR < -------------Istep
0
(EQ. 12)
The ESL of a capacitor is not usually listed in databooks. It
can be practically approximated with EQ. 16:
1
1
ESL = -------- • ---------------------------------Co ( 2π • Fres ) 2
(EQ. 16)
where Fres is the resonant frequency that produces the
lowest impedance of the capacitor.
At the very edge of the transient, the equivalent ESL of all
output capacitors induces a spike, as defined in EQ. 17 for a
11
Application Note 1002
given dI/dt, that adds on the top of the existing voltage
undershoot/overshoot due to the ESR and capacitance.
dI
∆V ESL = ESL • ----dt
(EQ. 17)
Vo
f(Istep)
to load transients. This could cause a significantly large
undershoot/overshoot at the output. In the reference design,
the loop bandwidth (fc) is lower than the zero
[1/(2π*ESR*Co)] of the output capacitors, which have low
ESL transient component due to low dI/dt(1A/us), therefore,
the required output capacitance can be roughly
approximated with EQ. 21 [7].
Istep
Co ≈ ----------------------------------2π • f c • dVtr
∆V CAP
∆V ESL
1
fc ≤ ---------------------------------------2π • ESR • Co
(EQ. 21)
Several lower-profile TAIYO YUDEN 100u, 6.3V capacitors
(JMK212F107MM) have been used in the evaluation board
to meet the electrical requirements of the above discussion
and the height constraint of the converter.
Istep
FIGURE 16. TYPICAL TRANSIENT RESPONSE WAVEFORM
Thus, the overall output voltage undershoot/overshoot due
to load transients can be summarized in EQ. 18, in which the
last term can be normally dropped out if the very edge of the
transient is the dominant peak, as shown in Figure 16.
dVtr ≈ f ( Istep ) + ∆V ESL + ∆V CAP
(EQ. 18)
where
1 + ( 2π • f c • Co • ESR ) 2
f ( Istep ) = Istep -----------------------------------------------------------------------2π • f c • Co
f ( Istep ) ≈ Istep • ESR
for
1
fc ≥ ---------------------------------------2π • ESR • Co
Istep
f ( Istep ) ≈ ------------------------------2π • f c • Co
for
1
fc ≤ ---------------------------------------2π • ESR • Co
∆V CAP = ∆V HUMP
for
step-up transients
∆V CAP = ∆V SAG
for
step-down transients
The last term in EQ. 18 is a direct consequence of the
amount of output capacitance. After the initial spike, all the
excessive charge is dumped into the output capacitors on
step-down transients causing a temporary hump at the
output, and the output capacitors deliver extra charge to
meet the load demand on step-up transients causing a
temporary sag before the output inductors catch the load.
The approximate response time intervals for removal and
application of a transient load are defined by dTn and dTp,
respectively.
Istep • dTn
∆V HUMP = ------------------------------2 • Co
where
Electrical design parameters of the output inductors are
summarized in EQs. 11, 22, & 23, which specify the ripple
current, the peak current, and the RMS current of each
inductor.
Io + dI
Iindpeak = ----------------2
(EQ. 22)
Io
dI
Iindrms = ----- + ---------2
12
(EQ. 23)
Calculations for Synchronous FETs (Q1 & Q2)
Some fundamental formulas that are used to calculate RMS
values of triangular and trapezoid waveforms and to derive
most equations in this paper are defined below.
Ib
∆I
1–d
Irms1 =
Ic
Ia
d
CASE 1
∆I 2
Ic 2 + -------12
Ib
∆I
Ic
Ia
CASE 2
d
0
(EQ. 19)
Irms2 =
Istep
dTn = Lo -------------2Vo
Istep • dTp
∆V SAG = ------------------------------2 • Co
where
Besides ESL, ESR, and capacitance of the output
capacitors, other system parasitics such as board resistance
and inductance should be included in the load transient
analysis [6], which will not be discussed in this paper.
Ib
(EQ. 20)
CASE 3
Irms3 =
In low-profile, high current density, and high frequency
applications, the required output capacitance defined in
EQ. 13 might not be enough to deliver or absorb energy due
∆I
Ia
0
d
Istep
dTp = Lo ------------------------Vs – 2Vo
12
I 2- • d
 Ic 2 + ∆
------
12 
– Id
∆I 2
Ic 2 • ( d – d 2 ) + -------- • d
12
In the power transfer period, one synchronous FET is turned
off, and the other one is turned on conducting all the load
Application Note 1002
Ib
∆I
Ia
CASE 4
1–d
0
Irms4 =
Ic
I 2- • ( 1 – d )
 Ic 2 + ∆
------
12 
+ IbIc = Ia
---------------2
WHERE
Id = Ic • d
∆I = Ib – Ia
current. The peak current through the FET is defined by the
load current plus half of the output ripple current in EQ. 24.
In this period, the RMS current through each FET can be
calculated with EQ. 25 using Case 2 formula. Note that the
duty cycle (D) is defined as the ratio of the ON-time interval
of a lower FET over one clock period (twice of the switching
period), which explains the 1/2 factor in the equation.
dIo
Isynpeak = Io + --------2
Isynrmstr =
2
D
 Io 2 + dIo
------------ • ---
12  2
2
1–D
 Io 2 + dIo
------------ • ------------
2
12 
Isysrmstr 2 + Isysrmsfr 2
Psynfet = Isynrms 2 • Rdsonsyn
An additional term “Isyndeadavg x Vdsyn” should be added
to EQ. 28 if the SYNC DRIVE scheme is implemented.
Isynrmsfr however would be slightly smaller.
The maximum voltage across the synchronous FET can be
approximated with EQ. 31, adding 30% margin for the
ringing on the rising edge.
(EQ. 27)
(EQ. 28)
(EQ. 29)
where p is the percentage of load current through one of the
synchronous FETs. A guess of p can made by looking at the
primary freewheeling current, as shown in the
EXPERIMENTAL RESULTS section. For the other two drive
schemes, FDIST is one.
In the SYNC DRIVE scheme, both synchronous FETs are
turned off during the dead time period. The freewheeling
13
The synchronous FETs should be selected such that the
VDS rating and power rating of the MOSFETs are greater
than Vsynmax and Psynfet, respectively. Four 30V Siliconix
Si4842DY MOSFETs are used for each leg. Note that any
switching losses, which will be discussed later, should be
included in the calculation to define the maximum power
dissipation.
(EQ. 26)
In addition, the distribution factor (FDIST) for IQ1 and IQ2
currents during the freewheeling period for the INV_LOW
DRIVE scheme can be included in EQ. 26 for an accurate
calculation:
( 1 – p )2 + p2
(EQ. 31)
(EQ. 25)
As shown in EQs. 25 and 26, the higher the ripple current is,
i.e., the lower the output inductances are, the higher the
RMS currents are, and the higher the conduction losses of
the synchronous FETs are.
F DIST =
(EQ. 30)
Vinmax
Vsynmax = ---------------------- ( 1 + 0.3 )
N
Thus, the overall RMS current through one synchronous
FET can be defined in EQ. 27, while the conduction losses
of each synchronous FET can be calculated with EQ. 28.
Isynrms =
t DEAD
dIo ( t DEAD + t RESDLY – 0.5T ( 1 – D ) )
Isyndeadavg = -----------------  Io + ----------------------------------------------------------------------------------------------------

4•T 
(1 – D) • T
(EQ. 24)
In the worst case, all the load current flows through one of
the synchronous FETs during the freewheeling period
(including the resonant and dead periods for simplicity), the
RMS current through the FET can be estimated by EQ. 26.
Isynrmsfr =
current flows through the body diodes of the FETs, and any
external schottky diodes. In the worst case, the freewheeling
current flows through only one leg, and the average current
for the dead time can be estimated by EQ. 30, where tDEAD
is the dead time and tRESDLY is the resonant time.
Calculations for Primary Switches
(QA, QB, QC, & QD)
The peak current through the primary winding happens at
the end of the active period, as defined in EQ. 32
Io + dI Imag
Ipripeak = ----------------- + -------------2N
2
(EQ. 32)
( Vin – 2 • I p • Rdsonpri ) • D
Imag = -----------------------------------------------------------------------------Lmag • Fclock
(EQ. 33)
EQ. 33 defines the peak-to-peak magnetizing current. The
RMS current through the power switches in the active period
can be estimated by EQ. 34, which also defines the overall
RMS current through a lower FET.
Iprirmstr =
where
Io  2 dIp 2 D
  ------- + ------------ • ---  2N
12  2
(EQ. 34)
dI
dIp = ----- + Imag
N
If there is a time delay Td to turn on the lower FET after its
output capacitance is completely discharged, i.e, the
resonant delay is set longer than is necessary, then the
current will flow through the body diode of the lower FET,
which has an average value defined in EQ. 35.
Io Imag dI ( D + Td ⁄ T ) Td
Ipriavgres =  -------- + -------------- + ------------------------------------ • ------ 2N
2
2N ( 2 – D )  2T
(EQ. 35)
Application Note 1002
The freewheeling current flows through the channel and the
body diode of upper FETs in alternate freewheeling periods
and at alternate directions. The RMS current through the
channel can be calculated with EQ. 36. The average current
through the body diode of the upper FET can be estimated
with EQ. 37.
Iprirmsfr =
1–D
Io
dI
Imag 2
dI 2 ( 1 – D ) 2
  ------- + --------------------------- + -------------- + ------------------------------------ • ------------  2N 2N ( 2 – D )
2
2 
12N 2 ( 2 – D ) 2
of EQ. 42 happens at D=0.5. Several lower-profile ITW
Paktron capacitors (105K100ST2814) and an external
capacitor have been used in the evaluation board. If a hold
up time (tHOLDUP) is required when the input line is
momentarily disconnected, then EQ. 43 helps define the
required hold up capacitance:
2Po • t HOLDUP
Cin = --------------------------------------------------------------η • ( Vin 2 – V 2 HOLDUP )
(EQ. 36)
1–D
Io- + Imag
dI - • -----------Ipriavgfr =  -------------------- – ------------------------- 2N
2
2
2N ( 2 – D )
(EQ. 37)
or
where
Thus, the overall RMS current through the channel of each
upper FET is defined in EQ. 38:
Iprirms =
Iprirmstr 2 + Iprirmsfr 2
(EQ. 38)
With all the above RMS and average current information, the
conduction losses of each power switch can be roughly
estimated with EQs. 39 and 40. As shown in EQs. 34 and
36, the higher the inductor ripple current and the
magnetizing current are, i.e., the lower the output inductance
and the magnetizing inductance are, the larger the RMS
currents are, the higher the power losses would be induced
by the primary switches.
Pupfet = Iprirms 2 • Rdsonpri + Ipriavgfr • Vd
(EQ. 39)
(EQ. 43)
Po • t HOLDUP
Cin ≈ --------------------------------------η • Vin • ∆Vin
η = Efficiency
∆Vin = Vin – V HOLDUP
The overall input voltage ripple induced by the ESR and
capacitance of the input capacitors can be estimated with
EQ. 44. In addition, the spikes caused by the ESL of the
input capacitors should be decoupled with lower ESL
ceramic capacitor.
Io
T
Vinripple = -------- • ( D – D 2 ) • --------- + ESRin • Ipripeak
2N
Cin
(EQ. 44)
Furthermore, for a low EMI level performance, an additional
L-C filter might be required in the front end. However, the
combination of both ZVS full bridge and current doubler
topologies helps reduce the size of this input EMI filter.
Switches Losses and Driver Losses
Plowfet = Iprirmstr 2 • Rdsonpri + Ipriavgres • Vd
(EQ. 40)
Four 100V Siliconix SUD40N10 MOSFETs are selected for
the bridge switches such that the ratings of the device are
greater than Pupfet, Plowfet, and the maximum input
voltage. Note that any switching losses, which will be
discussed later, should be included in EQs. 39 and 40 to
define the maximum power dissipation of the primary
switches, which limits the MOSFET selection.
Input Filter Design
The input pulsating current filtered by the input capacitors
has an RMS value in EQ. 41, while the minimum required
input capacitance is defined in EQ. 42.
Iinrms =
( dIp ) 2
Io  2
 ------- • ( D – D 2 ) + ----------------- • D
 2N
12
Io
T
Cin = -------- • ( D – D 2 ) • -----------------------2N
dVincap
(EQ. 41)
1
Ppriswon = --- V on • I on • t on • Fsw
2
(EQ. 42)
When the lower FET is turned off, its corresponding upper
FET is clamped to VIN in a very short time. The
corresponding synchronous FET is turned on when the
voltage across the secondary winding vanishes, therefore,
there are no turn-on switching losses for the synchronous
FETs. The resonant delay and the delay caused by the
leakage inductance to have any voltage across the
The dVINcap is the acceptable input ripple voltage
contributed by the amount of input capacitance, of which is
the input capacitors (ITW Patron capacitors in the reference
design) that filter most of pulsating currents. The maximum
value of EQ. 41 happens at D~0.5, while the maximum value
14
In general, switching losses are an insignificant portion
compared to conduction losses of the power switches if ZVS
transitions are achieved. Since the commutating
inductances store the peak energy to swing the output
capacitance of the upper FET from VIN to zero volt at the
beginning of the freewheeling period before the upper FET is
turned on, therefore, the upper FETs are lossless at turn on
transitions. At the end of freewheeling period, the
commutating inductances store the least energy, which
might not be enough (especially in high line and/or low load
conditions) to swing the output capacitance of the lower FET
to zero volt before they are turned on. The turn-on losses of
the lower FETs can be approximated with EQ. 45. The turnoff losses of primary switches can be minimized with a high
speed driver such as Intersil HIP2100.
(EQ. 45)
Application Note 1002
secondary winding, as illustrated in EXPERIMENTAL
RESULTS, prior to turn off the synchronous FET, help to
achieve ZVT for the synchronous FETs at turn off. To
achieve ZVT as discussed in previous lines, the
synchronous FET drivers however should have high current
capability with little propagation delays such as MICREL 9A
MIC4421 inverting drivers or better. The conduction losses
and reverse recovery losses of body diodes of the
synchronous FETs at turn on or off are not discussed here,
but they do show up in Figure 35.
Note that the drivers with high current capability can shorten
the transition time and reduce the switching losses.
The driver losses due to the gate charge of the MOSFETs
should be investigated thoroughly to prevent over stressing.
The switching losses of both primary and secondary drivers
and its corresponding average driver current due to the gate
charge can be estimated with EQs. 46 and 47, respectively,
the current ramp signal, which makes the supply look
voltage mode. A reasonable small Lmag can assist ZVS and
decrease any noise sensitivity problems. Around 100uH is a
start point for telecom brick applications. In addition, it is
recommended to have a small gap in the transformer
stabilizing the magnetizing inductance so that the
magnetizing current can be within a controllable range.
The leakage inductance is not an issue in the design. In fact,
it is part of the commutating inductance to assist ZVS using
its stored energy. Too much leakage inductance however
will lower the effective duty cycle, resulting in a lower turns
ratio.
The primary-to-secondary capacitance should be minimized
since it robs energy from the ZVS elements increasing the
resonant time and decreasing the maximum available duty
cycle and the ZVS load range.
Qg
Pdr = ------------ • Vcc 2 • Fsw
V GS
(EQ. 46)
As far as the size of the transformer is concerned, it varies
with applications. In the reference design, the transformer is
limited to less than 0.5 inch height, being able to fit into a
telecom half brick.
Qg
Idr = ------------ • Vcc • Fsw
V GS
(EQ. 47)
Determine Commutating Inductance
where Qg and VGS are defined in the MOSFET datasheet.
Define Requirements of Main Transformer
This section summarizes major design requirements of the
main transformer at the switching frequency.
The turns ratio of the transformer is derived from EQ. 9
while EQ. 32 defines the peak current through the primary
winding. The RMS current through the primary winding is
defined in EQ. 48.
Iprms =
2 • Iprirms
(EQ. 48)
The current through the secondary winding is only half of the
load, and its RMS currents in both transfer and freewheeling
periods can be defined by EQs. 49 and 50, respectively. The
overall RMS current through the secondary winding can be
calculated with EQ. 51.
Isrmstr =
2 dI 2
 Io
-------- + -------- • D
 4
12 
(EQ. 49)
Isrmsfr =
2 dI 2 ( 1 – D ) 2
dI
  Io
----- + ---------------------- + ------------------------------ • ( 1 – D )
  2 2 ( 2 – D )
12 ( 2 – D ) 2 
(EQ. 50)
Isrms =
Isrmstr 2 + Isrmsfr 2
(EQ. 51)
The magnetizing inductance (Lmag) is determined by the
number of turns of primary winding, the core geometry, and
the air gap. The Lmag however should not be designed too
low. If it is too low, high power dissipation will be introduced
in the primary switches, and too much ramp will be added to
15
The required external commutating inductance is
determined by the slower transition (from passive to active
period) since the commutating inductance stores the least
energy for ZVS. The ZVS condition is that the energy stored
in the commutating inductance, defined in EQ. 52, should be
greater than the energy stored in the primary capacitance,
defined in EQ. 53. Thus, the required external commutating
inductance can be roughly estimated with EQ. 54. Refer to
[1] for detailed discussion.
1
E L = --- ( L ext + L k ) • ( Imag + Ip ) 2
2
(EQ. 52)
1
E C = --- ( 2Coss + Cp ) • Vin 2
2
(EQ. 53)
2 • ( 2 • Coss + Cp )
L ext < Vin
------------------------------------------------------------- – Lk
( Imag + Ip ) 2
(EQ. 54)
Note that the output capacitance (Coss) of the MOSFET
varies with the drain to source voltage, and the primary
current (Ip) at the end of the freewheeling period determined
by the turns ratio and current distribution factor FDIST. The
external commutating inductor however would be better
defined in the real circuits by trial and errors.
Control Loop Design
The secondary-referenced, peak current control is
implemented in the converter design. Two pulse
transformers pass the PWM information of the full-bridge
controller (ISL6551) to two high current half-bridge drivers
(HIP2100s) in the primary. A current transformer is to feed
the primary current information to the full-bridge controller,
as a feed-forward loop. The control loop is closed by an error
Application Note 1002
amplifier, for loop compensation purpose, cascaded with a
differential amplifier, for remote sense purpose. Figure 17
shows the block diagram of the overall closed-loop system.
VIN
ISOLATION
PWM
POWER STAGE + OUTPUT FILTER
PRIMARY
DRIVERS
PRIMARY SIDE
+
-
SECONDARY SIDE
HIP2100s
Lo
RAMP
Lo
Co
Ro
MIC4421s
CURRENT TRANSFORMER
SECONDARY
DRIVERS
ERROR AMPLIFIER
DIFFERENTIAL AMPLIFIER
+
-
+
Vo
-
REF.
+
-
FIGURE 17. BLOCK DIAGRAM OF CLOSED-LOOP SYSTEM
This peak current mode controlled system can be simplified
as shown in Figure 18, for setting up an initial feedback
compensation, and EQ. 55 defines the approximate openloop transfer function. The factor “2” in the equation is due to
that only half of the load is sensed by the current
transformer.
2N • Ncs
Hopen ( S ) = ------------------------- • Hd ( S ) • He ( S ) • Zo ( S )
Rcs
(EQ. 57)
Refer to Vatché’s Article [3] for another way of modeling the
loop.
G=2N*Ncs/Rcs
+
-
Co
Zo(S)
ESR
Ro
ESL
ERROR AMP. [He(S)]
DIFFERENTIAL AMP. [Hd(S)]
+
+
-
(EQ. 56)
1
Qp = ------------------------------------------------------------D
π •  Mc •  1 – ---- – 0.5




2
Mc = 1 + Se
------Sn
Vs ( 2 – D )
Rcs
Sn = -------------------------- • --------------------2Lo
N • Ncs
16
+
-
1
Hs ( S ) = ---------------------------------------------------S
S2 1 + ----------------------- + ----------Wn • Qp Wn 2
Se = Sm + Sin
Hopen2 ( S ) = Hopen ( S ) • Hs ( S )
(EQ. 55)
Designers should initially set a low cut-off frequency, such
as 1kHz, system loop with this simplified model as a start
point and then continue to modify the loop under a stable
condition with a design tool such as a Venable System. Note
that the model does not include the slope compensation
component and does not account for subharmonic
oscillation phenomenon in current-mode controlled
converters. The high-frequency correction term given by
EQ. 56 will account for the phenomenon [4].
Wn = π • Fsw
A better representation of the open loop transfer function for
the overall system is defined in EQ. 57:
Vo
REF.
-
FIGURE 18. SIMPLIFIED CLOSED-LOOP MODEL
Application Note 1002
Special Notes for Configuring the ISL6551
The controller can be easily configured using Table 1 in the
ISL6551 datasheet. In this section, several things that
require the users’ attention are highlighted. For a detailed
configuration, please refer to the device datasheet.
• For a tighter tolerance of operating frequency, a 5% NPO
ceramic capacitor is recommended for CT.
• The resonant delay should not be too long, otherwise, the
residual resonant current will flow through the body diode
of the lower FET and additional losses are generated. The
maximum available duty cycle will also be decreased.
• The amount of slope contributed by the magnetizing
current is given by EQ. 58, while the amount of slope
contributed by the internal circuit of the IC is given by
EQ. 59. The overall slope added to the current ramp signal
is the sum of these two equations. An internal ramp
(programmed by a R_RA resistor) might not be required if
the ramp contributed by the Lmag is enough for the slope
compensation.
Vin
Rcs
Sm = ---------------- • ----------Lmag Ncs
(EQ. 58)
BGREF
1
Sin = ---------------------- • -----------------------------R ¬RA 500 ⋅ 10 – 12
(EQ. 59)
• The voltage at ISENSE pin should be scaled appropriately
such that the desired peak current equals or less than
Vclamp-200mV-Vramp, as defined in EQ. 60. In addition,
the turns ratio of the current transformer, Ncs, should be
selected so that power losses at Rcs (current sense
resistor) at the lowest line and the maximum output load is
less than the power rating of one or two SMT0805
resistors so that minimum losses are induced by the Rcs
and less board space is required.
Sin • D
( Vclamp – 200mV ) – ------------------Fclock-----------------------------------------------------------------------------Rcs ≤
Ipripeak
-----------------------Ncs
(EQ. 60)
• The peak current limit set by the PKILIM is lower than the
cycle-by-cycle current limit controlled by the Vclamp in the
reference design for two reasons: 1) ISENSE (at full load)
has to be designed no greater than the minimum
reference voltage (2.64V) at EANI pin, otherwise, the
monotonic output startup at full load cannot be achieved;
and 2) high losses can be introduced if ISENSE (at full
load) is pushed up to the Vclamp (3.75V) with a low turns
ratio (150:1) current transformer. In the reference design,
the ISL6550 would latch the ISL6551 off in overload
conditions.
• The voltage at EANI and EAO should be designed lower
than the Vclamp, otherwise the output will be regulated at
Vclamp and the output load will be limited to the
equivalent current voltage. Since both EANI and EAO are
clamped by the same voltage (Vclamp), the output voltage
would dip if the current ramp exceeds the EAO during the
17
startup, especially for applications with constant current
load. Hence, the EANI should be set higher than EAO,
otherwise, the output voltage cannot have a monotonic
startup. (This problem could be solved by setting the soft
start at the EANI pin instead of the CSS pin allowing the
clamping voltage to come up at a very high speed.) In the
reference design, the synchronous FETs are turned off
during start up achieving monotonic rise for resistive load
applications. The FETs are turned on after a certain load
and then cannot be turned off even back to no-load, which
achieves a better dynamic performance. Users however
can completely remove the current peak detecting circuits
(D23..., they are only handy circuits for users to turned off
the synchronous FETs whenever necessary) and rely on
the R134 and C132 to achieve monotonicity for the output
voltage startup.
• The BGREF should be kept as clean as possible,
otherwise, the over current trip point set at the PKILIM
would be lower than is expected due to the noise/ripple at
the bandgap reference. A low ESR 0.1uF ceramic
capacitor is recommended for decoupling. Due to an
internal race condition, the ISL6551 cannot work properly
without a 399kW resistor connecting between BGREF and
VDD pins. For additional reference load (no more than
1mA), this pull-up resistor should be scaled accordingly
such that the converter can start up properly. In other
words, VDD should source at least the amount of BGREF
external load current through the pull-up resistor.
• The SHARE pin requires a 30kΩ load. A low ESR 0.1uF or
higher ceramic capacitor should be connected to the
CS_COMP pin to design a much lower current loop
bandwidth than that of the voltage regulation loop in
current share operation.
• It is critical that the input signal to ISENSE decays to zero
prior to or during the clock dead time, otherwise, it could
cause severe errors in the signal reaching the PWM
comparator. Examine the current ramp tail of the converter
at maximum duty cycle and full load operations, and
extend the dead time to reset the current ramp tail if
oscillations occur. The C61 in the peak current detecting
circuits (page 6 of the schematics) causes a tail at the
current ramp. If it is removed, a smaller dead time can be
used while maintaining proper operations.
Layout Considerations
• When doing the layout, users should pay special attention
to the VSS and PGND returns (Analog Ground and Power
Ground). VSS is the reference ground, the return of VDD,
of all control circuits and must be kept as clean as
possible from all switching noises. It should be connected
to the PGND in only one location as close to the IC as
practical. For a secondary control system, it should be
connected to the net after the output capacitors, i.e., the
output return pinouts. For a primary control system, it
Application Note 1002
should be connected to the net before the input
capacitors, i.e., the input return pinouts.
land” design for this exposed die pad should include
thermal vias that drop down and connect to buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the MLFP to
achieve its full thermal potential. It is recommended to
connect this pad to the low noise copper plane Vss.
• Heavy copper traces should be connected to the bias pins
(VDD, VDDP1, VDDP2) and the ground pins (VSS and
PGND) for heat spreading.
• The copper routings from the drivers to the FETs should
be kept short and wide, especially in very high frequency
applications, to reduce the inductance of the traces so that
the drive signals can be kept clean, no bouncing.
• For additional tips, please refer to “PCB Design Guidelines
For Reduced EMI” [5].
• In the MLFP package, the pad underneath the center of
the IC is a “floating” thermal substrate. The PCB “thermal
33.3V
34.3V
VIN
LATCH
RESET
ENABLE
(PEN)
8
LATCH
CANNOT
BE RESET
1
LATCH
RESET
2
4
ON/OFF
(START)
LATCHED
PKILIM
> BGREF
ILIM_OUT
(INTERNAL)
3
LATCHED
W/70ms
DELAY
PKILIM < BGREF
5
LATSD
LATCHED
LATCH
RESET BY
VDD
6
VDD
7
8.6V
9.6V
SOFT
START
VOUT
DCOK
(+/-3, 5%)
FAULT
CONVERTER OVERCURRENT VOUT
INPUT
(VOUT < 1-8.33%) BEYOND
DISABLED
TURN-ON
WITH UV DELAY 1+/-8.33%
THRESHOLD
GOOD
MASTER
OV (4.0V)
VDD
VDD
INPUT
TURN-ON TURN-OFF
TURN-OFF
THRESHOLD THRESHOLD THRESHOLD
FIGURE 19. SHUTDOWN TIMING DIAGRAM OF THE CONVERTER
Shutdown Timing Diagram of the Converter
INPUT UV (1): With all the biases powered up and the
mechanical switch at the PEN pin turned on, the converter is
enabled after the input reaches its turn-on threshold (34.3V).
The output voltage rises to its regulation point following the
soft start. The soft start capacitor continues to be charged up
to the clamping voltage (Vclamp). The DCOK is pulled low
indicating “GOOD” once the output reaches within -3% of the
set point.
ENABLE (2): When the PEN pin is pulled low, the soft start
capacitor is discharged very quickly and all the drivers are
disabled. The DCOK is pulled high indicating “FAULT” when
18
the output voltage is discharged below -5% of the set point.
When the PEN pin is released, a soft start is initiated.
OVER CURRENT (3): If the output of the converter is over
loaded, i.e, the PKILIM is above the bandgap reference
(BGREF), the soft start capacitor is discharged quickly and
all the drivers are turned off. Once the output voltage is
below -8.33% of the regulation point, the capacitor of the
under-voltage delay set at ISL6550 is then charged up, and
the START is latched when the voltage at the capacitor
reaches 5V. The ISL6551 controller is quickly shut down by
the START. If the over load is removed and the converter
can return to normal operation within the under-voltage
Application Note 1002
delay (around 70mS), then the START will not be latched.
The latch can be reset by the PEN signal, which is controlled
by the input voltage, the mechanical switch, and the thermal
condition of the converter. If latching the converter off in
overload conditions is not allowed, then version B of
ISL6550 can be used. Then the converter would be running
in hiccup mode in overload conditions.
OUPUT UV & LOCAL OV (4): If the output voltage is
beyond +/-8.33% of the set point and does not reach the
master OV setpoint (4.19V) for any reason, the START is
then latched, so is the converter. The latch can be reset by
the PEN.
OUPTUT MASTER OV (5): If the master OV circuit is
triggered, the LATSD is pulled high and latches the
controller off. The latch can be reset ONLY by cycling VDD.
It CANNOT be reset by toggling ENABLE (PEN).
RESET LATCH (6): The soft start capacitor starts to be
charged after the VDD increases above the ISL6551 and
ISL6550 turn-on thresholds.
VDD UV LOCKOUT (7): The IC is turned off when the VDD
is below the ISL6551 and ISL6550 turn-off thresholds. The
soft start is reset.
INPUT UV LOCKOUT (8): When the input voltage is below
its turn-off threshold 33.3V, the converter is disabled and
latched off. The soft start is reset.
TABLE 1. BDAC OUTPUT PROGRAMMING CODE
#
VID4
VID3
VID2
VID1
VID0
VOUT (V)
17
0
1
1
1
0
3.185
18
0
1
1
0
1
3.216
19
0
1
1
0
0
3.248
20
0
1
0
1
1
3.280
21
0
1
0
1
0
3.312
22
0
1
0
0
1
3.344
23
0
1
0
0
0
3.376
24
0
0
1
1
1
3.408
25
0
0
1
1
0
3.440
26
0
0
1
0
1
3.472
27
0
0
1
0
0
3.504
28
0
0
0
1
1
3.536
29
0
0
0
1
0
3.568
30
0
0
0
0
1
3.599
31
0
0
0
0
0
3.631
Table 2 summarizes major design parameter requirements.
Most components are selected or designed based on these
values. Users should generate a similar table for their
applications and select components with derating guideline
of the datasheet or their own companies.
Summary of Design
TABLE 2. DESIGN PARAMETER REQUIREMENTS
Table 1 is the BDAC output programming code.
PARAMETER
TABLE 1. BDAC OUTPUT PROGRAMMING CODE
CONDITION
VALUE UNIT
DUTY CYCLE AND SWITCHING FREQUENCY
#
VID4
VID3
VID2
VID1
VID0
VOUT (V)
0
1
1
1
1
1
2.642
1
1
1
1
1
0
2.674
2
1
1
1
0
1
2.706
3
1
1
1
0
0
2.738
Cin
4
1
1
0
1
1
2.770
Iinrms
5
1
1
0
1
0
2.801
6
1
1
0
0
1
2.833
Co
7
1
1
0
0
0
2.865
8
1
0
1
1
1
9
1
0
1
1
10
1
0
1
11
1
0
12
1
13
Dmaxav
tDEAD=200ns, tRESDLY=100ns,
Fsw=250kHz
85
%
Fsw
CT=180pF
235
kHz
D=0.5, dVincap=1.65V
3
uF
Vin=48V, D~0.5, Vo=3.63V
5.4
A
fc=Fsw/10=23.5kHz
677
uF
dIo
Lo=0.8uH, Vin=75V, Vo=3.63V
12.9
A
2.897
Iorms
Vin=75V, Lo=8uH, Vo=3.63V
3.4
A
0
2.929
ESR
dVtr = 150mV @ 25% Load Step
10
mΩ
0
1
2.961
1
0
0
2.993
dI
Lo=0.8uH, Vin=75V, Vo=3.63V
16.3
A
0
0
1
1
3.025
Iindpeak
38.2
A
1
0
0
1
0
3.057
Io=60A, Vin=75V, Vo=3.63V
assuming the load evenly distributed
between both output inductors
14
1
0
0
0
1
3.089
Iindrms
A
1
0
0
0
0
3.121
Io=60A, Vin=75V, Vo=3.63V
assuming the load evenly distributed
between both output inductors
34.7
15
16
0
1
1
1
1
3.153
19
INPUT CAPACITORS
OUTPUT CAPACITORS
OUTPUT INDUCTORS
Application Note 1002
TABLE 2. DESIGN PARAMETER REQUIREMENTS (Continued)
PARAMETER
CONDITION
TABLE 3. FULL LOAD POWER LOSSES ANALYSIS
POWER DISSIPATION
AT 60A LOAD
VALUE UNIT
MAIN TRANSFORMER
ELEMENTS
Imag
Lmag=60uH (Limited by Core),
Vo=3.63V, Fsw
0.92
A
Ipripeak
Vin=75V, Vo=3.63V
11.4
A
Iprms
VIN=75V, Vo=3.63V
9.9
A
Isrms
Vin=75V, Vo=3.63V
33.4
A
N
Limited by Core
7:2
-
Nmax
Vin=36V, Vomax=3.63V,
Vmisc=0.3V, Dmaxav=0.85
3.77
-
CURRENT TRANSFORMER
Ncs
150:1
-
36V
175ns
Resonant Time
50ns
Td
40ns
Switching Frequency
235kHz
Transformer Turns Ratio
7:2
Magnetizing Inductance
60uH
Output Inductor
0.8uH
MOSFET Rds(on) Value
at Tj=500C
PRIMARY SIDE
Ipriavgfr
Vin=75V, Vo=3.63V
3.6
A
Ipriavgres
Vin=36V, Vo=3.63V
0.095
A
Iprirms
Vin=75V, Vo=3.63V
4.94
A
Iprirsmtr
Vin=75V, Vo=3.63V
2.57
A
Iprirsmtr
Vin=36V, Vo=3.63V
3.71
Pdr
Each Primary Driver
Vcc(max)=13.2, Qg=50nC x 2 at
VGS=10V, Two Siliconix SUD40N1025
0.42
Pupfet
Vin=75V, Vd=0.78V, Vo=3.63V
4.1
W
Plowfet
Vin=36V, Vd=0.75V, Vo=3.63V with
Td=40n. The worse case could be at
Vin=75 due to switching losses
0.90
W
Upper FETs Conduction
2.616W
3.371W
4.179W
Lower FETs Conduction
0.819w
0.630W
0.427W
Primary Winding Copper
1.023W
1.087W
1.155W
Current Sense Winding
0.110W
0.082W
0.053W
Pinouts of Current Sense
Transformer
1.521W
1.141W
0.731W
A
W
Full Bridge Drivers
0.677W
0.677W
0.677W
SECONDARY SIDE
SYNCHRONOUS FETs
Isynpeak
Vin=75V, Vo=3.63V
66.4
A
Isynrms
Vin=75V, Vo=3.63V
42.5
A
Pdr
Each Secondary Driver
Vcc(max)=13.2V, Qg=30nC x 4 at
VGS=4.5V
Four Siliconix Si4842DY
1.09
W
Vin=75V, Four Siliconix Si4842DYs.
Body Diode Conduction and
Recovery Losses are not Included
Here
2.3
Table 3 summarizes a rough full load power losses analysis
for 3.3V output of the reference design.
20
75V
CALCULATION CONDITIONS
Clock Dead Time
PRIMARY SWITCHES
Psynfet
48V
W
Synchronous FETs
Conduction
2.290W
2.293W
2.296W
Secondary Winding Copper
1.005W
1.054W
1.106W
Output Inductors Copper
2.575W
2.642W
2.716W
Synchronous Drivers
1.805W
1.8056W
1.805W
Current Sense Resistor
0.122W
0.095W
0.063W
Current Sense Rectifiers
0.075W
0.055W
0.034W
OTHERS
R22
0.656W
0.697W
0.741W
PCB Copper
1.096W
1.126W
1.157W
Biases other than Drivers
0.360W
0.360W
0.360W
Guess Overall Magnetics
Core (20% of Conduction)
0.942W
0.973W
1.006w
Miscounted Switching
Losses, Body Diodes
Conduction and Reverse
Recovery Losses at Bridge
FETs and Synchronous
FETs, Contact Resistance,
Clamping Losses, and Error
3.914W
3.492W
5.625W
TOTAL
27.33W
27.87W
31.03W
Application Note 1002
Thoughts After Design
Users can use these thoughts to make some possible
improvements of the reference design.
1. The input capacitors (C13-C15) can be replaced with
ceramic capacitors with smaller footprints such as TDK
SMT1812 C4532X7R2A105M.
2. The output capacitors (2220 footprint) can be replaced
with smaller footprint 1812 capacitors such as the TDK
new product, C4532X5R0J107M.
3. The main transformer (T2) and output chokes (L2 and L3)
are too tall for brick applications with current design form
factors. They can be integrated with the PCB to save
board space and reduce losses. An external inductance
however might be required for ZVS operation because an
integrated PCB transformer would have a very low
leakage inductance, which could not store enough
energy to swing the primary capacitance.
4. The current sense transformer (T4) runs hot due to its
high pinout resistance (more than 10mΩ) and it eats up
too much space, users should redesign the current sense
transformer for better form factor (like J-lead) and thermal
performance. In addition, it cannot be placed
symmetrically in the board due to space constraint. In the
applications of no space limitation, it should be relocated.
5. The overall layout can be improved by removing test
point connectors (TP1-TR34), which are not required in
the real design.
6. The peak current limit set by the PKILIM is lower than the
cycle-by-cycle current limit controlled by the Vclamp, i.e.,
the PKILIM is triggered earlier than the cycle-by-cycle
limit.Thus, the reference-based clamp circuit, for the
cycle-by-cycle current limit accuracy, is not necessary.
7. Users can completely remove the current peak detecting
circuits (D23, C61..., they are only handy circuits for
users to turned off the synchronous FETs whenever
necessary) and rely on the R134 and C132 to achieve
monotonicity for the output voltage startup. The dead
time then can be cut down.
8. R22 can be replaced with a wire for users to look at the
primary current. It is not an ideal zero Ohm, couple milliOhms could induce 0.2% or higher less efficiency.
9. For a narrower range input (48V+/-10%) and/or a lower
output voltage application, a higher turns ratio (4:1) can
improve the efficiency as much as 1%.
Design Tips For Using ISL6551
1. Since the upper FETs carry not only active currents
through their channels but also freewheeling currents
through their body diodes, the power dissipation of the
upper FETs (QA and QD) is higher than the lower FETs
(QC and QB), which can be replaced with smaller size of
MOSFETs such as SO-8 in moderate primary current
applications. The switching losses however should be
taken into account.
2. With assistance of a pre-regulator, the post full-bridge
regulator can be designed to operate at a fixed maximum
duty cycle (~100%). Thus, the freewheeling currents flow
21
through the body diodes of the upper FETs in the shortest
period. The power dissipation of the upper FETs
therefore can be reduced significantly in high primary
current applications. The narrower the input line range is,
the higher the turns ratio of the main transformer can be
chosen, and the higher the efficiency can be achieved.
The power losses and cost of the pre-regulator however
should be taken into account for overall performance
evaluation.
3. An external commutating inductor can be added in series
with the primary side of the transformer to assist ZVS
transitions if the energy stored in the leakage inductance
and the magnetizing inductance is less than the energy
stored in the output capacitance (2*Coss) of the power
switches, the primary capacitance (Cp), and any external
capacitance. Extending the ZVS range with an external
inductor is at the penalties of additional component cost
and less effective duty cycle resulting in a lower turns
ratio, which adds power losses to the primary side.
4. An external capacitor in parallel with the primary side of
the transformer can help lower the dV/dt and the noise
level without introducing additional losses when the zerovoltage switching is still retained. The penalties, as
discussed above, still hold.
5. External high current bridge drivers cascading with the
ISL6551 drivers help absorb the power that supposed to
dissipate in the controller so that the controller is not over
stressed in high gate capacitive load applications, which
extends the application range in a much higher power
level.
6. The higher the switching frequency is, the higher the
system closed-loop bandwidth can be realized, and the
lower the input and output capacitances are required for
overcoming load transients. This, however, comes at the
cost of the efficiency.
7. The current ramp signal to ISENSE should decay to zero
prior to or during the clock dead time. Hence, the dead
time should be set long enough to reset the trailing-edge
tail of the current ramp at the maximum duty cycle
operation, otherwise, oscillations could occur.
8. The leakage inductance of pulse transformers would
induce propagation delay depending on the drive current
through it. The higher the energy through the pulse
transformer is, the longer the delay would be.
9. To save board space, the silk screen text can be deleted,
as some brick manufacturers do today.
10. In the initial design, use a SOD123 diode (such as
MBR0530T1) in series with VDD and VDDP pins to protect
the ISL6551 from being damaged by reverse biasing,
especially for the design with the MLF package, which
cannot to be replaced easily. At the end of the design, the
diode can be substituted with a zero Ohm 805 resistor.
11. For a high current density and multi-layer design, buried
vias can be used to save space, but cost is added.
12. The current share support is for paralleling operation but
not for redundancy. When it is used in redundant
systems, it requires OR’ing circuit inserting between the
converter and the common output bus.
Application Note 1002
Debugging TIPS
This section discusses some easy ways to bring up the
power train in the least amount of time.
Before/After Build
1. Before building the board, it is wise to check if all
magnetics components such as current transformer,
main transformer, output inductors, input inductor, and
commutating inductor are designed properly using
magnetics design tools or waveforms across the
magnetics method. In addition, all components,
especially the power train components, should be
checked if their power/thermal derating guidelines are
met.
3. Increase the input voltage slowly with input and output
current limiting and monitor the current through the main
transformer or the current ramp signal that is fed into the
ISL6551. No asymmetric behaviors should be seen and
ten percent of load is a good start point.
4. If the converter is not stable, use a low ESR ceramic
capacitor (say 0.1uF) at the feedback network to cut
down the cut-off frequency until the converter becomes
stable. Or use the simplified model in Figure 18 to design
a low cut-off frequency system loop. Later, optimize the
loop with a tool.
Apply Biases with Current and Voltage Limiting
5. Enable the synchronous drivers. If the timing is not set
properly, shoot-through currents between the secondary
winding and the synchronous FETs would be induced
and affect the converter’s performance, especially in light
load conditions. Start with some load (10% rated load)
and work backward.
Before applying the input voltage to the converter, a quick
check of all control circuits is always the first step.
6. Check the current ramp signal at the ISENSE pin of
ISL6551 and see if a longer blanking time is required.
2. After the build, check if pin 1 of all ICs is placed properly.
1. Use Table 1 on page 15 of the ISL6551 datasheet design
checklist.
2. Disable anything that prevents both ISL6551 and
ISL6550 from free running. In the reference design,
disconnecting the resistor (R6) between the START pin
of the ISL6550 and the ON/OFF pin of ISL6551 will allow
both chips to be free running.
3. In series forward diodes with the bias lines so that all ICs
will not be damaged by reverse biasing. The reference
design has built-in diodes.
4. Apply biases with current limiting.
5. Check if both DC and AC voltage levels of each ISL6550
pinout are correct. No noises and no over stressed.
6. Check if both DC and AC voltage levels of each ISL6551
pinout are correct. No noises and no over stressed.
7. Check if a nice sawtooth is in CT pin and equal pulse
width is between upper drive signals.
8. Check if both DC and AC voltage levels of drive signals
of bridge FETs and synchronous FETs are correct. No
noises and no over stressed.
9. Check if the delays such as Dead Time, Resonant Delay,
and LEB Delay are designed properly.
10. Check if the timing of the synchronous signals is
designed properly. No shoot through.
Power Up Slowly with Current and Voltage
Limiting
1. If possible, disconnect the secondary winding from the
secondary side, then increase the input voltage slowly.
Fix the primary timing until no (very low) current is drawn
from the input line. And check if the magnetizing current
is in a proper level.
2. Connect the secondary winding back to the circuit and
disable the synchronous drivers such that the current
conducts only through the body diodes of the
synchronous FETs.
22
7. Tune up. Design a proper resonant delay by
programming the R_RESDLY resistor and changing (if
possible) the ZVS elements such as, the magnetizing
inductance, the leakage inductance, any external
commutating inductor, the output capacitance of bridge
FETs, and any external primary capacitance. Note that
any loop that is used to measure the primary current can
induce additional commutating inductance, depending
upon the enclosed air area, and extends the ZVS load
range. For instance, 5.0” of 14AWG wire can contribute
as much as 80nH inductance.
Experimental Results
The evaluation board is intended to test the ISL6551 in a
200W half brick form factor. The specification of this
converter is summarized at the end of this paper. Most of the
converter circuitries are placed in the central 2.50”x2.45”
area and limited within 0.5” height, and all unnecessary
components such as test point connectors and Input/Output
connectors are placed beyond the center.This DC/DC
converter accepts a wide range input, 36V to 75V, and
generates a wide range output, 2.64V to 3.63V with
31.918mV step and 60A full load. An ultra high efficiency,
88% efficiency at 3.3V fully loaded output, has been
achieved. In the following sections, some critical aspects of
the converter are examined with detailed experimental data.
Drive Signal Timing
The drive signals are taken when the ISL6551 is free running,
which can be done by removing the input line and R6 that
connects to the START pin of the ISL6550. The resonant delay
to turn on the lower switch after the corresponding upper switch
is turned off, as shown in Figure 20, helps achieve zero-voltage
switching (ZVS). The dead time to turn on the upper FET after
the corresponding lower switch is turned off, as shown in
Figure 21, helps eliminate the shoot-through currents
through the primary switches during switching transitions.
Figures 22 and 23 show the resonant delay and the dead
Application Note 1002
time set at the ISL6551 prior to be processed through pulse
transformers (T3 andT5) and bridge drivers (Intersil HIP2100).
The dead time and the resonant delay, with 2V as the turn-on
threshold of primary switches, of one converter is summarized
in Table 3. The real delays at the primary switches are shorter
than the “delays” set at the ISL6551 due to long propagation
delays of falling edges of both upper and lower drive signals.
Furthermore, the leakage inductances of pulse transformers
also would induce additional propagation delays depending on
the drive current through it. The higher the energy through the
pulse transformer is, the longer the delay would be.
2
3
1
TABLE 4. RESONANT DELAY AND DEAD TIME
DELAY
AT SWITCH’S GATE
AT ISL6551
Resonant Delay
32 ns
36 ns
Dead Time
157 ns
186 ns
FIGURE 22. RESONANT DELAY AT ISL6551. CHANNEL 1:
LOWER DRIVE SIGNAL; CHANNEL 2 & 3:
UPPER DRIVE SIGNALS
3
3
1
2
2
1
FIGURE 20. RESONANT DELAY AT LOWER FET. CHANNEL
1: LOWER DRIVE SIGNAL; CHANNEL 2 & 3:
UPPER DRIVE SIGNALS
1
2
FIGURE 21. DEAD TIME AT LOWER FET. CHANNEL 1:
LOWER DRIVE SIGNAL; CHANNEL 2 & 3:
UPPER DRIVE SIGNALS
23
3
FIGURE 23. DEAD TIME AT ISL6551. CHANNEL 1: LOWER
DRIVE SIGNAL; CHANNEL 2 & 3: UPPER
DRIVE SIGNALS
The synchronous drive signals are the inverting version of
both lower drive signals with little propagation delays. The
turn-on gate resistors, R23 and R33, soften the rising edge
of the lower drive signals, while the diodes, D5 and D19,
reduce their falling edge delay. Meanwhile, the diodes, D1
and D4, minimize the turn-off delay of the synchronous drive
signals, while the resistors, R3 and R18, increase their turnon delay. As shown in Figure 24, the synchronous FET is
turned off/on (Channel 2) whenever its corresponding lower
switch is turned on/off (Channel 3). There is no overlap
between these two drive signals. Hence, shoot-through
currents between the secondary winding and the
synchronous FETs are eliminated.
Application Note 1002
1
3
2
Figure 29 shows the operation waveforms for INV_SYNC
DRIVE scheme. Since only one synchronous FET is turned
on and conducts currents during the freewheeling period, the
freewheeling current reflected to the primary is higher than
that of the INV_LOW DRIVE scheme. Hence, the INV_LOW
DRIVE scheme produces as much as 2% higher efficiency
than the INV-SYNC DRIVE scheme.
3
4
2
FIGURE 24. SYNCHRONOUS DRIVE SIGNAL. CHANNEL 1:
LOWER DRIVE SIGNAL AT ISL6551; CHANNEL 2:
SYNCHRONOUS DRIVE SIGNAL; CHANNEL 3:
LOWER DRIVE SIGNAL AT THE LOWER FET
Switching Waveforms
WINDING VOLTAGE AND CURRENT
Figures 24 to 29 show the voltage waveforms across the
transformer and the primary currents through it. Note that
the R22 is replaced with a 5.0” of 14AWG wire so that the
primary current can be measured at this loop, which should
be shorted when determining the ZVS load range.
The delay between the primary voltage and secondary
voltage on the leading edge, as shown in Figures 25 and 26,
is caused by the leakage inductance of the transformer. The
input voltage is applied first across the leakage inductor
resetting its current, and the voltage across the real primary
and secondary must stay zero until the current through the
leakage inductor changes in direction and reaches the value
of the reflected load. A higher load results in larger stored
energy in the leakage inductor that needs to be reset before
going into the active mode, and the longer the delay is.
There is almost no delay for zero load operation, as shown
in Figure 27.
As shown in Figure 27, with the synchronous FETs turned
on, the converter still runs at continuous mode (CCM) with a
large duty cycle even at no-load operation. Figure 28 shows
the operation waveforms with synchronous FETs off. In this
case, the synchronous FETs block any negative current,
which forces the converter to run at discontinuous mode
(DCM) cutting down the duty cycle significantly.
24
FIGURE 25. TRANSFORMER WAVEFORMS AT VIN=48V,
VOUT=3.3V, AND IOUT=60A. CHANNEL 4:
PRIMARY CURRENT (IP); CHANNEL 3: PRIMARY
VOLTAGE (VP); CHANNEL 2: SECONDARY
VOLTAGE (VS)
3
2
4
FIGURE 26. TRANSFORMER WAVEFORMS AT VIN=48V,
VOUT=3.3V, AND IOUT=30A. CHANNEL 4:
PRIMARY CURRENT (IP); CHANNEL 3: PRIMARY
VOLTAGE (VP); CHANNEL 2: SECONDARY
VOLTAGE (VS)
Application Note 1002
ZVS TRANSITIONS
3
2
4
FIGURE 27. TRANSFORMER WAVEFORMS AT VIN=48V,
VOUT=3.3V, AND IOUT=0A (SYN ON). CHANNEL 4:
PRIMARY CURRENT (IP); CHANNEL 3: PRIMARY
VOLTAGE (VP); CHANNEL 2: SECONDARY
VOLTAGE (VS)
Figures 30 to 34 show resonant transitions for the lower FET
in various situations, and they are taken by shortening the
loop that is used to measure the primary current. Table 5
summarizes the ZVS conditions of one converter for various
input and output voltages (which do not apply to every
converter since the ZVS conditions of each converter are
heavily dependant upon the leakage inductance and the
output capacitance of the primary switches). In the nominal
48V input and 3.3V output condition, the converter loses
ZVS transitions below 62% of full load, as shown in Figure
31. At the low line (36V) situation, ZVS transitions extend to
42% of full load, as shown in Figure 33, since the energy
stored in the parasitic capacitance is proportional to VIN2
and reaches its minimum. On the other hand, the high line
(75V) completely loses ZVS transitions even at 100% load
since the energy stored in the parasitic capacitance reaches
its maximum and the energy in the commutating inductance
is not enough to resonate the tank to the valley, as shown in
Figure 34.
TABLE 5. ZVS LOAD RANGE
3
VIN\VOUT
2.64V
3.30V
3.63V
36V
<50%
<42%
<33%
48V
<75%
<62%
<58%
75V
>100%
>100%
<92%
2
4
FIGURE 28. TRANSFORMER WAVEFORMS AT VIN=48V,
VOUT=3.3V, AND IOUT=0.5A (SYN OFF).
CHANNEL 4: PRIMARY CURRENT (IP); CHANNEL
3: PRIMARY VOLTAGE (VP); CHANNEL 2:
SECONDARY VOLTAGE (VS)
3
4
2
FIGURE 29. TRANSFORMER WAVEFORMS AT VIN=48V,
VOUT=3.3V, AND IOUT=60A (INV_SYNC DRIVE
SCHEME). CHANNEL 4: PRIMARY CURRENT
(IP); CHANNEL 3: PRIMARY VOLTAGE (VP);
CHANNEL 2: SECONDARY VOLTAGE (VS)
25
FIGURE 30. RESONANT TRANSITION AT VIN=48V, VOUT=3.3V,
AND IOUT=60A. CHANNEL 2: VDS VOLTAGE OF
LOWER FET; CHANNEL 3: LOWER GATE DRIVE
SIGNAL
Application Note 1002
FIGURE 31. RESONANT TRANSITION AT VIN=48V, VOUT=3.3V,
AND IOUT=37A. CHANNEL 2: VDS VOLTAGE OF
LOWER FET; CHANNEL 3: LOWER GATE DRIVE
SIGNAL
FIGURE 34. RESONANT TRANSITION (LOST) AT VIN=75V,
VOUT=3.3V, AND IOUT=60A. CHANNEL 2: VDS
VOLTAGE OF LOWER FET; CHANNEL 3: LOWER
GATE DRIVE SIGNAL
FIGURE 32. RESONANT TRANSITION (LOST) AT VIN=48V,
VOUT=3.3V, AND IOUT=0A. CHANNEL 2: VDS
VOLTAGE OF LOWER FET; CHANNEL 3: LOWER
GATE DRIVE SIGNAL
FIGURE 35. VIN=48V, VOUT=3.3V, AND IOUT=60A. CHANNEL 2:
VDS VOLTAGE OF SYN FET; CHANNEL 3:
SYNCHRONOUS GATE DRIVE SIGNAL
FIGURE 33. RESONANT TRANSITION AT VIN=36V, VOUT=3.3V,
AND IOUT=25A. CHANNEL 2: VDS VOLTAGE OF
LOWER FET; CHANNEL 3: LOWER GATE DRIVE
SIGNAL
FIGURE 36. VIN=48V, VOUT=3.3V, AND IOUT=0A. CHANNEL 2:
VDS VOLTAGE OF SYN FET; CHANNEL 3:
SYNCHRONOUS GATE DRIVE SIGNAL
26
Application Note 1002
As shown in Figures 35 and 36, the synchronous FETs are
zero-voltage switching at turn on, and have negligible
switching losses at turn off during the light load. Nevertheless,
the two bumps, as shown in Figure 35, are caused by the
body diode conduction and/or its reverse recovery at turn on
or off, which do induce losses.
Shutdown Timing (Shorted Circuit, UV, OV)
OUTPUT SHORTED CIRCUIT
When the output is shorted, the START (channel 2) is
latched after the UVDLY (channel 3) capacitor (C26) is
charged above the threshold 5V, as shown in Figure 37.
Note that additional delay is induced by the probe at the
ISL6550 UVDLY pin. If the short is removed and the output
voltage returns to the normal level before the under-voltage
delay, around 70ms, is time out, then the START would not
be latched.
FIGURE 37. OUTPUT SHORTED CIRCUIT. CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: START
SIGNAL; CHANNEL 3: UVDLY AT ISL6550;
CHANNEL 4: OUTPUT CURRENT
OUTPUT UNDER-VOLTAGE DELAY
As shown in Figure 38, the output voltage (Channel 3) has a
huge dip, but it returns to normal level before the undervoltage delay is time out, hence, the START (channel 2) is
not pulled low. Figure 39 shows that the UVDLY starts to rise
when the output voltage is below the under-voltage
threshold, and the START is latched when the UVDLY
reaches 5V threshold.
27
FIGURE 38. OUTPUT UNDER-VOLTAGE DELAY. CHANNEL
1: UVDLY; CHANNEL 2: START SIGNAL;
CHANNEL 3: OUTPUT VOLTAGE
FIGURE 39. OUTPUT UNDER-VOLTAGE DELAY. CHANNEL 1:
UVDLY; CHANNEL 2: START SIGNAL;
CHANNEL 3: OUTPUT VOLTAGE
OUTPUT OVER-VOLTAGE
When the EAI pin is pulled to ground, the error voltage
jumps up and causes an over voltage at the output (channel
1), and the START (Channel 3) is latched, as shown in
Figure 40. The LATSD (Channel 2) is not triggered since the
output voltage does not exceed the master over-voltage
setpoint.
With a quick touch to the output (at zero load) with a 5V
voltage source, both local and master over-voltage setpoints
are violated. Figure 41 shows that the START is triggered at
a lower voltage level than the LATSD. The START is
nominally latched at around 108.33% of the output voltage,
while the LATSD is latched at a higher fixed voltage, around
4.19V and above the maximum BDAC output voltage. The
master over-voltage monitoring circuit is designed with the
bandgap reference of the ISL6551, rather than the ISL6550
internal reference that is used for the local over-voltage
setpoint, about 108.33% of the BDAC voltage. Thus, the
converter can gain additional protection against the failure of
Application Note 1002
the ISL6550 internal reference or mis-configuration of the
ISL6550. For instance, when R40 or R42 is somehow
shorted by debris or solder, the output voltage would be
programmed up to 5V (the reference of ISL6550) and the
local over-voltage setpoint is also moved up relative to the
output voltage level. In a such situation, the master overvoltage circuit will over-ride the local over-voltage setpoint
whenever it is greater than 4.19V and protect the processor
or the load from being over-stressed.
Efficiency Curves
Figures 42 to 44 show the efficiency curves for different
output voltages, and the data are taken at around 400 LFM
airflow with a PAPST-MOTOREN TYP 4600 fan. Each figure
illustrates that the lower the input line is, the higher the
efficiencies at which the converter operates. This is mainly
because the higher the input line is, the lower the duty cycle
is, and the higher the conduction and switching losses of the
primary switches are. Note that the input and output voltages
are measured at TP9 & TP10 and TP4 & TP5, respectively.
Efficiency ( %)
Figure 45 shows the full-load efficiencies of the converter for
various input lines. Each curve shows that the higher the
output voltage is, the higher the efficiency is for the same
reasons, as mentioned above.
FIGURE 40. OVER VOLTAGE (VOUT=3.6V). CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: LATSD
SIGNAL; CHANNEL 3: START SIGNAL
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
36V
48V
75V
0 5 10 15 20 25 30 35 40 45 50 55 60
Iout (A)
FIGURE 41. OVER VOLTAGE (VOUT=3.63V). CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: LATSD
SIGNAL; CHANNEL 3: START SIGNAL
Efficiency ( %)
FIGURE 42. EFFICIENCY CURVES FOR
VOUT=2.64V@~400 LFM
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
36V
48V
75V
0 5 10 15 20 25 30 35 40 45 50 55 60
Iout (A)
FIGURE 43. EFFICIENCY CURVES FOR
VOUT=3.3V @~400 LFM
28
Efficiency ( %)
Application Note 1002
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
36V
48V
75V
Figure 48 shows the case temperature of the current sense
transformer (T4). At low line, the case temperature is much
higher since the current ramp through the current sense
transformer has a larger duty cycle and produces a higher
RMS value and higher resistive losses.
Figures 49 and Figure 50 show the case temperature of the
main transformer (T2) and a synchronous FET (Q1),
respectively.
0 5 10 15 20 25 30 35 40 45 50 55 60
Iout (A)
Figure 51 shows the synchronous driver (M2) case
temperature. The curves in this figure look flatter than those
in other figures since the driver losses heavily depend on the
gate charge of the synchronous FETs (which remains almost
constant), rather than the output load.
FIGURE 44. EFFICIENCY CURVES FOR
VOUT=3.64V @~400 LFM
90
Efficiency (%) at 60A
Figure 47 shows the case temperature of the lower FET
(Q17). The higher the input voltage is, the higher the
switching losses of the lower FET are. At the high line, the
case temperature of the FET rises significantly since ZVS
transitions are completely lost and the switching losses
dominate the channel conduction losses.
Figure 52 shows the case temperature of an output inductor
(L2). At the high line, the inductor gets hotter since the ripple
current as well as its RMS value is higher.
89
88
36V
87
48V
86
75V
85
84
2.6
2.8
3
3.2
3.4
3.6
The data points in Figures 53 to Figure 59 are taken at
various output and full load operating conditions with around
400 LFM airflow. As shown in these figures, the worst
operating point is at the high line and maximum output
voltage for all cases except the current sense transformer
(T4), which has its worst operating point at the low line and
maximum output voltage.
3.8
Vout (V)
THERMAL DATA
The thermal data are taken with a Fluke 80T-IR Infrared
Temperature Probe at 210C ambient temperature while a
PAPST-MOTOREN TYP 4600 fan (estimated around 400
LFM or more) is placed vertically 2.0” away from the input
end of the converter. The data are used only for a relative
comparison purpose, therefore, users should not do any
thermal derating based on these thermal curves because the
data points are not necessarily presenting the absolute
values at the operating condition.
The data points in Figures 46 to 52 are taken at VOUT=3.3V.
Figure 46 shows the upper FET (Q14) case temperature.
The higher the input voltage is, the longer the freewheeling
period is, therefore, the higher the conduction losses of the
upper FET is. Thus, the case temperature is higher at the
high line.
29
C)
0
Case Temperature (
FIGURE 45. EFFICIENCY AT 60A FOR
DIFFERENT VOUT @~400 LFM
60
55
50
45
36V
40
48V
35
75V
30
25
20
20
25
30
35
40
45
50
55
60
Output Load (A)
FIGURE 46. UPPER FET (Q14) CASE TEMPERATURE
Application Note 1002
60
55
C)
0
50
45
36V
40
48V
35
75V
30
25
Case Temperature (
Case Temperature (
0
C)
55
20
50
45
36V
40
35
48V
30
75V
25
20
20
25
30
35
40
45
50
55
60
20
25
Output Load (A)
40
45
50
55
60
FIGURE 50. SYNCHRONOUS FET (Q1) CASE TEMPERATURE
65
85
80
75
70
65
60
55
50
45
40
35
30
25
20
0
C)
60
36V
48V
75V
Case Temperature (
C)
0
35
Output Load (A)
FIGURE 47. LOWER FET (Q17) CASE TEMPERATURE
Case Temperature (
30
55
50
36V
45
48V
40
35
75V
30
25
20
20
25
30
35
40
45
50
55
60
20
25
Output Load (A)
30
35
40
45
50
55
60
Output Load (A)
FIGURE 51. SYNCHRONOUS DRIVER (M2) CASE
TEMPERATURE
FIGURE 48. CURRENT TRANSFORMER (T4) CASE
TEMPERATURE
.
70
55
50
0
C)
60
55
36V
50
45
48V
40
35
75V
30
25
20
Case Temperature (
Case Temperature (
0
C)
65
45
36V
40
35
48V
30
75V
25
20
20
25
30
35
40
45
50
55
60
Output Load (A)
FIGURE 49. MAIN TRANSFORMER (T2) CASE TEMPERATURE
30
20
25
30
35
40
45
50
55
60
Output Load (A)
FIGURE 52. OUTPUT INDUCTOR (L2) CASE TEMPERATURE
Application Note 1002
75
C)
0
55
2.64V
50
3.3V
3.63V
45
Case Temperature (
Case Temperature (
0
C)
60
40
70
65
2.64V
60
3.3V
55
3.63V
50
45
40
35
45
55
65
75
35
Input Voltage (V)
C)
0
55
2.64V
50
3.3V
3.63V
45
Case Temperature (
C)
0
Case Temperature (
75
55
40
50
2.64V
3.3V
45
3.63V
40
35
45
55
65
75
35
Input Voltage (V)
45
55
65
75
Input Voltage (V)
FIGURE 54. LOWER FET (Q17) CASE TEMPERATURE
FIGURE 57. SYNCHRONOUS FET (Q1) CASE TEMPERATURE
65
85
80
75
70
60
0
C)
95
90
2.64V
3.3V
65
60
55
50
3.63V
45
40
Case Temperature (
C)
65
FIGURE 56. MAIN TRANSFORMER (T2) CASE TEMPERATURE
60
0
55
Input Voltage (V)
FIGURE 53. UPPER FET (Q14) CASE TEMPERATURE
Case Temperature (
45
2.64V
55
3.3V
50
3.63V
45
40
35
45
55
65
75
Input Voltage (V)
FIGURE 55. CURRENT TRANSFORMER (T4) CASE
TEMPERATURE
31
35
45
55
65
75
Input Voltage (V)
FIGURE 58. SYNCHRONOUS DRIVERS (M2) CASE
TEMPERATURE
Application Note 1002
55
50
2.64V
3.3V
45
3.63V
40
35
45
55
65
Current Share (%, Slave wrt Master)
Case Temperature (
0
C)
45
75
40
35
30
25
48V-3.3V
20
75V-2.64V
15
36V-3.63V
10
5
0
0
5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Load Current (A)
FIGURE 59. OUTPUT INDUCTOR (L2) CASE TEMPERATURE
35
Current of Maste or Slave Unit
As shown in the figures above, the current transformer and
the main transformer are the hottest components. Without
any airflow, their case temperatures would rise significantly
and exceed the device ratings at heavy load operations.
Users should do a more thorough analysis at the worst case
operating condition to evaluate thermal stress of each
device. The current transformer is roughly measured to be
above 130°C at room ambient temperature, 48V input and
3.3V, 50A output without any airflow due to its heavy glossy
pinout, so it is recommended that users redesign the current
sense transformer for a better form factor and thermal
performance.
FIGURE 60. CURRENT SHARE CURVES
30
48V-3.3VM
25
48V-3.3VS
20
75V-2.64VM
15
75V-2.64VS
10
36V-3.63VM
5
36V-3.63VS
0
Current Share
Two equal length (3 inch) and size (10 AWG) wires split the
load into each individual converter, thus, the impedance
mismatching of current-carrying traces from the converters
to the load is minimized. The current delivered by each
converter is measured with only one current probe to reduce
measurement error. With this kind of setup and
measurement method, impedance difference and
measurement error are still greater than that of building both
converters in a board with a symmetric layout and measuring
the current with precise current sense resistors. The
measurement error increases with decreasing load.
Figure 60 shows current share curves at various input lines
and output voltages. The current sharing is inversely
proportional to the load, and the slave unit can share the
load within 5% of the master unit at full load operation. Since
the offset of the error amplifier and the difference of the
output reference as well as the difference of power train
components between both units remains constant, the
difference of the load currents delivered by the master and
the slave units almost remains constant, as shown in Figure
61. In addition, at no-load operation, the master unit will
source current into the slave units because the higher
voltage (master) back drives the lower voltage (slave).
32
5 10 15 20 25 30 35 40 45 50 55 60
Load Current (A)
FIGURE 61. CURRENT OF MASTER AND SLAVE UNIT
3
2
1
4
FIGURE 62. TURN ON SLAVE (CHANNEL 3 AND CHANNEL 2)
FIRST. MASTER: CHANNEL 4 AND CHANNEL 1
Application Note 1002
3
2
1
4
FIGURE 63. TURN ON MASTER (CHANNEL 3 AND
CHANNEL 1) FIRST. SLAVE: CHANNEL 4 AND
CHANNEL 2
FIGURE 64. TRANSIENT RESPONSE FOR VIN=75V AND
VOUT = 2.64V AT 0A-15A STEP, 1A/us
Figures 62 and Figure 63 show the interaction between
master and slave units in two different turn-on sequences.
When the slave unit is turned on first, it acts as a “master”
during the start up of the master unit. It takes a longer time
for both converters to switch back to their proper roles
settling down than that of the master unit is turned on first.
Step Responses
This section summarizes step responses of the converter at
various input lines and output voltages (Figures 64 to 69). In
all the figures of this section, Channel 4 represents the load
step, and channel 1 represents the output voltage. For
transients from 45A to 60A, channel 4 shows only 1/4 of the
load. Table 6 summarizes the transient voltage spikes at
different operating conditions. Note that the measurement is
including the ripple voltage. The actual transient voltages
excluding the ripple voltage should be smaller and not very
different in all cases since the cut-off frequency and the
corresponding phase of the loop for all cases are very close,
as illustrated in the Loop Response section.
FIGURE 65. TRANSIENT RESPONSE FOR VIN=75V AND
VOUT = 2.64V AT 45A-60A STEP, 1A/us
TABLE 6. TRANSIENT RESPONSE
INPUT OUTPUT
LOAD STEP
TRANSIENT
Vp-p
1/2 Vp-p
75V
2.64V
0-15A, 1A/us
353mV
177mV
75V
2.64V
45-60A, 1A/us
350mV
175mV
48V
3.30V
0-15A, 1A/us
328mV
164mV
48V
3.30V
45-60A, 1A/us
319mV
160mV
36V
3.63V
0-15A, 1A/us
316mV
158mV
36V
3.63V
45-60, 1A/us
306mV
153mV
FIGURE 66. TRANSIENT RESPONSE FOR VIN=48V AND
VOUT = 3.3V AT 0A-15A STEP, 1A/us
33
Application Note 1002
Loop Response
The experimental results presented in this section are
measured with a 350 Venable system. The injection point is
at R131 instead of R76 since R76 is located at noise
sensitivity nodes.
Since it is a current mode control system, the transfer
function of the plant is mainly determined by the
characteristic of the load including the output resistive,
capacitive, and inductive impedance, all of which varies with
different applications.
FIGURE 67. TRANSIENT RESPONSE FOR VIN=48V and
VOUT = 3.3V AT 45A-60A STEP, 1A/us
We had only five 25W 0.1Ω “pure” resistive loads available
for testing in our lab. A 38A load was constructed with these
five resistors for 3.3V output. As shown in Figure 70, the
load can be characterized as a 0.086Ω resistor in series with
260 nH inductance induced by the two 5.0” 10AWG wires
that connect to the load. The open loop response slightly
varies with the input voltage, as shown in Figure 71.
Gain (dB) and Phase (Degrees)
90
80
Measured
Gain
70
60
50
Measured
Phase
40
30
Model
Gain
20
10
0
Model
Phase
-10
-20
-30
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Fre que ncy (Hz)
FIGURE 68. TRANSIENT RESPONSE FOR VIN=36V AND
VOUT = 3.63V AT 0A-15A STEP, 1A/us
FIGURE 70. RESISTIVE LOAD CHARACTERISTIC
PHASE
GAIN
FIGURE 69. TRANSIENT RESPONSE FOR VIN=36V AND
VOUT = 3.63V AT 45A-60A STEP, 1A/us
34
FIGURE 71. OPEN LOOP RESPONSE FOR [email protected]
RESISTIVE LOAD. RED-48V, BLUE-75V, AND
BLACK-36V
Application Note 1002
3
GAIN
1
2
PHASE
FIGURE 72. PLANT FREQUENCY RESPONSE FOR [email protected]
RESISTIVE LOAD. RED-48V, BLUE-75V, AND
BLACK-36V
FIGURE 74. PLANT RESPONSE FOR THREE KINDS OF
LOADS AT 48V, [email protected] RED(1)-”PURE”
RESISTIVE LOAD, BLUE(2)-ELECTRONIC
CONSTANT CURRENT LOAD, AND BLACK(3)ELECTRONIC RESISTIVE LOAD.
2
4
3
1
AREA OF INTEREST
FIGURE 73. FREQUENCY RESPONSE OF 1) PLANT (Vo/Ve),
2) FEEDBACK COMPENSATION,
3) DIFFERENTIAL AMPLIFIER, AND
4) OPEN LOOP FOR VIN=48V, [email protected]
RESISTIVE LOAD. RED-GAIN AND BLUE-PHASE
Figure 73 shows three portions of the system loop for 3.3V
38A resistive loaded output: 1) Plant (Vo/Ve), 2) Feedback
compensation, and 3) Differential amplifier. The overall loop
is the sum of these components, in which the feedback
compensation and the differential amplifier are fixed elements
and the plant is a variable depending on the load.
Figure 75 shows loop responses for three different types of
loads: “pure” resistive load, electronic constant current load,
and electronic resistive load. The responses vary
significantly at low frequencies, but the frequencies of
interest that define the phase margin and gain margin shift
little at high frequencies, therefore, the system stability can
be studied by just looking at the loop response against the
constant current load.
35
FIGURE 75. OPEN LOOP RESPONSE FOR THREE KINDS OF
LOADS AT 48V, [email protected] RED-”PURE”
RESISTIVE LOAD, BLUE-ELECTRONIC
CONSTANT CURRENT LOAD, AND BLACKELECTRONIC RESISTIVE LOAD
Figures 76 to 81 show loop responses for various input and
output conditions including four corners. It can be concluded
that the system is stable in under all input and output
operating conditions since it has a 20-30kHz loop bandwidth,
around 10dB gain margin, and above 45o phase margin.
One thing that should be noted is that the tail of the gain,
caused by the ESL of output capacitors, at above 200kHz
increases with the frequency. If it still exists and causes a
problem in a real system, users can lower the pole at the
differential amplifier stage to smooth it out (say 100pF for
both C27 and C28). The gain of the feedback compensation
however should be adjusted, as necessary, to design a
favorable gain margin and phase margin system.
Application Note 1002
FIGURE 76. OPEN LOOP RESPONSE FOR [email protected]
CONSTANT CURRENT LOAD. RED-48V, BLUE75V, AND BLACK-36V
FIGURE 77. OPEN LOOP RESPONSE FOR [email protected]
CONSTANT CURRENT LOAD. RED-48V, BLUE75V, AND BLACK-36V
FIGURE 78. OPEN LOOP RESPONSE FOR [email protected]
CONSTANT CURRENT LOAD. RED-48V,
BLUE-75V, AND BLACK-36V
36
FIGURE 79. OPEN LOOP RESPONSE FOR 2.64V
@6A CONSTANT CURRENT LOAD. RED-48V,
BLUE-75V, AND BLACK-36V
FIGURE 80. OPEN LOOP RESPONSE FOR [email protected]
CONSTANT CURRENT LOAD. RED-48V,
BLUE-75V, AND BLACK-36V
FIGURE 81. OPEN LOOP RESPONSE FOR [email protected]
CONSTANT CURRENT LOAD. RED-48V, BLUE75V, AND BLACK-36V
In addition to the above loop measurement, the following
presents some modeling results using the simplified loop
system including the high-frequency correlation term as
discussed in the Control Loop Design section on page 16.
The feedback compensation and the differential amplifier
stages are verified with the 350 Venable System, as shown
in Figures 82 and 83. They are well matched with the
theoretical results except that the phase at the differential
amplifier stage is smaller at above 100kHz than is expected.
In addition, each TAIYO YUDEN capacitor is characterized
with 100uF capacitance in series with 1.8mΩ ESR and
6nH ESL as defined in EQ. 61, which is also verified with
the Venable System.
1
Zcap ( jω ) = --------------------------------- + 1.8x10 – 3 + jω6x10 – 9
jω100x10 – 6
Gain (dB) and Phase (Degrees)
Application Note 1002
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
1.0E+02
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Frequency
Fe que
ncy (Hz)(Hz)
(EQ. 61)
FIGURE 84. OUTPUT CAPACITOR MODELING
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Measured
90
Gain
80
70
60
Measured
50
Phase
40
30
20
10
Model
0
Gain
-10
-20
-30
Model
1.0E+0 1.0E+0 1.0E+0 1.0E+0 1.0E+0
Phase
2
3
4
5
6
Gain (dB) and Phase (Degrees)
Gain (dB) and Phase (Degrees)
Thus, the only variable is the plant, i.e., the load and the
power train.
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase
Frequency
Frequency(Hz)
(Hz)
Fequency
(Hz)(Hz)
Frequency
FIGURE 85. OUTPUT LOAD
10
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
1.0E+02
20
Measured
Gain
Measured
Phase
Model
Gain
Model
Phase
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Frequency
Fequency
(Hz)(Hz)
FIGURE 83. DIFFERENTIAL STAGE
37
Gain (dB) and Phase (Degrees)
Gain (dB) and Phase (Degrees)
FIGURE 82. COMPENSATION STAGE
0
-20
-40
Measured
Gain
-60
-80
Measured
Phase
-100
-120
-140
Model
Gain
-160
-180
Model
Phase
-200
-220
-240
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Frequency
Fequency
(Hz)(Hz)
FIGURE 86. PLANT RESPONSE FOR 38A “PURE” RESISTIVE
LOAD
140
140
120
120
100
Measured
Gain
80
60
Measured
Phase
40
20
0
Model
Gain
-20
-40
-60
Model
Phase
-80
-100
1.0E+02
1.0E+03
1.0E+04
1.0E+05
Gain (dB) and Phase (Degrees)
Gain (dB) and Phase (Degrees)
Application Note 1002
Measured
Gain (60A)
100
Measured
Phase (60A)
80
60
Measured
Gain (6A)
40
Measured
Phase (6A)
20
Model Gain
(60A)
0
-20
Model
Phase (60A)
-40
Model Gain
(6A)
-60
AREA OF INTEREST
-80
-100
1.0E+02
1.0E+06
Model
Phase (6A)
1.0E+03
Fequency (Hz)
1.0E+04
1.0E+05
1.0E+06
Fequency (Hz)
FIGURE 87. LOOP RESPONSE FOR 38A “PURE”
RESISTIVE LOAD
FIGURE 89. LOOP RESPONSE FOR 75V, [email protected] AND 60A
Output Voltage
The measured loop and plant responses for 48V input and
3.3V output with the resistive load, which is characterized in
Figure 85, have a reasonable match with that of the
simplified model, as shown in Figure 87.
The loop response in overall “pure” resistive load conditions
was not tested. Instead, an electronic constant current load
was used. The results are not significantly off from that of the
“pure” resistive load within the frequencies of interest, as
shown in Figure 75. Figures 88 and Figure 89 show a good
prediction of phase margin and gain margin of the system
using the simplified model in overall operating conditions.
140
Gain (dB) and Phase (Degrees)
120
M e as ure d
Gain (60A)
100
M e as ure d
Phas e (60A)
80
60
M e as ure d
Gain (6A)
40
The output ripple voltage in different operating conditions is
no greater than 60mV, as summarized in Table 7. The
results show that the output has the largest output ripple
voltage at the highest input line and the highest output
voltage since the highest output ripple current is at this
operating point. Note that the ripple current in the table is not
for discontinuous mode. Figure 90 shows the converter
operating in burst mode at very light load. Figure 93 and 94
show the converter operates at 48V, 3.3V, and 0.5A load
with synchronous FETs turned off and on, respectively. The
one with synchronous FETs turned on has a larger duty
cycle than the one with synchronous FETs turned off, which
runs at discontinuous mode since the body diodes of the
turned-off FETs block the output inductor current from
flowing negatively. Note that the channel 1 represents the
output ripple voltage and the channel 3 represents the
voltage across the secondary winding.
M e as ure d
Phas e (6A)
20
0
TABLE 7. OUTPUT VOLTAGE RIPPLE
M ode l Gain
(60A)
-20
-40
-60
-80
OUTPUT RIPPLE VOLTAGE
AREA OF INTEREST
-100
-120
1.0E+02
1.0E+03
1.0E+04
1.0E+05
M ode l
Phas e (60A)
VIN
VOUT
0.5A SYN
OFF
0.5A SYN
ON
60A
LOAD
RIPPLE
CURRENT
M ode l Gain
(6A)
36V
3.63V
21.9mV
25.0mV
32.8mv
5.4A
M ode l
Phas e (6A)
48V
3.31V
25.0mV
28.1mV
34.4mV
9.0A
75V
2.64V
56.2mV
37.5mV
48.4mV
10.8A
75V
3.63V
59.4mV
46.9mV
59.4mV
12.9A
1.0E+06
Fequency (Hz )
FIGURE 88. LOOP RESPONSE FOR 36V, [email protected] AND 60A
38
Application Note 1002
FIGURE 90. OUTPUT VOLTAGE RIPPLE (CHANNEL 1) AT
VIN=75V, VOUT=3.63V, AND IOUT=0.5A. SYN OFF
FIGURE 93. OUTPUT VOLTAGE RIPPLE (CHANNEL 1) AT
VIN=48V, VOUT=3.3V, AND IOUT=0.5A. SYN OFF
FIGURE 91. OUTPUT VOLTAGE RIPPLE (CHANNEL 1) AT
VIN=75V, VOUT=3.63V, AND IOUT=0.5A. SYN ON
FIGURE 94. OUTPUT VOLTAGE RIPPLE (CHANNEL 1) AT
VIN=48V, VOUT=3.3V, AND IOUT=0.5A. SYN ON
FIGURE 92. OUTPUT VOLTAGE RIPPLE (CHANNEL 1) AT
VIN=75V, VOUT=3.63V, AND IOUT=60A
FIGURE 95. OUTPUT VOLTAGE RIPPLE (CHANNEL 1) AT
VIN=48V, VOUT=3.3V, AND IOUT=60A
39
Application Note 1002
Output Start Up
The start up characteristic of the output voltage heavily
depends on the load. For a “pure” resistive load or an
electronic load with low slew rate (0.01A/us), the output
voltage comes up smoothly, as shown in Figures 96 and 97.
In the case of high slew rate electronic load, the
monotonicity of the output voltage is lost, as shown in
Figures 98 and 99. During the startup, the load demands
more current than what the converter can deliver, which
causes the output dipping. The higher the load is, the higher
the current ramp is needed, and the higher the error voltage
is required to push the duty cycle up further. The error
voltage is limited by the soft start voltage (Vclamp) that
comes up with a slower speed, therefore, the duty cycle is
limited causing repetitive up/downs at the output voltage, as
shown in Figure 100. For applications with similar behavior
of the electronic load, this problem can be resolved by
speeding up the startup of the soft start with two possible
options: 1) increase the soft start speed above the start-up
speed of the error voltage by reducing the capacitive load at
the CSS pin of ISL6551; or 2) set the soft start at the output
reference pin (EANI) and completely remove all capacitive
load at the CSS pin. In general, the second option is the
practical one. Note that the delay at the electronic load is
caused by its turn-on threshold.
FIGURE 97. OUTPUT VOLTAGE (CHANNEL 1) AT VIN=75V,
VOUT=2.64V, AND IOUT=60A, 0.01A/US
ELECTRONIC CONSTANT CURRENT MODE
(CHANNEL 4, 1/4 OF THE LOAD)
FIGURE 98. OUTPUT VOLTAGE (CHANNEL 1) AT VIN=75V,
VOUT=2.64V, AND IOUT=60A, 1A/US ELECTRONIC
RESISTIVE MODE (CHANNEL 4, 1/4 OF THE LOAD)
3
1
FIGURE 96. OUTPUT VOLTAGE (CHANNEL 1) AT VIN=48V,
VOUT=3.3V, AND 0.083Ω RESISTIVE LOAD
2
4
FIGURE 99. OUTPUT VOLTAGE (CHANNEL 1) AT VIN=48V,
VOUT=2.64V, AND IOUT=60A, 1A/US ELECTRONIC
CONSTANT CURRENT MODE. CHANNEL 2:
ERROR VOLTAGE; CHANNEL 3: VCLAMP
VOLTAGE; CHANNEL 4: CURRENT RAMP
(ISENSE). EACH CHANNEL IS 1V/DIV AND
2MS/DIV.
40
Application Note 1002
FIGURE 100. OUTPUT VOLTAGE STARTUP EXPANSION
(CHANNEL 1) AT VIN=48V, VOUT=2.64V, AND
IOUT=60A, 1A/US ELECTRONIC CONSTANT
CURRENT MODE. CHANNEL 2: ERROR
VOLTAGE; CHANNEL 3: VCLAMP VOLTAGE;
CHANNEL 4: CURRENT RAMP (ISENSE).
100US/DIV.
FIGURE 101. VIN=48V, VOUT=3.3V, IOUT=60A ELECTRONIC LOAD
WITH NO ADDITIONAL CAP. CHANNEL 1: OUTPUT
VOLTAGE; CHANNEL 2: SYNCHRONOUS FET GATE
SIGNAL; CHANNEL 4: OUTPUT CURRENT
Output Turned Off Characteristic
When the converter is turned off by an operator or a fault,
the energy stored in the output inductors and capacitors is
dissipated in the parasitic resistance of the output inductors
and capacitors, the load, and the synchronous FETs.
In Figure 101, the output current lags by 90° from the output
voltage, which means that the output load (electronic load)
behaves inductively when the converter is turned off. Note
that the electronic load is not activated until its input is above
0.95V. The delay to turn off the synchronous FETs is
induced by the C60 and C58 in the peak current detecting
circuit on page 6 of the schematics, which allows negative
currents through the Channels during this period. Since the
electronic load does not behave resistively and the losses
due to the Rds(on) of the synchronous FETs are relatively
small, the output L-C resonant tank cannot be heavily
dampened, which causes the output ringing down to an
undesired negative voltage (-2V). With an 1000uF Aluminum
capacitor at the output, the resonant frequency decreases
but the stored energy increases; however, the negative
spike does cut down by a small amount, as shown in Figure
102. With the assistance of additional output capacitance
and additional circuits, as shown on page 6 of the
schematics (D131...), to turn off the synchronous FETs by a
fault or an operator, the negative spike is reduced to an
acceptable level (200mV), as shown in Figure 104. Note that
the 1000uF Aluminum capacitor at the output is necessary to
help reduce the negative spike to a controllable level.
FIGURE 102. VIN=48V, VOUT=3.3V, IOUT=60A ELECTRONIC LOAD
WITH 1000uF ALUMINUM CAPACITOR. CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: SYNCHRONOUS
FET GATE SIGNAL; CHANNEL 4: OUTPUT CURRENT
FIGURE 103. VIN=48V, VOUT=3.3V, IOUT=60 ELECTRONIC LOAD
WITH NO ADDITIONAL CAP. CHANNEL 1: OUTPUT
VOLTAGE; CHANNEL 2: SYNCHRONOUS FET
GATE SIGNAL; CHANNEL 4: OUTPUT CURRENT
41
Application Note 1002
As shown in Figure 105, the output voltage and the output
current are in phase since the load is resistive (two DALE
NH-25 25W 0.1W in parallel, they operate for only a short
period due to their power ratings). The negative spike is
much smaller than that of the previous case because the
load helps dissipate some of the residual energy. When the
synchronous FETs are turned off at the shutdown of the
converter, the body diodes of the synchronous FETs help
dissipate a large portion of the energy and block any
negative current through the output inductors resulting in
zero negative spike, as shown in
Figure 106. In this case, no extra capacitor is required.
Equipment List
FIGURE 104. VIN=48V, VOUT=3.3V, IOUT=60A ELECTRONIC LOAD
WITH 1000UF ALUMINUM CAPACITOR. CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: SYNCHRONOUS
FET GATE SIGNAL; CHANNEL 4: OUTPUT CURRENT
FIGURE 105. VIN=48V, VOUT=3.3V, IOUT=60A PURE RESISTIVE
LOAD WITH NO ADDITIONAL CAP. CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: SYNCHRONOUS
FET GATE SIGNAL; CHANNEL 4: OUTPUT
CURRENT
FIGURE 106. VIN=48V, VOUT=3.3V, IOUT=60A PURE RESISTIVE
LOAD WITH NO ADDITIONAL CAP. CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: SYNCHRONOUS
FET GATE SIGNAL; CHANNEL 4: OUTPUT
CURRENT
42
TABLE 8. EQUIPMENT LIST
EQUIPMENT
EQUIPMENT DESCRIPTIONS
Boards Used
ISl6551EVAL1 Rev. B, #1, #2, #3, & #4
Power Supplies
1. HP 6653A S/N: 3621A-03425
2. Lamda LQ521 S/N: J 3570
3. XANTREX 100-10 S/N: 72963
4. XANTREX 100-6 S/N: 66287
5. HP6205C S/N: 2411A-06136
Oscilloscope
LeCroy LT364L S/N: 01106
Differential Probe
Hewlett Packard HP1141A
Multimeters
Fluke 8050A S/N: 2466115 & 3200834
Load
1. Chroma 63103 S/N: 631030002967
2. Chroma 63103 S/N: 631030003051
3. Four DALE NH-25 25W 0.1Ω 1%
Current Probe Amplifier
LeCroy AP015 SN: 970139
Temperature Probe
Fluke 80T-IR Infrared Temperature
Probe (93/09)
Fan
POPST-MOOREN TYP 4600X (4098547)
Schematics Description
There are six pages of schematics. On the first page is the
secondary side power train including the output filter and the
synchronous rectifiers with their drivers. Additional circuits
are used to turn off the synchronous FETs during the start
up and to clamp the ringings across the FETs on the leading
edge. On page 2 is the primary power train. It consists of an
input filter, current transformer, main transformer, pulse
transformer, and full-bridge power switches with their
drivers. On page 3 are the main supervisor circuits ISL6550
with some external resistor components, which can
differentially sense the output voltage, set the output undervoltage and over-voltage protection, program the output
reference with four VID inputs, and set an appropriate output
under-voltage lockout delay. On page 4 are the full-bridge
controller and the master over-voltage circuit. On page 5 are
the input under-voltage and thermal condition detecting
circuits. The circuits on the last page are used to monitor the
output load level during the start up. It turns off the
synchronous FETs during the start up at low load conditions.
Application Note 1002
5.00”
PC1 & PC4
BJ17
BJ1, BJ2, C12, F1, & L1
FIGURE 107. COMPONENT PLACEMENT OUTLINE
ON TOP LAYER
SBJ1 & BJ2
SW1
SYN1 FETS
& Driver (p1)
CS XFMR &
CS Rectifiers
Test
Test Points
SW2
Pri. FETs
HIP2100
Test Points
Main
XFMR
6.45”
HIP2100
BJ3, BJ4, &C16
Output
Inductors
Test Points
SYN2 FETS
& Driver (p1)
BJ5, BJ6, &C32
TP4 & TP5
Input UV &
Thermal(p5)
2.50”
The components of the converter are placed on both top and
bottom layers within a particular area. Figures 107 and 108
show where each portion of circuit is placed on both layers.
Since it is a high current density design, 10 layers with 4 oz
copper have been used in the PCB layout. In addition, a
buried vias technique has also been applied. A careful and
proper layout helps to lower EMI and reduce bugs and
development time. Users should use as much time as
needed and is possible to layout the board very carefully
following guidance. Some guidance for laying out the
reference design is discussed in the Layout Considerations
section on page 17. Refer to [5] for additional layout
guidelines.
Output Capacitors
Pulse XFMRs
T3 & T5
Input Caps (p2)
ISL6551(p4)&
ISL6550
Bridge Driver
(p3)
Clamp Diode(p2)
Layout
LL_SYNOFF(p6)
& Master OV(p4)
Once the FETs are turned on, they will not be turned off
again unless the converter re-start up at low load conditions.
In addition to that, some circuits are used to turn off the
synchronous FETs at a high speed to eliminate any negative
voltage spike when the converter is shut down by an
operator or a fault.
2.45”
FIGURE 108. COMPONENT PLACEMENT OUTLINE
ON BOTTOM LAYER
Conclusion
The ZVS technique of the ISL6551 full-bridge controller is
presented. The superior performance of the ISL6551, with its
companions Intersil’s HIP2100 half-bridge driver and
ISL6550 Supervisor And Monitor, has been demonstrated in
the reference design of a 200W, 470kHz telecom power
supply incorporating both full-bridge and current doubler
topologies.The converter is implemented with secondaryside peak current mode control and includes output
overload, input under-voltage, and output over-voltage and
under-voltage protection features. A footprint for a thermistor
is ready for users to implement thermal protection on the
primary side. An ultra high efficiency of 88% at 3.3V output
and 60A full load has been achieved.
This application note includes a step-by-step design
procedure for the converter, which allows for easier
component selection and customization of this reference
design for a broader base of applications. Users can use
equations, presented in the CONVERTER DESIGN section
to determine the turns ratio of the main transformer and the
switching frequency, to estimate power dissipation of
primary switches and synchronous rectifiers, and to
calculate I/O filters design parameters. By entering these
calculations in a worksheet, users can do numerical
iterations and choose appropriate components for their
applications in an easier manner. The open loop response of
the system can be roughly approximated using the simplified
model.
In addition, extensive experimental results give users a
better understanding of the operation of the converter, the
ISL6551, and the ISL6550.
43
Application Note 1002
TERM DEFINITIONS (Continued)
TERM DEFINITIONS
Cin
Input Capacitance
Io
Output Load Current
Co
Output Capacitance
Ion
Current at Turn-on
Coss
Output Capacitance of MOSFET
Cp
Primary Capacitance of Transformer
D
Ratio of On-Time Interval of Lower FET to One
Clock Period (1/Fclock), Duty Cycle
dI
Ripple Current thru Each Output Inductor
dIo
Overall Ripple Current thru Output Capacitors
Dmaxav
Maximum Available Duty Cycle
dVCo
Output Ripple Voltage due to Output Capacitance
dVESL
Ripple Voltage Contributed by ESL of Output
Capacitance
dVESR
Ripple Voltage Contributed by ESR of Output
Capacitors
dVincap
Allowable Input Ripple Voltage Contributed by the
Input Capacitors
dVtr
Output Transient at 25% Step Load
∆V CAP
Transient due to Output Capacitance
∆V ESL
Initial Transient Spike due to ESL
EC
Energy Stored in Primary Parasitic Capacitance
EL
Energy Stored in Commutating Inductance
ESR
Iorms
Ip
RMS Current thru Output Capacitors
Current thru Primary Winding
Ipriavgfr
Average Current thru Body Diode of Upper FET in
Freewheeling Period
Ipriavgres
Average Current thru Body Diode of Lower FET for
a Td turn-on delay longer than Required Resonant
Delay
Ipripeak
Peak Current thru Primary Winding /Power Switches
Iprirmsfr
RMS Current thru the Channel of Upper FET in
Freewheeling Period
Iprirmstr
RSM Current thru Primary Switches in Power
Transfer Period
Iprirms
Overall RMS Current thru Upper FET
Iprms
Overall RMS Current thru Primary Winding
IQ1
Current thru One Synchronous Leg, Q1
IQ2
Current thru Another Synchronous Leg, Q2
Is
Current thru Secondary Winding
Isrmstr
RMS Current thru Secondary Winding in Transfer
Period
Isrmsfr
RMS Current thru Secondary Winding in
Freewheeling Period
Overall ESR of Output Capacitors
Overall ESR of Input Capacitors
Isrms
Overall RMS Current thru Secondary Winding
ESL
Overall ESL of Output Capacitors
Istep
Transient Load Step
fc
System Closed-Loop Bandwidth
Isyndeadavg
ESRin
Average Current thru Body Diode of Synchronous
FETs/External Schottky in SYNC DRIVE Scheme in
Dead Time
Fclock
Internal Clock Frequency
FDIST
Current Distribution Factor thru Synchronous FETs
Isynpeak
Peak Current thru Synchronous FET
Fsw
Switching Frequency
Isynrms
Overall RMS Current thru Synchronous FETs
He
Transfer Function of Error Amplifier
Hd
Transfer Function of Differential Amplifier
Hopen
Open Loop Transfer Function for Simplified Model
Hopen2
Open Loop Transfer Function with Subharmonic
and Ramp Components Added
Hs
Idr
High-frequency Correction Term for Subharmonic
Phenomenon
Isynrmstr
RMS Current thru Synchronous FETs in Power
Transfer Period
Isynrmsfr
RMS Current thru Synchronous FETs in Clamped
Freewheeling Period
Lext
Lk
Lmag
External Commutating Inductance
Leakage Inductance
Magnetizing Inductance
Driver Current
Lo
Inductance of Each Output Inductor
Iindpeak
Peak Current thru Each Output Inductor
N
Main Transformer Turns Ratio (Np/Ns)
Iindrms
RMS Current thru Each Output Inductor
Ncs
Current Sense Transformer Turns Ratio
Iinrms
RMS Current thru Input Capacitors
Nmax
Maximum Allowable Turns Ratio of Main
Transformer
ILO
Overall Ripple Current thru Output Inductors
ILO1
Ripple Current thru Inductor Lo1
ILO2
Ripple Current thru Inductor Lo2
Imag
Magnetizing Current
44
Pdr
Plowfet
Ppriswon
Driver Switching Losses
Power Dissipation of Lower FET
Switching Losses of Primary Switches at Turn-on
Application Note 1002
TERM DEFINITIONS (Continued)
Po
Psynfet
Psynfetfr
Output Power
Power Dissipation of Synchronous FET
Losses of Syn FET in Freewheeling Period
Pupfet
Power Dissipation of Upper FET
Qg
Gate Charge of MOSFET at VGS
Rcs
Current Sense Resistor
Rdsonpri
Ro
Rdsonsyn
Output Load Impendence
Rds(on) of Synchronous FETs
External Slope Added to Sn
Sn
Positive Slope of One Output Inductor Current
tDEAD
ton
tRESDLY
Vcc
Vdsyn
Vin
[3] Vatché Vorpérian, “Simplified Analysis of PWM
Converters Using the Model of the PWM Switch Part I:
Continuous Conduction Mode.” IEEE Transactions on
Aerospace and Electronics Systems Vol 26, No. 3 May 1990
p. 490-496.
Rds(on) of Primary Switches
Se
T
[2] Laszlo Balogh, “The Current doubler Rectifiers: An
Alternative Rectification Technique For Push-Pull and Bridge
Converters,” Design Note-63, Unitrode Integrated Circuit
Corporation.
Clock Period
Clock Dead Time
Primary MOSFET Switching Time at Turn On
Resonant Delay
Bias Voltage of Drivers
Body Diode Drop of Synchronous FETs
[4] “Designers’s Series - Part V Current-Mode Control
Modeling.” Switching Power Magazine. July 2001, Volume 2,
Issue 3.
[5] “PCB Design Guidelines For Reduced EMI.” Texas
Instrument: SZZA009, November 1999.
[6] Rais Miftakhutdinov. “An Analytical Comparison of
Alternative Control Technique for Powering Next Generation
Microprocessors.” TI-Unitrode Power Supply Design
Seminar, 2001 Series.
[7] Vatché Vorpérian. Analytical Methods in Power
Electronics (Lecture Note). CA: California Institute of
Technology.
Input Voltage
Appendix
Vinmax
Maximum Input Line
1. Block diagram of the converter in the evaluation board.
Vinmin
Minimum Input Line
Vinripple
Input Ripple Voltage
Vo
Vmisc
Vomax
Von
Voripple
3. Evaluation board layout (12 pages).
Output Voltage
Miscellaneous Voltage Drops Including Contact
Resistance, Winding Resistance, PCB Copper
Resistance
Maximum Output Voltage
Primary MOSFET VDS at Turn-on
Output Ripple Voltage
Vp
Voltage across Primary Winding
Vs
Voltage across Secondary Winding
Vsynfet
2. Evaluation board schematics (6 pages).
Voltage Drop of Synchronous FET due to Its
Rds(on) at Half of the Load
Vsynmax
Maximum Voltage across VDS of Syn FET
Zo
Impedance of Output Capacitors and Load
Acknowledgement
The author acknowledges the support of DT Magnetics for
designing and providing magnetics samples.
References
[1] Laszlo Balogh, “Design Review: 100W, 400kHz, DC/DC
Converter With Current Doubler Synchronous Ratification
Achieve 92% Efficiency.” Unitrode Integrated Circuit
Corporation.
45
4. Bill of Materials of the evaluation board (2 pages).
5. Preliminary specifications of the converter.
46
Application Note 1002
5
4
3
2
1
Secondary Rectification
R5
D2
TP1
GND
1u
2
R4
R105
C1
DNP0603
Q1
4
GND
5
6
7
8
5
6
7
8
Q2
4
Q3
4
Q4
4
1
2
3
2
1
2
3
SYNP_IN
750
5
6
7
8
47
R3
VS+
SYNP_G
M1
Inverting Driver
1
8
VS
2 VS
7
OUT
3 IN
6
OUT
4 NC
5
LOWER1
R2 DNP603
D
Si4842DY
TP3
SYNC2
2.43k
5
6
7
8
D1
TP2
1.1V
1
2
3
R1 10
1.3V
1
2
3
Max.
2.4V
D
MIC4421BM
C2
D25
3
0
SAPGND
SARTN
1
C
3.3Vout
TP4
0
C64
5.6n, 50V
MMJT9410
C5-C8 can be used
smaller footprint caps.
PC1
7X, JMK550BJ107MM
Q5
L2
R46
DNP
C
0.8uH
SARTN
R9
DNP
L3
C75
C3
C5
C6
C7
C8
C4
R10
TP5
100uF
PC4
100uF
1u
100u
100u
100u
100u
100u
100
R11
0.8uH
D27
D29
DNP1210
C74
R12
C9
D28
0
C65
2
SARTN
C70
2.2N, 630V
R107
R108
5.6n, 50V
SBRTN
DNP
SA+12V
B
R15
D4
TP6
TP7
750
GND
C10
DNP0603
SYNC drivers can drive only up to 20p,
therefore C1 and C10 cannot use for
turnoff delay if SYNC signals are used.
GND
C11
MIC4421BM
SYNN_G
4
Q7
Q8
4
5
6
7
8
5
6
7
8
Q9
4
Q10
4
1
2
3
DNP0603
1
2
3
S YNN_IN
SYNC1
VS-
5
6
7
8
M2 Inverting Driver
1
8
VS
2 VS
7
OUT
3 IN
6
OUT
4 NC
5
1
2
3
2
R18
R17
TP8
R19
5
6
7
8
10
LOWER2
1
2
3
R16
B
SARTN
D3
2.43k
1u
R106
A
A
0
SAPGND
Title
SARTN
Telecom Power Supply Schematics, [email protected]
Size
A
Date:
5
4
3
Document Number
ISL6551EVAL1
Thursday, April 18, 2002
2
Rev
C
Sheet
1
of
1
6
Application Note 1002
Reverse
Voltage at D26
and D27, at
least 40V
D26
R28
BAS40-06LT1
0.1u, 100V, DNP
SYNOFF
5
4
2
1
Primary Full-Bridge Power Train
F1
LF 10A
+ -
TP9
C12
47u, 100V
R451010
L1
C13-C15 can be replaced with
smaller footprint ceramic caps.
105K100ST2824, ITW Paktron
SB+12V
D
C15
1u
Q13
TP10
36.5
8
7
6
5
LW1_G
1
HIP2100IB
R24
C62
R26
R102
4
C19
0.1u
0
D33 DNP
0
VS-
TP16
TP19
C69
1
3900pF 3900pF
TP18
R27
5.6
Q18
T4
TP21
T5
Q19
2N7002LT1
1
2
5
3
D13
10
R29
C20
6
LOWER2
DNP0603
1
2
TP20
3
3
3
XUP_4
LOWER1
C
LW2_S
SBRTN
C66 C67
4
UPPER2
R13
2
D11
5
3
6
1
0 R25
36.5
2
DNP0603
T3
Q17
Q16
LW1_S
TP17
B
12
11
R23 36.5
TP15
1
UP2_G
0
DNP0603
3
LO
V ss
LI
HI
1
TP14
C21
5.8V
5.4V
C22
0.1u
4
D15 D16 D17 D18
R30
D14
10
M4
0.1u
0
R31
1
2
3
4
VDD
HB
HO
HS
8
7
6
5
LO
V ss
LI
HI
D36
D38
D35
D37
ISENSE
B
SAICRTN
TP22
MBR0530T1
DNP0603
Q20
1
R14
2
MMSD914T1
TP24
HIP2100IB
TP25
TP23
36.5
DNP0603
C23
R33
LW2_G
3
XLO_4
0
C63
D19
SAPGND
UP2_S
A
A
Title
Telecom Power Supply Schematics, [email protected]
Size
A
Date:
5
4
3
Document Number
ISL6551EVAL1
Thursday, April 18, 2002
2
Rev
C
Sheet
2
of
1
6
Application Note 1002
D10
C18
0.1u
VDD
HB
HO
HS
D5
2
2
C68
1
2
3
4
0.1u
DNP0603
0
D6 D7 D8 D9
1
T2
R22
7
Q15
R101
UPPER1
TP13
3
DNP
SAVDDP
M3
3
C17
2
TP11
XUP_1
D32
C
VS+
TP12
1
BJ4
SBICRTN
SUD40N10-25
SBRTN
3
5.6
C16
100u, 16V
2
R20
BJ3
MBR0530T1
Q14
3
48
SBBIAS
C14
1u
2
1
C13
1u
6
0
D39
1
SBRTN
BJ2
7
BJ1
8
5
SB+48V
2
SB+48VF
D
3
Primary Full-Bridge Power Train
5
4
3
2
1
SAMSAM
(6550)
Circuits
(6550)
Circuits
SA+12V
R32
D
D
49
20k
R35
30
R8 49.9k
R34
3.3Vsense
Differential Amp. Output
10
C24
10n
50
VOPOUT
C25
0.1u
TP26
R131
JP1
C
1
3.3Vout
8
9
10
11
12
13
14
15
16
17
2
R37
10k
3
C27
10p
0.1u
C76
Tie these to
the last
output cap
R7
SAICRTN
R38
10k
UVDLY
VCC
VOPP OVUVSEN
PGOOD
VOPM
VOPOUT START
VREF5
PEN
VID0
GND
VID1
BDAC
OVUVTH VID2
DACHI
VID3
DACLO
VID4
7
6
5
4
3
2
1
20
19
18
R6 0
C
START
ENABLE
TP28
R69 100
SW1
10
9
8
7
6
0
1
SARTN
TP27
SAICRTN
SAICRTN
R36 10k
REMOTE_SENSE
D31
LED
1
2
3
4
5
C71
10n
SW2
R40
JP2
5-Bit SW
ISL6550CIR
2
SAICRTN
R42
3
B
C28
10p
C29
28.7k 26.7k
110k
BAV70LT1
D24
R100
2
1.2k
3
1
CSS
BDAC
R43
Output
Reference
DNP0603
SENSE_RTN
R39 10k
R41
10k
B
SAICRTN
C72
10n
R44
R68
3.65k
DNP
SAPGND
R45
10k
C30
10n
SAICRTN
C73
10n
R47
26.7k
A
A
Title
Telecom Power Supply Schematics, [email protected]
SAICRTN
Size
A
Date:
5
4
3
Document Number
ISL6551EVAL1
Thursday, April 18, 2002
2
Rev
C
Sheet
3
of
1
6
Application Note 1002
C26
0.1u
M5 SAICRTN
5
4
3
2
1
FBC (ISL655
(ISL6551)
Circuits
FBC
1) Circuits
V+
U1A
3 +
Protect ICs from
reverse biasing
D34
8
SA+12V
SABIAS
R48 49.9k
50
BJ6
R49
R50 46.4k
30
8
+
C33
1n
BGREF
R52
10
R53
R54
10
10
Note:
F_SW=235kHz
Tdead=171ns
Resonant_Delay=40ns
Ramp=5.05E+4V/S
LEB=255n
SoftStart=10ms
Vclamp=3.75V >Voutmax=3.63V
R59 7.5k
26
27
28
1
2
3
4
5
6
7
8
9
10
11
R60 49.9k
ISENSE
R64
399k
R63
120k
R132
C41
R66
DNP
1k
CSS
R65
C42
73.2
73.2
2.21k
M6
VSS
CT
RD
R_RESDLY
R_RA
ISENSE
PKILIM
BGREF
R_LEB
CS_COMP
CSS
EANI
EAI
EAO
R70
5.1K
2
R73
5.6
SAPGND
C39
25
24
23
22
21
20
19
18
17
16
15
14
13
12
UPPER1
Tie this to
Synchonous
Drivers RTN
UPPER2
0.1u
LOWER1
LOWER2
SYNC1
SYNC2
START
B
C44
1n
C45
TP32
SAICRTN
100p
C47
470p, NPO, 5%
Q21
D20 LED
R72 20k
C46
0.1u
3
1
100, DNP0603
VDD
VDDP1
VDDP2
PGND
UPPER1
UPPER2
LOWER1
LOWER2
SYNC1
SYNC2
ON/OFF
DCOK
LATSD
SHARE
ISL6551IR
MMBT3906LT1, DNP
BDAC
R57
5.6
R67 49.9k
C43
33n
0.1u
R71 1k
SAICRTN
R56
TP31
C40
220pF
C38
0.1u
TP29
R62
C35
0.1u
C
C36
0.1u
R58 15k
R61 1.24k
-
LM393D
0.1u
180p, NPO, 5% C37
TP30
R55
20k
SHARE BUS
C48
22n, NPO, 5%
SAICRTN
R76
BJ7
R74
A
VOPOUT
30.1k
R77
50
R75 1.5k
Telecom Power Supply Schematics, [email protected]
C49
DNP0603
Title
TP33
SAICRTN
TP34
Size
A
DNP0603
Date:
5
4
3
Document Number
ISL6551EVAL1
Thursday, April 18, 2002
2
Rev
C
Sheet
4
of
1
6
Application Note 1002
C34
10n
C80
7
OUT
6
V-
1.263V
U1B
4
SAVDDP
A
R51
20k
V+
5
B
LM393D
SARTN
3.3Vsense
C
1
D
-
4
MBR0530T1
OUT
C31
1n 2
C32
100u, 16V
V-
BJ5
D
5
4
3
2
1
Input
UV
andTherm
Thermal
Circuits
Input
UV
and
al Circuits
D
D
45.3k, DNP
R79
45.3k, DNP
51
R78
45.3k, DNP
SB+48VF
R80
R81
MMBT5551LT1, 160V, B=80, DNP
200k
R83
Q22
at least
1.3mA
SB+12V
0
R82
C131 10n
12VREF
U2A
3
+
C
C51
1n
-
C53
TL431AID
20k
1
OUT
2
R88
R85 499k
LM393D
R87
Vsat=0.7
@4mA
D21
ENABLE
20k
R89
100k
M8
D22
10n
1
SBICRTN
R90
24.9k
B
Anode NC
Cathode Base
NC Collector
NC Emitter
IL217AT
34.3V
Q23
1
8
7
6
5
C77
10n
33.3V
2N7002LT1
B
R91 100k
RTH1
0
+
6
-
SAICRTN
8
C55
1n
7
V-
OUT
C56
0.1u
4
R103
SBRTN
5
V+
U2B
100k, DNP0603
C54
10n
A
1
2
3
4
BAV70LT1
3
3
C50
0.1u
V-
DNP0603
C52
Cathode REF
Anode Anode
Anode Anode
NC
NC
2.5VREF
2
R86
16.2k
8
7
6
5
2
M7
C
1
2
3
4
SA+12V
1k
8
R84
V+
60.4k
1n
LM393D
Tie this resistor
in front of the
input capacitor
11/1/2001
SBICRTN
A
Title
Telecom Power Supply Schematics, [email protected]
Size
A
Date:
5
4
3
Document Number
ISL6551EVAL1
Thursday, April 18, 2002
2
Rev
C
Sheet
5
of
1
6
Application Note 1002
C78
4
at least
0.7mA
5
4
3
2
1
TurnTurn
Off Synchronous
FETs
at
Off Synchronous
FETs
Start-up
and and
Power-down
Mode
at Start-up
Power-down
Mode
D
D
SA+12V
52
R95
R92
4.99k
1.263V
30
R94
D30
R93
2.67k
R133
2.67k
3.01k
R96
20K
3
R97
200k
1
ISENSE
SAICRTN
D23
-
C
C59
0.1u
LM393D
2
BAS40-06LT1
50
SYNOFF
0
V-
2
R104
1
4
3
R98
U3A
OUT
C58
DNP
C
+
SAICRTN
R99
1M
C61
220p
C60
100p
5
B
V+
8
SAICRTN
+
U3B
-
4
6
LM393D
SAICRTN
START
2
R134
B
7
V-
OUT
D131
3
BAS40-06LT1
1M
1
ENABLE
C132
A
A
2.2n
SAICRTN
Title
Telecom Power Supply Schematics, [email protected]
Size
A
Date:
5
4
3
Document Number
ISL6551EVAL1
Thursday, April 18, 2002
2
Rev
C
Sheet
6
of
1
6
Application Note 1002
C57
DNP
V+
8
BGREF
Application Note 1002
53
53
Application Note 1002
54
54
Application Note 1002
55
55
Application Note 1002
56
56
Application Note 1002
57
57
Application Note 1002
58
58
Application Note 1002
59
59
Application Note 1002
60
60
Application Note 1002
61
61
Application Note 1002
62
62
Application Note 1002
63
63
Application Note 1002
64
64
Application Note 1002
BILL OF MATERIALS (1/2)
Item
Quantity Reference
1
2
3
4
5
6
7
1
2
1
1
1
1
11
8
9
10
11
12
13
14
3
7
1
1
3
2
17
15
10
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2
6
1
1
3
1
2
1
1
1
1
2
2
1
1
16
32
14
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
2
2
3
2
1
2
2
1
2
2
2
1
1
1
1
2
8
1
4
5
1
1
1
BJ1
BJ4,BJ2
BJ3
BJ5
BJ6
BJ7
C1,C10,C20,C23,C29,C49,
C52,C62,C63,C68,C69
C2,C3,C11
C4,C5,C6,C7,C8,C74,C75
C9
C12
C13,C14,C15
C32,C16
C17,C18,C19,C21,C22,C25,
C26,C35,C36,C38,C39,C42,
C50,C56,C59,C76,C80
C24,C30,C34,C53,C54,C71,
C72,C73,C77,C131
C27,C28
C31,C33,C44,C51,C55,C78
C37
C40
C41,C57,C58
C43
C60,C45
C46
C47
C48
C61
C64,C65
C67,C66
C70
C132
D1,D2,D3,D4,D5,D10,D11,
D13,D14,D19,D22,D26,D27,
D28,D29,D30
D6,D7,D8,D9,D15,D16,D17,
D18,D34,D35,D36,D37,D38,
D39
D20,D31
D21,D24
D23,D25,D131
D32,D33
F1
JP1,JP2
Jumpers
L1
L2,L3
M2,M1
M3,M4
M5
M6
M7
M8
PC1, PC4
Q1,Q2,Q3,Q4,Q7,Q8,Q9,Q10
Q5
Q13,Q14,Q16,Q17
Q15,Q18,Q19,Q20,Q23
Q21
Q22
RTH1
56
57
58
59
60
3
1
2
3
2
R1,R16,R34
R2
R3,R18
R4,R15,R107
R19,R5
65
Part
Footprint
Vendor
Vendor Part Number
Red binding post
White binding post
Yellow binding post
Green binding post
Black binding post
Blue binding post
DNP0603
BINDING/POST
BINDING/POST
BINDING/POST
BINDING/POST
BINDING/POST
BINDING/POST
SM/C_0603
Johnson Components
Johnson Components
Johnson Components
Johnson Components
Johnson Components
Johnson Components
Various
111-0702-001
111-0701-001
111-0707-001
111-0704-001
111-0703-001
111-0710-001
DNP
1u, X7R, 25V
100u, 6.3V
0.1u, 100V
47u, 100V
1u, 100V
100u, 16V
0.1u, X7R, 25V
SM/C_0805
SM/L_2220
SM/C_0805
CPCYL1/D.400/LS.200/.034
SM/ST2824
CYL/D.200/LS.079/.034
SM/C_0603
Various
Taiyo Yuden
DNP
Panasonic
ITW Paktron
Panasonic
Various
Various
JMK550BJ107MM
DNP
ECA-2AHG470
105K100S2824
ECA-1CHG101
Various
10n, X7R, 25V
SM/C_0603
Various
Various
10p, X7R, 25V
1n, X7R, 25V
180p, NPO, 5%, 25V
220p, X7R, 25V
DNP0603
33n, X7R, 25V
100p, X7R, 25V
0.1u, X7R
470p, NPO, 5%, 25V
22n, X7R, 25V
220p, X7R, 25V
5.6n, X7R, 50V
3900pF, X7R, 25V
2.2N, X7R, 630V, 1206
2.2n, X7R, 25V
MMSD914T1
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0805
SM/C_0603
SM/C_0805
SM/C_0603
SM/C_0805
SM/C_0603
SM/L_2220
SM/C_0603
SOD123
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
TDK
Various
On Semiconductor
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
5.6n, X7R, 50V
Various
C3216X7R2J222M
Various
MMSD914T1
MBR0530T1
SOD123
On Semiconductor
MBR0530T1
LED
BAV70LT1
BAS40-06LT1
DNP
R451010
3-Pin Connector
Jumpers for JP1 &JP2
0
0.8uH
MIC4421BM
HIP2100IB
ISL6550CIR
ISL6551IR
TL431AID
IL217AT
KPA8CTP
Si4842DY
MMJT9410
SUD40N10-25
2N7002LT1
MMBT3906LT1
MMBT5551LT1
100k, DNP0603
DL-35
SM/SOT23_123
SM/SOT23_123
SOD123
SM/C_1812
TP\3P
160-1173-2-ND
BAV70LT1
BAS40-06LT1
MMSD914T1
R451010
S1012-03-ND
Jumpers for JP1 &JP2
Various
015138 Rev B
MIC4421BM
HIP2100IB
ISL6550CIR
ICL6551IR
TL431AID
IL217AT
KPA8CTP
Si4842DY
MMJT9410
SUD40N10-25
2N7002LT1
DNP
DNP
WSTL06104R
10
DNP603
750
2
2.43k
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0805
SM/R_0805
Digi-Key
On Semiconductor
On Semiconductor
On Semiconductor
LittleFuse
Digi-Key
Various
Various
DT Magnetics
Micrel Semiconductor
Intersil
Intersil
Intersil
Texas Instrument
Infineon
Burndy
Vishay Siliconix
On Semiconductor
Vishay Siliconix
On Semiconductor
On Semiconductor
On Semiconductor
Western Electronic
Components Corp.
Various
Various
Various
Various
Various
SM/R_2512
IND/DTPC1000-0002
SOG.050/8/WG.244/L.200
SOG.050/8/WG.244/L.200
MLFP.65M/20/5X5
MLFP.65M/28/6X6
SOG.050/8/WG.244/L.200
SOG.050/8/WG.244/L.200
BINDING/POST_2_REV2
SOG.050/8/WG.244/L.200
SM/SOT223_BCEC
TO252AA-DPAK
SM/SOT23_123
SM/SOT23_123
SM/SOT23_123
SM/R_0603
1%
DNP
1%
1%
1%
Application Note 1002
BILL OF MATERIALS (2/2)
Item
Quantity Reference
61
8
62
63
64
65
66
67
68
69
70
71
4
1
1
1
2
4
1
4
5
7
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
3
6
1
2
1
1
2
1
1
1
1
1
1
2
3
1
1
1
1
1
1
3
3
2
7
97
98
99
100
101
102
103
104
105
106
107
108
109
110
1
1
1
2
1
1
2
1
2
1
1
1
1
34
111
112
113
114
115
1
2
1
3
1
R6,R7,R12,R13,R14,R25,
R28,R30
R8,R48,R60,R67
R9
R10
R11
R77,R17
R20,R27,R56,R57
R22
R23,R24,R26,R33
R29,R31,R52,R53,R54
R32,R51,R55,R72,R87,R88,
R96
R35,R49,R95
R36,R37,R38,R39,R41,R45
R40
R42,R47
R43
R44
R108,R46
R50
R58
R59
R61
R62
R63
R65,R64
R66,R71,R82
R68
R69
R70
R73
R74
R75
R76,R98,R131
R78,R79,R80
R97,R81
R83,R101,R102,R103,R104,
R105,R106
R84
R85
R86
R89,R91
R90
R92
R133,R93
R94
R99,R134
R100
R132
SW1
SW2
TP1,TP2,TP3,TP4,TP5,TP6,
TP7,TP8,TP9,TP10,TP11,
TP12,TP13,TP14,TP15,TP16,
TP17,TP18,TP19,TP20,TP21,
TP22,TP23,TP24,TP25,TP26,
TP27,TP28,TP29,TP30,TP31,
TP32,TP33,TP34
T2
T5,T3
T4
U1,U2,U3
PCB board
66
Part
Footprint
Vendor
Vendor Part Number
0
SM/R_0805
Various
1%
49.9k
DNP
100
DNP1210
DNP0603
5.6
0
36.5
10
20k
SM/R_0603
SM/R_1210
SM/R_1210
SM/R_1210
SM/R_0603
SM/R_0805
SM/R_2512
SM/R_0805
SM/R_0805
SM/R_0603
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
1%
1%
1%
DNP
DNP
1%
Various
1%
1%
1%
30
10k
28.7k
26.7k
110k
DNP0603
DNP0805
46.4k
15k
7.5k
1.24k
399k
120k
73.2
1k
3.65k
100
5.1K
100
30.1k
1.5k
50
45.3k
200k
0
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0805
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0805
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0805
SM/R_0603
SM/R_0603
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
1%
1%
1%
1%
1%
DNP
DNP
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
DNP
1%
1%
1%
DNP
1%
1%
60.4k
499k
16.2k
100k
24.9k
4.99k
2.67k
3.01k
1M
1.2k
2.21k
5-Bit DAC Switch
ON/OFF Switch
Test Point
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0805
SM/R_0805
SM/R_0603
SM/R_0603
SM/R_0603
SM/R_0603
DIPSW.100/10/W.300/L.550
SWITCH_DPST
TP
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
CTS
C&K Components
Keystone
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
208-5
GT11MSCKE
5002
DT Magnetics
DT Magnetics
DT Magnetics
On Semiconductor
Various
010107 Rev C
UGDT125100
010109 Rev A
LM393D
10 layers, 4 oz Copper
Main Transformer
IND/DTPC1000-0001
Pulse Transformer
DT_X_330X260_REV11
Current Sense Transformer DT_XC_640X400_REV3
LM393D
SOG.050/8/WG.244/L.200
10 layers, 4 oz Copper, Buried Vias
Application Note 1002
CONVERTER PRELIMINARY SPECIFICATIONS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
67
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