CY8C20180 CapSense Express™ - 8 Configurable IOs Features Overview ■ The CapSense Express™ controller allows the control of eight IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up the device from sleep based on an interrupt input. 8 configurable IOs supporting ❐ CapSense™ buttons ❐ LED drive ❐ Interrupt outputs ❐ WAKE on interrupt input ❐ Bi-directional sleep control pin ❐ User defined input or output ■ 2.4V to 2.9V, 3.10V to 3.6V, and 4.75V to 5.25V operating voltage ■ Industrial temperature range: –40°C to +85°C ■ I2C slave interface for configuration 2 ❐ I C data transfer rate up to 400 kbps ■ Reduce BOM cost ❐ Internal oscillator - no external oscillators or crystal ❐ Free development tool - no external tuning components ■ Low operating current ❐ Active current:1.5 mA ❐ Deep sleep current: 2.6 uA ■ Available in 16-pin COL and 16-pin SOIC packages The user has the ability to configure buttons, outputs, and parameters through specific commands sent to the I2C port. The IOs have the flexibility of mapping to capacitive buttons and as standard GPIO functions such as interrupt output or input, LED drive, and digital mapping of input to output using simple logical operations. This enables easy PCB trace routing and reduces the PCB size and stack up. CapSense Express products are designed for easy integration into complex products. Architecture The logic block diagram illustrates the internal architecture of CY8C20180. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense system. CY8C20180 supports a standard I2C serial communications interface that allows the host to configure the device and to read sensor information in real time through easy register access. The CapSense Express Core The CapSense Express core has a powerful configuration and control block. It encompasses SRAM for data storage, an interrupt controller, and sleep and watchdog timers. System resources provide additional capability, such as a configurable I2C slave communication interface and various system resets. The analog system contains the CapSense PSoC® block which supports capacitive sensing of up to eight inputs. Cypress Semiconductor Corporation Document Number: 001-17346 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 28, 2009 [+] Feedback CY8C20180 Logic Block Diagram External VCC 2.40V to 2.90V, 3.10V to 3.60V, 4.75V to 5.25V 8 Configurable IOs CapSense ExpressTM Core SYSTEM BUS 512B SRAM 2 KB Flash Sleep and Watchdog Configuration and Control Engine Interrupt Controller Clock Sources (Internal Main Oscillator) SYSTEM BUS CapSense Block Document Number: 001-17346 Rev. *F I2C Slave Voltage & Current Reference System Reset POR/LVD Page 2 of 16 [+] Feedback CY8C20180 Pinouts Figure 1. Pin Diagram - 16 Pin COL COL (TOP VIEW) Table 1. Pin Definitions - 16 Pin COL[1] Pin Number Name Description 1 GP0[0] Configurable as CapSense or GPIO 2 GP0[1] Configurable as CapSense or GPIO 3 I2C SCL I2C clock 4 I2C SDA I2C data 5 GP1[0] Configurable as CapSense or GPIO 6 GP1[1] Configurable as CapSense or GPIO 7 VSS 8 GP1[2] Configurable as CapSense or GPIO 9 GP1[3] Configurable as CapSense or GPIO 10 GP1[4] Configurable as CapSense or GPIO 11 XRES Active HIGH external reset with internal pull down 12 GP0[2] Configurable as CapSense or GPIO 13 VDD 14 GP0[3] 15 CSInt 16 GP0[4] Ground connection Supply voltage Configurable as CapSense or GPIO Integrating Input.The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10 nF to 100 nF Configurable as CapSense or GPIO Note 1. 8 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8 IOs are chosen, the remaining 2 IOs of the package get locked and is not available for any functionality. Document Number: 001-17346 Rev. *F Page 3 of 16 [+] Feedback CY8C20180 Figure 2. Pin Diagram - 16 Pin SOIC GP0[3] 1 16 VDD CSInt 2 15 GP0[2] GP0[4] 3 14 XRES GP0[0] 4 13 GP1[4] GP0[1] 5 12 GP1[3] I2CSCL 6 11 GP1[2] I2CSDA 7 10 VSS GP1[0] 8 9 SOIC (Top View) GP1[1] Table 2. Pin Definitions - 16 Pin SOIC[1] Pin Number Name 1 GP0[3] 2 CSInt 3 GP0[4] Configurable as CapSense or GPIO 4 GP0[0] Configurable as CapSense or GPIO 5 GP0[1] Configurable as CapSense or GPIO 6 I2C SCL I2C clock 7 I2C SDA I2C data 8 GP1[0] Configurable as CapSense or GPIO 9 GP1[1] Configurable as CapSense or GPIO 10 VSS 11 GP1[2] Configurable as CapSense or GPIO 12 GP1[3] Configurable as CapSense or GPIO 13 GP1[4] Configurable as CapSense or GPIO 14 XRES Active HIGH external reset with internal pull down 15 GP0[2] Configurable as CapSense or GPIO 16 VDD Document Number: 001-17346 Rev. *F Description Configurable as CapSense or GPIO Integrating Input.The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10 nF to 100 nF Ground connection Supply voltage Page 4 of 16 [+] Feedback CY8C20180 The CapSense Analog System I2C Interface The CapSense analog system contains the capacitive sensing hardware. which supports CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing and scanning without external components. Capacitive sensing is configurable on each pin. The two modes of operation for the I2C interface are: Additional System Resources The I2C address is programmable during configuration. It can be locked to prevent accidental change by setting a flag in a configuration register. System resources provide additional capability useful to complete systems. Additional resources are low voltage detection and power on reset (POR). ■ The I2C slave provides 50, 100, or 400 kHz communication over two wires. ■ Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels and the advanced POR circuit eliminates the need for a system supervisor. An internal 1.8V reference provides a stable internal reference so that capacitive sensing functionality is not affected by minor VDD changes. ■ Device register configuration and status read or write for controller. ■ Command execution. I2C Device Addressing I2C device address is contained in the upper seven bits of the first byte of a read or write transaction. The first byte of the transaction is used by the I2C master to address the slave. The LSB of the byte contains the R/W bit. If this bit is 0, the master performs write operation to the addressed slave. If this bit is 1, the master performs read operation from the addressed slave. The LSB(B0) is eliminated when fixing the device address. For example, if the slave address is 02h, then the required address is 0000010 (7 bit) excluding LSB. If write operation is performed, the LSB is 0 and the address is 00000100(04h). If read operation is performed, the LSB is 1 and the address is 00000101(05h). Table 3 provides examples of I2C addressing. Table 3. Examples of I2C Addressing Slave Address Defined B7 B6 B5 B4 B3 B2 B1 B0 Address to be sent (in Hex) by Master 0 0 0 0 0 0 0 0 0(W) 00 0 0 0 0 0 0 0 0 1(R) 01 1 0 0 0 0 0 0 1 0(W) 02 1 0 0 0 0 0 0 1 1(R) 03 10 0 0 0 1 0 1 0 0(W) 14 10 0 0 0 1 0 1 0 1(R) 15 75 1 0 0 1 0 1 1 0(W) 96 75 1 0 0 1 0 1 1 1(R) 97 127 1 1 1 1 1 1 1 0(W) FE 127 1 1 1 1 1 1 1 1(R) FF CapSense Express Software Tool CapSense Express Register Map An easy to use software tool integrated with PSoC Express is available for configuring and tuning CapSense Express devices. Refer to the application note “CapSense™ Express Software Tool - AN42137” for details of the software tool. CapSense Express supports user configurable registers through which the device functionality and parameters are configured. For details, refer to the CY8C201xx Register Reference Guide. Document Number: 001-17346 Rev. *F Page 5 of 16 [+] Feedback CY8C20180 Modes of Operation Deep Sleep Mode CapSense Express devices are configured to operate in any of the following three modes to meet different power consumption requirements: Deep sleep mode provides the lowest power consumption because there is no operation running. In this mode, the device is woken up only using an external GPIO interrupt. A sleep timer interrupt cannot wake up a device from deep sleep mode. This can be treated as a continuous sleep mode without periodic wakeups. Refer to the application note “CapSense Express Power and Sleep Considerations - AN44209” for details on different sleep modes. ■ Active Mode ■ Sleep Mode ■ Deep Sleep Mode Active Mode Bi-Directional Sleep Control Pin In the active mode, all the device blocks including the CapSense sub system are powered. Typical active current consumption of the device across the operating voltage range is 1.5 mA. The CY8C20180 requires a dedicated sleep control pin to allow reliable I2C communication in case any sleep mode is enabled. This is achieved by pulling the sleep control pin LOW to wake up the device and start I2C communication. The sleep control pin can be configured on any of the GPIO. If sleep control feature is enabled, the device has one less GPIO available for CapSense and GPIO functions. The sleep control pin can also be configured as interrupt output pin from CY8C20180 to the host to acknowledge finger press on any button. To enable bi-directional feature, user must use I2C-USB bridge program. Sleep Mode Sleep mode provides an intermediate power operation mode. It is enabled by configuring the corresponding device register. When enabled, the device enters sleep mode and wakes up after a specified sleep interval. It scans the capacitive sensors before going back to sleep again. The device can also wake up from sleep mode with a GPIO interrupt. The following sleep intervals are supported in CapSense Express. The sleep interval is configured through registers. ■ 1.95 ms (512 Hz) ■ 15.6 ms (64 Hz) ■ 125 ms (8 Hz) ■ 1s (1 Hz) Document Number: 001-17346 Rev. *F Page 6 of 16 [+] Feedback CY8C20180 Electrical Specifications Absolute Maximum Ratings Parameter Description Min Typ Max Unit Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C (0°C to 50°C). Extended duration storage temperatures above 65°C degrade reliability TSTG Storage temperature –55 25 +100 °C TA Ambient temperature with power applied –40 – +85 ºC VDD Supply voltage on VDD relative to VSS –0.5 – +6.0 V VIO DC input voltage VSS – 0.5 – VDD + 0.5 V VIOZ DC voltage applied to tri-state VSS – 0.5 – VDD + 0.5 V IMIO Maximum current into any GPIO pin –25 – +50 mA ESD Electro static discharge voltage 2000 – – V LU Latch up current – – 200 mA Min Typ Max Unit Human body model ESD Operating Temperature Parameter Description TA Ambient temperature –40 – +85 °C TJ Junction temperature –40 – +100 °C Notes DC Electrical Characteristics DC Chip Level Specifications Min Typ Max Unit VDD Parameter Supply voltage Description 2.40 – 5.25 V IDD Supply current – 1.5 2.5 mA Conditions are VDD = 3.10V, TA = 25°C ISB Deep sleep mode current with POR and LVD active. Mid temperature range – 2.6 4 µA VDD = 2.55V, 0°C < TA < 40°C ISB Deep sleep mode current with POR and LVD active – 2.8 5 µA VDD = 3.3V, –40°C < TA < 85°C ISB Deep sleep mode current with POR and LVD active – 5.2 6.4 µA VDD = 5.25V, –40°C < TA < 85°C Document Number: 001-17346 Rev. *F Notes Page 7 of 16 [+] Feedback CY8C20180 5 and 3.3V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C< TA<85°C, 3.10V to 3.6V and -40°C<TA<85°C respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for design guidance only. Parameter Description Min Typ Max Unit 4 5.6 8 kΩ Notes RPU Pull up resistor VOH1 High output voltage Port 0 pins VDD – 0.2 – – V IOH = 10 µA, VDD > 3.10V, maximum of 20 mA source current in all IOs. VOH2 High output voltage Port 0 pins VDD – 0.9 – – V IOH = 1 mA, VDD > 3.10V, maximum of 20 mA source current in all IOs. VOH3 High output voltage Port 1 pins VDD – 0.2 – – V IOH < 10 µA, VDD> 3.10V, maximum of 10 mA source current in all IOs. VOH High output voltage Port 1 pins VDD – 0.9 – – V IOH = 5 mA, VDD> 3.10V, maximum of 20 mA source current in all IOs. VOL Low output voltage – – 0.75 V IOL = 20 mA, VDD > 3.10V, maximum of 60 mA sink current on even port pins and 60 mA sink current on odd port pins VIL Input low voltage – – 0.75 V VDD = 3.10V to 3.6V. VIH Input high voltage 1.6 – – V VDD = 3.10V to 3.6V. VIL Input low voltage – – 0.8 V VDD = 4.75V to 5.25V. VIH Input high voltage 2.0 – – V VDD = 4.75V to 5.25V. VH Input hysteresis voltage – 140 – mV IL Input leakage – 1 – nA Gross tested to 1 µA. CIN Capacitive load on pins as input 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. Document Number: 001-17346 Rev. *F Page 8 of 16 [+] Feedback CY8C20180 2.7V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.90V and -40°C<. TA <85°C, respectively. Typical parameters apply to 2.7V at 25°C. These are for design guidance only. Parameter Description Min Typ Max Unit Notes RPU Pull up resistor 4 5.6 8 kΩ VOH1 High output voltage Port 0 pins VDD – 0.2 – – V IOH < 10 µA, maximum of 10 mA source current in all IOs. VOH2 High output voltage Port 0 pins VDD – 0.5 – – V IOH = 0.2 mA, maximum of 10 mA source current in all IOs. VOH3 High output voltage Port 1 pins VDD – 0.2 – – V IOH < 10 µA, maximum of 10 mA source current in all IOs. VOH4 High output voltage Port 1 pins VDD – 0.5 – – V IOH = 2 mA, maximum of 10 mA source current in all IOs. VOL Low output voltage – – 0.75 V IOL = 10 mA, maximum of 30 mA sink current on even port pins and 30 mA sink current on odd port pins. VOLP1 Low output voltage port 1 pins – – 0.4 V IOL=5 mA, maximum of 50 mA sink current on even port pins and 50 mA sink current on odd port pins 2.4<VDD <2.9V and 3.1<VDD <3.6V. VIL Input low voltage – – 0.75 V VDD = 2.4 to 2.90V and 3.10V to 3.6V. – – V VDD = 2.4 to 2.7V. V VDD = 2.7 to 2.90V and 3.10V to 3.6V. VIH1 Input high voltage 1.4 VIH2 Input high voltage 1.6 VH Input hysteresis voltage – 60 – mV IIL Input leakage – 1 – nA Gross tested to 1 µA. CIN Capacitive load on pins as input 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. Document Number: 001-17346 Rev. *F Page 9 of 16 [+] Feedback CY8C20180 2.7V DC Spec for I2C Line with 1.8V External Pull Up This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.9V and 3.10V to 3.60V, and -40°C<TA <85°C, respectively. Typical parameters apply to 2.7V at 25°C. The I2C lines drive mode must be set to open drain and pulled up to 1.8V externally. Parameter Description Min Typ Max Unit Notes VOLP1 Low output voltage port 1 pins – – 0.4 V IOL=5mA, maximum of 50 mA sink current on even port pins and 50 mA sink current on odd port pins. 2.4<VDD <2.9V and 3.1<VDD <3.6V. VIL Input low voltage – – 0.75 V VDD = 2.4 to 2.90V and 3.10V to 3.6V. VIH Input high voltage 1.4 – – V VDD = 2.4 to 2.7V. CIN Capacitive load on pins as input 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent. Temp = 25°C. Min Typ Max Unit Notes – – 2.36 2.60 2.40 2.65 V V VDD must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from watchdog. 2.39 2.75 3.98 2.45 2.92 4.05 2.51 2.99 4.12 V V V DC POR and LVD Specifications Parameter Description VPPOR0 VPPOR1 VDD Value for PPOR Trip VDD= 2.7V VDD= 3.3V,5V VLVD0 VLVD2 VLVD6 VDD Value for LVD Trip VDD= 2.7V VDD= 3.3V VDD= 5V Document Number: 001-17346 Rev. *F Page 10 of 16 [+] Feedback CY8C20180 DC Programming Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C<TA<85°C, 3.10V to 3.6V and -40°C<TA<85°C, or 2.4V to 2.90V and -40°C<TA<85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Flash Endurance and Retention specifications with the use of EEPROM user module are valid only within the range: 25°C±20°C during the Flash Write operation. Refer to the EEPROM user module data sheet instructions for EEPROM Flash Write requirements outside the 25°C±20°C temperature window. Use of this User Module for Flash Writes outside this range must occur at a known die temperature (±20°C) and requires the designer to configure the temperature as a variable rather than the default 25°C value hard coded into the API. All use of this UM API outside the range of 25°C±20°C is at the user’s own risk. This risk includes overwriting the Flash cell (when above the allowable temperature range) thereby reducing the data sheet specified endurance performance or underwriting the Flash cell (when below the allowable temperature range) thereby reducing the data sheet specified retention. Symbol Description VddIWRITE Supply Voltage for Flash Write Operations[2] IDDP Supply Current During Programming or Verify VILP Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total) FlashDR Flash Data Retention Min 2.7 – – Typ – 5 – Max – 25 0.8 Units V mA V 2.2 – – V – – 0.2 mA – – 1.5 mA – – V Vdd –1.0 50,000 1,800,0 00 10 – Vss + 0.75 Vdd – – – – – – – – Years Notes Driving internal pull down resistor. Driving internal pull down resistor. V Erase/write cycles per block. Erase/write cycles. CapSense Electrical Characteristics Max (V) Typical (V) Min (V) Conditions for Supply Voltage Result 3.6 3.3 3.10 <2.9V The device automatically reconfigures itself to work in 2.7V mode of operation. 3.10 2.7 2.45 <2.45V The scanning for CapSense parameters shuts down until the voltage returns to over 2.45V. <2.4V The device goes into reset. 3.6 3.3 3.10 >3.10V The device automatically reconfigures itself to work in 3.3V mode of operation. 5.25 5.0 4.75 <4.73V The scanning for CapSense parameters shuts down until the voltage returns to over 4.73V. 3.6 to 4.75V This range is not supported by CapSense Express. The device will work, but CapSense scanning is not enabled until the voltage goes above 4.73V. 2.9 to 3.1V This range is not supported by CapSense Express. Note 2. Commands involving Flash Writes (0x01, 0x02, 0x03) must be executed only within the same VCC voltage range detected at POR (power on, XRES, or command 0x06) and above 2.7V. For register details, refer to CY8C201xx Register Reference Guide. If the user powers up the device in the 2.4V–3.6V range, Flash writes must be performed only in the range 2.7V to 2.9V and 3.10V to 3.6V. If the user powers up the device in the 4.75V–5.25V range, Flash writes must be performed in that range only. Document Number: 001-17346 Rev. *F Page 11 of 16 [+] Feedback CY8C20180 AC Electrical Characteristics 5V and 3.3V AC General Purpose IO Specifications Parameter Description Min Max Unit Notes TRise0 Rise time, strong mode, Cload = 50 pF, Port 0 15 80 ns VDD = 3.10V to 3.6V and 4.75V to 5.25V, 10% - 90% TRise1 Rise time, strong mode, Cload = 50 pF, Port 1 10 50 ns VDD = 3.10V to 3.6V, 10% - 90% TFall Fall time, strong mode, Cload = 50 pF, all ports 10 50 ns VDD = 3.10V to 3.6V and 4.75V to 5.25V, 10% - 90% Min Max Unit 2.7V AC General Purpose IO Specifications Parameter Description Notes TRise0 Rise time, strong mode, Cload = 50 pF, Port 0 15 100 ns VDD = 2.4V to 2.90V, 10% - 90% TRise1 Rise time, strong mode, Cload = 50 pF, Port 1 10 70 ns VDD = 2.4V to 2.90V, 10% - 90% TFall Fall time, strong mode, Cload = 50 pF, all ports 10 70 ns VDD = 2.4V to 2.90V, 10% - 90% AC I2C Specifications Parameter FSCLI2C Description SCL clock frequency THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated Standard Mode Fast Mode Unit Min Max Min Max 0 100 0 400 KHz 4.0 – 0.6 – µs TLOWI2C LOW period of the SCL clock 4.7 – 1.3 – µs THIGHI2C HIGH period of the SCL clock 4.0 – 0.6 – µs TSUSTAI2C Setup time for a repeated START condition 4.7 – 0.6 – µs THDDATI2C Data hold time 0 – 0 – µs TSUDATI2C Data setup time 250 – 100 – ns TSUSTOI2C Setup time for STOP condition 4.0 – 0.6 – µs TBUFI2C BUS free time between a STOP and START condition 4.7 – 1.3 – µs TSPI2C Pulse width of spikes suppressed by the input filter – – 0 50 ns Document Number: 001-17346 Rev. *F Notes Fast mode not supported for VDD < 3.0V Page 12 of 16 [+] Feedback CY8C20180 ~ ~ ~ ~ Figure 3. Definition of Timing for Fast/Standard Mode on the I2C Bus tf ~ ~ tf tSUDATI2C tr tLOWI2C ~ ~ SDA tHDSTAI2C tSPI2C tBUFI2C tr S tHDSTAI2C tSUSTAI2C tHIGHI2C tHDDATI2C ~ ~ ~ ~ SCL tSUSTOI2C Sr P S Ordering Information Ordering Code Package Diagram Package Type Operating Temperature CY8C20180-LDX2I 001-09116 16 COL[5] Industrial CY8C20180-SX2I 51-85068 16 SOIC Industrial Thermal Impedances by Package Typical θJA[3] Package 16 COL[5] 46 °C 16 SOIC 79.96 °C Solder Reflow Peak Temperature Package 16 COL [5] 16 SOIC Minimum Peak Temperature[4] Maximum Peak Temperature 240 °C 260 °C 240 °C 260 °C . Notes 3. TJ = TA + Power x θJA. 4. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. 5. Earlier termed as QFN package. Document Number: 001-17346 Rev. *F Page 13 of 16 [+] Feedback CY8C20180 Package Diagrams Figure 4. 16L Chip On Lead 3 X 3 mm Package Outline (SAWN) - 001-09116 - (Pb-Free) 001-09116 *D Figure 5. 16-Pin (150-Mil) SOIC (51-85068) 51-85068-*B Document Number: 001-17346 Rev. *F Page 14 of 16 [+] Feedback CY8C20180 Document History Page Document Title: CY8C20180 CapSense Express™ - 8 Configurable IOs Document Number: 001-17346 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 1341766 TUP/FSU See ECN New Data Sheet *A 1494145 TUP/AESA See ECN Changed to FINAL Datasheet Removed table - 2.7V DC General Purpose IO Specifications - Open Drain with a pull up to 1.8V Updated Logic Block Diagram *B 1773608 TUP/AESA See ECN Removed table - 3V DC General Purpose IO Specifications Updated Logic Block Diagram Updated table - DC POR and LVD Specifications Updated table - DC Chip Level Specifications Updated table - 5V and 3.3V DC General Purpose IO Specifications Updated table - 2.7V DC General Purpose IO Specifications Updated table - AC GPIO Specifications and split it into two tables for 5V/3.3V and 2.7V Added section on CapSense ExpressTM Software tool Updated 16-QFN Package Diagram *C 2091026 DZU/MOHD /AESA See ECN Updated table-DC Chip Level Specifications Updated table-Pin Definitions 16 pin COL Updated table-Pin Definitions 16 pin SOIC Updated table-5V and 3.3V DC General Purpose IO Specifications Updated table - 2.7V DC General Purpose IO Specifications Changed definition for Timing for Fast/Standard Mode on the I2C Bus diagram *D 2404731 DZU/MOHD/ PYRS See ECN Updated Logic Block Diagram Added DC Programming Specifications Table Updated Features Added CapSense Electrical Characteristics Table *E 2544918 ZSK/AESA 09/06/2008 *F 2648811 DZU/PYRS 01/28/09 Document Number: 001-17346 Rev. *F Different sleep modes explained Bi-Directional Sleep Control Pin defined Table added on “2.7V DC Spec for I2C Line with 1.8V External Pull-Up Included section on I2C Device Addressing Updated CapSense Electrical Specifications table Deleted VOH5, VOH6, VOH7, and VOH8 parameters Page 15 of 16 [+] Feedback CY8C20180 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com Clocks & Buffers Wireless Memories clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power wireless.cypress.com Precision Analog memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors image.cypress.com psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-17346 Rev. *F Revised January 28, 2009 Page 16 of 16 CapSense Express™, PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback