AN1080: Using the ISL6414 Triple LDO Controller

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ISL6414 - Enhanced ISL6411
April 2004
AN1080.2
Author: Manisha Pandya
Introduction
Quick Start Evaluation
The ISL6414 integrates three ultra low noise, low dropout
linear regulators providing a highly integrated single-chip
solution for 802.11 wireless chipset architectures. It operates
from 3.0V to 3.8V input and provides preset output voltages LDO1 set at 1.8V, LDO2 and LDO3 set at 2.84V.
The evaluation board is shipped “ready to use” right from the
box. The board accepts a 3.3V input from a standard power
supply. The output can be exercised through the use of an
external load.
The device features power sequencing specifically for
wireless chipsets. The outputs are sequenced such that
LDO1, the 1.8V core regulator voltage, is always within
regulation before LDO2, the 2.84V output LDO, is
sequenced on. When powering down, power to the 2.84V
LDO2 is removed before the 1.8V LDO1 core regulator is
sequenced off.
Designed with an internal P-channel MOSFET pass
transistor, the ISL6414 operates with a low supply current.
An output fault detection circuit indicates loss of regulation
on any of the three outputs. Other features include a logic
controlled shutdown mode, short circuit and thermal
shutdown protection, and reverse battery protection.
The ISL6414 also includes a RESET function. Integration of
this function into the ISL6414 eliminates the additional
RESET IC and external support components required in
wireless chipset power supply applications. The IC asserts a
RESET signal whenever the VCC (IN) supply voltage drops
below a preset threshold, keeping it asserted for at least
100ms after VCC (IN) has risen above the reset threshold.
Two RESET outputs are provided; RESET is a push-pull
active-LOW output, while RESET is an active-HIGH output.
Applications
• PRISM® 3, PRISM GT™, and PRISM WWR Chipsets
1
• An adjustable 0V - 5V, 2A capable bench power supply
• An electronic load
• A Four channel oscilloscope with probes
• A Precision digital multimeter
Power and Load Connections
Input Voltage - Connect the positive lead of the adjustable
bench power supply to the 3.3V post (P3). Connect the
ground lead of the supply to GND post (P4).
Output Voltages - The ISL6414EVAL1 provides fixed output
voltages for use in Wireless Chipset applications. Internal
trimmed resistor networks inside the chip set the nominal
output voltages as below:
The outputs can be exercised through external load on
connectors. The maximum currents are VOUT1 - 500mA,
VOUT2 - 300mA and VOUT3 -200mA.
TABLE 1. ISL6414 EVALUATION BOARD
ISL6414IR
To test the functionality of the ISL6414, the following
equipment is recommended:
VOUT3 = 2.84V (P1)
ISL6414 Reference Design
ISL6414EVAL1
Recommended Test Equipment
VOUT2 = 2.84V (P7)
• Hand-Held Instruments
IC PART NUMBER
Each evaluation board kit is sent with 5 samples of
ISL6414IR.
VOUT1 = 1.8V (P5)
• WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
BOARD NAME
There are posts available on the board for introducing power
to the board and for drawing current from the regulated
outputs. Post connectors are also available to monitor power
good conditions FAULT (P11), RESET (P9) and RESET
(P10). Posts for Shutdown functions SHDN (P12) and
SHDN3 (P13) allows low power mode function testing.
PACKAGE
16-Ld QFN
Output Loading, Sourcing Current - To load the VOUT1
output connect the positive lead of the electronic load to the
VOUT1 (P5) post and the return terminal of the same load
channel to the GND (P6) post. Similarly connect the positive
terminal of the second load channel to the VOUT2 (P7) post
and the return terminal to the GND (P8) post to load the
output of LDO2. The LDO3 output can be loaded by
connecting the positive terminal of a third channel of the
electronic load to the VOUT3 (P1) post and the return
terminal to the GND (P2) post.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1080
ISL6414EVAL1 Evaluation board provides easy platform to
characterize performance of the IC.
Figures below show transient response and regulation for
LDO1, LDO2 and LDO3.
LOAD = 50mA
0
3
3
TIME (1ms/DIV)
LOAD = 50mA
0
OUTPUT VOLTAGE
DEVIATION (mV)
VOUT = 2.84V
20
FIGURE 2. LINE TRANSIENT RESPONSE (VOUT2)
VOUT = 1.8V
10
VIN = 3.3V
5
0
4
LOAD
CURRENT (mA)
INPUT
VOLTAGE (V)
OUTPUT
VOLTAGE (mV)
FIGURE 1. LINE TRANSIENT RESPONSE (VOUT1)
3
100
0
TIME (1ms/DIV)
TIME (2ms/DIV)
VOUT = 2.84V
10
VIN = 3.3V
5
LOAD
CURRENT (mA)
0
FIGURE 4. LOAD TRANSIENT RESPONSE (VOUT1)
OUTPUT VOLTAGE
DEVIATION (mV)
FIGURE 3. LINE TRANSIENT RESPONSE (VOUT3)
OUTPUT VOLTAGE
DEVIATION (mV)
LOAD = 50mA
0
TIME (1ms/DIV)
LOAD
CURRENT (mA)
VOUT = 2.84V
20
4
4
INPUT
VOLTAGE (V)
INPUT
VOLTAGE (V)
VOUT = 1.8V
20
OUTPUT
VOLTAGE (mV)
Output Performance
OUTPUT
VOLTAGE (mV)
Evaluation Board Performance
100
0
TIME (2ms/DIV)
FIGURE 5. LOAD TRANSIENT RESPONSE (VOUT2)
2
VOUT = 2.84V
10
VIN = 3.3V
5
0
100
0
TIME (2ms/DIV)
FIGURE 6. LOAD TRANSIENT RESPONSE (VOUT3)
Application Note 1080
Dropout Voltage
DROPOUT VOLTAGE (mV)
180
The ISL6414 features a typical 0.5Ω rDS(ON) P-channel
MOSFET pass transistors. This provides several advantages
over similar designs using PNP bipolar pass transistors. The
P-Channel MOSFET requires no base drive, which reduces
quiescent current considerably. PNP based regulators waste
considerable current in dropout when the pass transistor
saturates. They also use high base drive currents under
large loads. The ISL6414 does not suffer from these
problems and ultra low drop-out regulators to maintain 2.84V
supplies within regulation with worst case minimum line
input. Both LDO2 and LDO3 can supply full load with less
then 3.0V input. Figure below shows the dropout voltage vs
output load current for both LDO2 and LDO3.
160
140
120
100
80
60
40
20
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
FIGURE 9. LD02 DROPOUT VOLTAGE vs TEMPERATURE
0.140
0.120
100
90
80
0.080
DROPOUT (mV)
VD (V)
0.100
0.060
0.040
0.020
0.000
0.00
70
60
50
40
30
20
0.05
0.10
0.15
IO (A)
0.20
0.25
0.30
10
0
FIGURE 7. LD02 DROPOUT VOLTAGE
-40
-10
25
85
TEMPERATURE (°C)
FIGURE 10. LD03 DROPOUT VOLTAGE vs TEMPERATURE
0.100
Current Limit
0.090
The ISL6414 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limit for
LDO1 is 550mA, LDO2 is 330mA and LDO3 is 250mA.
Performance in over current event can be tested by applying
over load on respective LDO outputs. The FAULT output will
go low for over current condition on any of the three LDO.
The ISL6414 based DC-DC converter is fully protected from
short circuit to ground outputs due to the current limit and
thermal protection features.
0.080
VD (V)
0.070
0.060
0.050
0.040
0.030
0.020
0.010
0.000
0.00
0.05
0.10
0.15
IO (A)
FIGURE 8. LD03 DROPOUT VOLTAGE
3
0.30
Integrated RESET for MAC/ Baseband Processors
The ISL6414 includes a microprocessor supervisory circuit.
This circuit eliminates the extra RESET IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the VIN supply voltage decreases below a preset
threshold 2.63V, keeping it asserted for a programmable
time (set by external capacitor CT) after the VIN pin voltage
has risen above the RESET threshold.
The push pull output stage of the reset circuit provides both
an active-Low RESET (P10) and an active-HIGH RESET
(P9) output. This function is guaranteed to be in the correct
state for VIN down to 1V. In addition to issuing a reset to the
microprocessor during power-up, power down and brownout
conditions, this block is relatively immune to short duration,
negative-going VIN transients/glitches. Figure below shows
the relations between RESET timing capacitor and
programmable RESET delay.
VOLTAGE (V)
Application Note 1080
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6414. When the junction temperature (TJ) exceeds
+150°C, the thermal sensor sends a signal to the shutdown
logic, turning off the pass transistor and allowing the IC to
cool. The pass transistor turns on again after the IC’s
junction temperature cools 20°C, resulting in a pulsed output
during continuous thermal overload conditions. Thermal
overload protection protects the ISL6414 against fault
conditions. For continuous operation, do not exceed the
absolute maximum junction temperature rating of +150°C.
Shutdown
Driving the SHDN input (P12) LOW puts both LDO1 and
LDO2 into shutdown mode. Driving the SHDN3 (P13) input
LOW puts LDO3 in shutdown mode. Pulling the SHDN and
SHDN3 pins LOW simultaneously, puts the entire chip into
shutdown mode, and supply current drops to 5µA typical.
External pull up resistors are not required because both
SHDN and SHDN3 inputs have internal pull-up resistors, so
that in normal operation the outputs are always enabled.
During shutdown mode using the SHDN pin, the FAULT
output will remain HIGH (refer to Figure 11).
Fault-Detection Circuitry
The FAULT pin monitors LDO1 output regulation, as well as
fault conditions such as current limit and thermal shutdown.
The FAULT output goes LOW, if the LDO1 output is out of
regulation by ±5.5% (typ.). During shutdown mode using the
SHDN pin, the FAULT output will remain HIGH (refer to
Figure 11).
4
TIME (µs)
FIGURE 11. SHUTDOWN vs RESET and FAULT
Operating Region and Power Dissipation
The maximum power dissipation of ISL6414 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:
PT = P1 + P2 + P3, where
P1 = IOUT1 (VIN – VOUT1)
P2 = IOUT2 (VIN – VOUT2)
P3 = IOUT3 (VIN- VOUT3)
The maximum allowed power dissipation is:
PMAX = (TJMAX – TA)/θJA
Where TJMAX = 150°C, TA = ambient temperature, and θJA
is the thermal resistance from the junction to the surrounding
environment.
References
For Intersil documents available on the web, see
http://www.intersil.com/
[1] ISL6414 Data Sheet, Intersil Corporation, File No.
FN9128.
Application Note 1080
ISL6414EVAL1 Schematic
FAULT
R1
P11
P3
100K
C5
0.01µF
P12
RESET
CT
ISL6414
SHDN
SHDN3
P13
C7
0.033µF
P6
C9
DNP
P7
C6
0.033µF
P8
5
6
7
8
SHDN3
2
3
4
C2
4.7µF
12
OUT1
11
CC1
10
OUT2
9
CC2
OUT3
CC3
GND3
GND
SHDN
1
P5
14
VIN
13
VIN
16
15
P10
FAULT
RESET
P4
VOUT3
+2.84V
GND
+3.3V
GND
P9
RESET
RESET
+ C1
10µF
VIN
C3
4.7µF
P1
C4
4.7µF
P2
C11
DNP
C10
DNP
VOUT1
+1.8V
GND
VOUT2
+2.84V
GND
C8
0.033µF
ISL6414EVAL1 Bill of Materials
ITEM
1
REFERENCE
U1
QTY
PART NUMBER
PART TYPE
1
ISL6414IR
IC, Linear, Multi-Output
DESCRIPTION
Regulator, Low Drop Out
PACKAGE
VENDOR
16-Lead
QFN 4x4
Intersil
CAPACITORS
2
C1
1
1210ZC106MAT2A
Capacitor, Ceramic, X7R 10µF, 20%, 10V
SM_1210
AVX/Panasonic
3
C2, C3, C4
3
1210ZC475MAT2A
Capacitor, Ceramic, X7R 4.7µF, 20%, 10V
SM_1210
AVX/Panasonic
4
C9, C10, C11
(DNP)
3
Capacitor, Ceramic, X7R
SM_1210
AVX/Panasonic
5
C5
1
0603ZC103KAT2A
Capacitor, Ceramic, X7R 0.01µF, 10%, 10V
SM_0603
AVX/Panasonic
6
C6, C7, C8
3
0603ZC333JAT2A
Capacitor, Ceramic, X7R 0.033µF, 5%, 10V
SM_0603
AVX/Panasonic
Resistor, Film
100kΩ, 5%, 0.1W
SM_0603
Panasonic
Turrett Post
Terminal post, throughhole, 1/4 inch tall
PTH
Keystone
RESISTORS
7
R1
1
OTHERS
8
P1 - P13
13
1514-2
5
Application Note 1080
ISL6414EVAL1 Evaluation Board Layout
ISL6414EVAL1
FIGURE 12. ISL6414EVAL1 - TOP LAYER SILK SCREEN
FIGURE 13. ISL6414EVAL1 - TOP LAYER
6
Application Note 1080
ISL6414EVAL1 Evaluation Board Layout (Continued)
FIGURE 14. ISL6414EVAL1 - LAYER 2 (GROUND)
FIGURE 15. ISL6414EVAL1 - LAYER 3 (POWER)
7
Application Note 1080
ISL6414EVAL1 Evaluation Board Layout (Continued)
FIGURE 16. ISL6414EVAL1 - LAYER 4 (BOTTOM)
FIGURE 17. ISL6414EVAL1 - BOTTOM LAYER SILK SCREEN
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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8
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