AN1083: ISL6421 Single LNB Controller With I2C Interface For Advanced Satellite Set-Top

ISL6421, ISL6425 Single LNB Controllers with I2C
Interface for Advanced Satellite Set-Top Box Designs
®
Application Note
PRELIMINARY
Introduction
Communication Satellite Frequency Allocation
Communication satellites operate within two frequency
bands for TV/Broadband service broadcast signals, C Band
and Ku Band. The C Band overall frequency spectrum is
4.0GHz -8.0GHz, while the Ku Band overall frequency
spectrum is 11.7GHz -18.0GHz.
Within these bands each satellite will have specific uplink
and downlink frequency allocation. For example the North
American DBS system has categories assigned as follows,
Ku Band high power downlink is 12.2GHz-12.7GHz and
17.3GHz-17.8GHz as the uplink frequency, C Band downlink
frequency is 3.7GHz -4.2GHz and 5.925GHz -6.425GHz as
uplink frequency.
Also, to use the frequencies that are available for satellite
broadcast as efficiently as possible, and to accommodate an
additional number of channels within a given frequency
band, the transmission signal can be formatted to be either
vertical and horizontal, or circular right-hand and circular lefthand simultaneously per frequency.
What is a Low Noise Block (LNB)?
An LNB is a low noise block module, placed on the focus of
the dish antenna (parabola) that provides the following
functions:
• Down conversion of the incoming signal from GHz range
to the 910MHz-2150MHz (for Europe) range called “first
conversion signal.” This conversion allows the signal to be
carried by an inexpensive coaxial cable towards the
receiver.
• Signal amplification with good noise figure. The LNB
improves the first conversion signal level through the use
of a built-in low noise amplifier.
• Selection of Vertical or Horizontal polarization.
• Selects operating band by switching its internal oscillator
from Low band to High band when the LNB “receives” a
22kHz tone. Specifically, the local oscillator (LO)
frequency changes from 9.75GHz to 10.6GHz.
C Band - LO frequency 9.75GHz
Ku Band - LO frequency 10.6GHz
• Miscellaneous functions based on 22kHz tone PPM
encoding, as discussed later in this paper.
AN1083.1
(right-hand or left-hand). Consequently, the satellite can
broadcast both H and V or LH and RH polarized signals on
one frequency.
The “universal” LNB switches the polarization by looking at
the voltage that it receives from the receiver.
12V – Horizontal, 18V – Vertical
13V – Circular right-hand, 20V – Circular left-hand
Generally, only two (12V and 18V or 13V and 20V) will be
used with one type of antenna. Also, 1V can be added from
a receiver to any of above voltages to compensate for the
voltage drop in the coaxial cable, i.e., it could be 13V (12V),
14V (13V), 19V (18V) or 21V (20V) instead.
22kHz Tone and DiSEqC (Digital Satellite
Equipment Control) Encoding
In addition to selecting the polarization, the LNB needs to
select the operating band. This is done with the use of a
22kHz tone frequency. A 22kHz pulse-position modulated
signal of about 0.6V amplitude is superimposed on the
LNB’s DC power rail. Its coding scheme allows the remote
electronics to perform more complex functions like varying
the down conversion frequency to select one of multiple
LNB’s for dual-dish systems or physically rotating the
antenna assembly. Traditionally, when other encoding
functions do not require using 22kHz tone, simple presence
or absence of this tone selects the operating band by
changing the local oscillator frequency of the LNB.
The complex encoding of the 22kHz burst is done with a
more sophisticated communication bus protocol named the
DiSEqC standard (Digital Satellite Equipment Control). The
open DiSEqC standard developed by the European
Telecommunication Satellite Organization is a well accepted
worldwide standard for communication between satellite
receivers and satellite peripheral equipment.
The 22kHz oscillator has to be a tone generator with specific
rise and fall time. The wave shape will be a quasi-square
wave (sine with flat-top). The required frequency tolerance is
±2kHz over line and temperature variations. Burst coding of
this signal is accomplished by input from the microcontroller
at the DSQIN pin of the IC or by setting the ENT bit of the
system register through the I2C bus as detailed in the
ISL6421, ISL6425 datasheets.
22kHz WAVE SHAPE AND DETAILS (See Figures 1 and 2)
Polarization Selection
Polarization is a way to give a transmission signal specific
direction. It increases the beam concentration. The signal
transmitted by satellite can be polarized in one of four
different ways: Linear (horizontal or vertical) or Circular
1
May 6, 2005
Carrier frequency: 22kHz ±2kHz over line and temperature
Carrier amplitude: 650mVpp ±250mV
Modulation mark period: 500µs ±100µs
Modulation space period: 1ms ±200µs
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1083
Quick Start Evaluation
Methods of Modulation
‘0’ DATA BIT
1.0ms
‘1’ DATA BIT
0.5ms
0.5ms
1.0ms
FIGURE 1. DiSEqC MODULATION SCHEME
Out Of The Box
The ISL6421/ISL6425 evaluation board is shipped in a
“ready-to-test” state. The board requires an input voltage
ranging from 8V to 14V and a 3.3V/5V supply. The use of an
electronic load enables evaluation over a wide range of
operating conditions. The evaluation kit also includes 5
samples of the ISL6421ER/ISL6425ER, a PC to I2C bus
interface board (USB-I2CIO), PC to I2C bus software, a USB
cable, and a connector cable to connect the USB-I2CIO
board and the ISL6421EVAL1A/ISL6425EVAL2 board.
TABLE 1. ISL6421/ISL6425 EVALUATION BOARDS
‘0’ TONE BURST (SATELLITE A)
‘1’ DATA BURST (SATELLITE B)
BOARD NAME
IC
PACKAGE
ISL6421EVAL1A
ISL6421ER
32 Ld QFN
ISL6425EVAL2
ISL6425ER
32 Ld QFN
Required Test Equipment
12.5ms
FIGURE 2. TIMING DIAGRAM FOR TONE BURST
CONTROL SIGNAL
To fully test the ISL6421/ISL6425 functionality, the following
equipment is needed:
• 4 channel oscilloscope with probes
• 1 electronic load
ISL6421/ISL6425 - Provides a Complete
Power Solution for LNB Control
• 2 bench power supplies
The ISL6421/ISL6425 is a highly integrated solution for
supplying power and control signals from advanced satellite
set-top box (STB) modules to the low noise block (LNB) of
the antenna port. The devices are comprised of a currentmode boost PWM and a low-noise linear regulator along
with the circuitry required for I2C device interfacing and for
providing DiSEqC standard control signals to the LNB.
• I2C bus read/write capability
The regulator output voltage is available at the output
terminal (VOUT) to support operation of the antenna port in
advanced satellite STBs. The regulator output for the PWM
is set to 13V or 18V by a voltage select command (VSEL)
through the I2C bus. Additionally, to compensate for the
voltage drop in the coaxial cable, the selected voltage may
be increased by 1V with the line length compensation (LLC)
feature. An enable command sent on the I2C bus provides
standby mode control for the PWM and linear combination,
disabling the output to conserve power.
The current-mode boost converter provides the linear
regulator with input voltage that is set to the output voltage,
plus typically 1.2V dropout to insure minimum power
dissipation across the linear regulator. This maintains
constant voltage drop across the linear pass element while
permitting adequate voltage range for tone injection.
Please refer to the ISL6421 datasheet (FN9130), or ISL6425
datasheet (FN9176), for more information.
2
• Precision digital multimeters
Power and Load Connections
The ISL6421/ISL6425 evaluation board has three sets of
terminal posts used to supply the input voltages and to
monitor and load the outputs.
Jumper Settings ISL6421 - JP1, JP2, and JP3 will be
shorted with shunt jumpers pulling the ADDR, SEL18V, and
the DISQIN pins low.
Jumper Settings ISL6425 - JP1, JP2 short VIN supply to V1
and Q1. JP3 short to set ADDRs low.
Input Voltage - Adjust two power supplies to provide the
5V/3.3V and 12V input voltages of the evaluation board.
With the power supplies turned off, connect the positive lead
of the 12V supply to the VIN post (P1) and the ground lead
to the GND post (P2).
The second supply set for either 5V or 3.3V provides the
pull-up voltage for the I2C bus clock and data line. Connect
the positive lead of the second supply to the +5V/+3.3V post
(P7)/ISL6421 or (P5)/ISL6425 and the ground lead to the
SGND post (P8)/ISL6421 or (P6)/ISL6425.
Output Voltage Loading and Monitoring - To exercise
and monitor VOUT, connect the positive lead of one of the
electronic loads and the positive lead of a digital multimeter
to the VOUT post (P3) and the ground lead to the GND
post (P4).
AN1083.1
May 6, 2005
Application Note 1083
I2C Bus Communication Setup
To control and exercise the ISL6421/ISL6425 requires
communication through the I2C bus clock (SCL) and data
(SDA) pins. Refer to the ISL6421, ISL6425 datasheets for
more information about the I2C bus specification. You can
use existing I2C hardware/software, a word generator, or
use the PC to I2C hardware/software included in the
ISL6421/ISL6425 evaluation kit to produce the necessary
I2C waveforms.
USB-I2CIO Board Driver Installation - To use a PC to
control the I2C bus to communicate with the
ISL6421/ISL6425 you will have to install the drivers of the
USB-I2CIO board included in the kit. You will need a
Windows 98/XP/2000 machine with a standard USB port.
10. If you receive a ‘No USB Device Detected’ error:
• Make sure the drivers were installed correctly. If
Windows did not detect your USB device, try running
the Add/Remove Hardware Wizard in the control panel.
• Make sure the USB board is powered up (internally or
externally, not both).
11. If you receive the ‘Incorrect Return Value’ error:
• The ISL6421/ISL6425 evaluation board may not be
powered up. Check the power connections.
• Make sure SCL and SDA are connected correctly. The
5-pin connector to the USB-I2CIO board only fits one
way. Try reversing the 4-pin connector at J1 of the
ISL6421/ISL6425 evaluation board.
1. The evaluation kit comes with a CD containing the
software and drivers to control the I2C bus. Copy the
contents of the CD to some directory, e.g., C:\’some
directory’.
2. Applying power to the USB-I2CIO board: The USB-I2CIO
board has the option of being powered with 3.3V through
the USB bus of the PC or externally with 5V connected to
the +5 test point and GND test point. The I2C bus can
operate at 3.3V or 5V logic levels. If you use an external
5V supply then place a shunt jumper shorting pins 2 and
3 of JP3. If you are using an external 5V supply to power
the USB-I2CIO board, place a shunt jumper shorting pins
1 and 2 of JP3.
3. After the USB-I2CIO board is powered up, connect the
USB cable to the USB port of a PC.
4. Windows should detect the new USB device and the
‘Found New Hardware Wizard’ should begin. This will
help you install the drivers. Follow the directions on the
screen until it asks you where to search for the drivers. At
this point, you should select the ‘choose location’ option
and browse to the C:\’some directory’ created in step one
and select the drivers folder.
5. Follow the remaining directions and the driver should be
installed and the USB-I2CIO detected by your PC.
6. If this is successful, another ‘Found New Hardware
Wizard’ window will appear. Repeat steps 4 and 5. At this
point, the USB-I2CIO board should be ready to use.
7. To connect the USB-I2CIO board to the ISL6421/ISL6425
evaluation board, use the 5-pin to 4-pin connector cable.
Connect the 5-pin connector to J4 on the USB-I2CIO
board and the 4-pin connector to J1 on the
ISL6421/ISL6425 evaluation board.
8. Turn on the power supplies to power up the
ISL6421/ISL6425 evaluation board.
9. Run the ISL6421&25_I2C_reva.exe program copied to
C:\’some directory’. Figure 3 shows the PC to I2C
software application window. Click the ‘Open Device’
button.
3
FIGURE 3. PC TO I2C APPLICATION WINDOW
Using the PC to I2C Application
After opening the application window and clicking on the
‘Open Device’ button, the program will detect the USB-I2CIO
board and initialize the I2C system registers of the
ISL6421/ISL6425. To evaluate the ISL6421/ISL6425
functionality, toggle the system register bits as needed and
then click on the ‘Write I2C’ button to write to the system
registers. The lower portion of the application window shows
the current values of the system register bits. They are read
and updated continuously. The OLF1 and OTF flag in
system register 1 and 2 are read only bits and provide
diagnostic status of the ISL6421/ISL6425.
AN1083.1
May 6, 2005
Application Note 1083
Performance Characterization
Boost PWM Efficiency
Start-up
The Boost PWM architecture allows close to 90% efficiency
at full load as shown in Figure 6.
The ISL6421/ISL6425 features internal soft-start to reduce
the external number of components. Figure 4 shows a
typical soft-start waveform. Typical soft-start time is 4.6ms.
100
95
EFFICIENCY (%)
90
VOUT
5V/DIV
85
80
75
70
65
60
50
150
250
350
450
550
650
750
IOUT (mA)
FIGURE 6. BOOST PWM EFFICIENCY vs LOAD
FIGURE 4. SOFT START
Shutdown
The LNB output of the ISL6421/ISL6425 can be shut down
using the EN bit via I2C. Figure 5 shows a typical shutdown
waveform.
VO1
5V/DIV
DiSEqC Implementation
The ISL6421/ISL6425 has a built-in 22kHz tone generator
that can be controlled either by the I2C interface or by a
dedicated pin (DSQIN) that allows immediate DiSEqC data
encoding for the DiSEqC compliance. When the I2C tone
enable bit (ENT) is set to HIGH, a continuous 22kHz tone is
generated regardless of the status of the DSQIN pin. The
ENT pin must be LOW when DSQIN pin is being used for
DiSEqC encoding. Figure 7 shows the 22kHz tone waveform
with 450mA load.
200mV/DIV
100µs/DIV
FIGURE 5. SHUTDOWN USING I2C ENABLE
22kHz
TONE
tRISE = 8µs
tFALL = 7.4µs
20µs/DIV
FIGURE 7. 22kHz TONE OPERATION
4
AN1083.1
May 6, 2005
Application Note 1083
Overcurrent Hiccup Mode
Output Ripple
Figure 8 shows a typical overcurrent trip.
Figure 10 shows the typical output ripple waveforms. VOUT
is set to 13V and 450mA load.
IOUT
200mA/DIV
VOUT 20mV/DIV
VOUT
10V/DIV
50µs/DIV
FIGURE 8. OVERCURRENT TRIP
FIGURE 10. OUTPUT RIPPLE
When the DCL (dynamic current limiting) bit is set LOW, the
overcurrent protection circuit works dynamically in a hiccup
mode; as soon as an overload is detected, the output is
shutdown for a time tOFF, typically 900ms. The output is
resumed for a time tON = 20ms. At the end of tON, if the
overload condition is still detected, the protection circuit will
cycle again through tOFF and tON. Figure 9 shows the typical
waveforms for the overcurrent hiccup mode.
External Back-Bias Protection
Some applications may need to be able to protect the
ISL6421/ISL6425 from an inadvertent back-bias voltage
condition. For the case where a DC supply is connected to
the output of the ISL6421/ISL6425, a series connected diode
as shown in Figure 11 will protect the IC. The LLC bit can be
set high through the I2C bus to increase the output voltage
by 1V to compensate for the diode voltage drop.
D1
STPS2L40U
ISL6405
(LLC = HIGH)
LNB
VD
CLOAD
IOUT
200mA/DIV
X DEVICE
FIGURE 11. DC BACK-BIAS PROTECTION CIRCUIT
VOUT 10V/DIV
500ms/DIV
FIGURE 9. OVERCURRENT HICCUP MODE
The DiSEqC standard recommends a maximum bus load of
0.25µF. For the circuit in Figure 11 to provide proper 22kHz
tone operation, the bus would have to have a minimum
loading of 12mA.
If tone operation is required at zero load conditions, a
resistor can be placed from the cathode of the protection
diode to ground, scaled to provide the minimum 12mA. To
avoid the added dissipation of this method, a capacitor can
be placed in parallel with the back-bias protection diode as
shown in Figure 12. This capacitor should be scaled with the
capacitive load present on the DiSEqC bus line. For a load of
0.25µF, use a 10µF capacitor. Consider the maximum load
of 0.25µF and the highest output voltage of 19V and a 0.5V
drop across the Schottky diode. After the tone rise time,
Qd(rise)~0, Qload(rise) = 19V*0.25µF = 4750nC
5
AN1083.1
May 6, 2005
Application Note 1083
ISL6421/ISL6425
Component Selection Guidelines
D1
STPS2L40U
LNB
(LLC = HIGH)
TCAP Capacitor
CLOAD
CD
The ISL6421EVAL1A/ISL6425EVAL2 application schematics
show the configuration for a single LNB power supply.
X DEVICE
A capacitor connected to the TCAP pin sets the transition
time from 13V to 18V. A 1µF minimum capacitor is
recommended for smooth transition with reduced peak
currents. Figure 14 shows the transition time versus
capacitor value.
FIGURE 12. DC BACK-BIAS PROTECTION CIRCUIT FOR
ZERO LOAD CONDITION
Figure 13 shows the tone mode operation at the cathode of
the protection diode in a zero load condition and the
charging current between CD and CLOAD. Large current
transients may occur from a fast dV/dt created if a DC supply
were connected to the output of the ISL6421/ISL6425,
therefore, to use the circuit in Figure 13, the DC supply
would have to be limited to 1A maximum current during the
dV/dt voltage transient to fully protect the IC.
ICLOAD 20mA/DIV
3.3
RISE/FALL TIME (ms)
During the tone fall time, the capacitors are essentially in
series so the charge will try to equally distribute between CD
and CLOAD. CLOAD will discharge allowing current to flow to
CD to match the falling voltage at the anode of the diode.
You will have to choose a capacitor, CD, that is large enough
to absorb the CLOAD discharging current and to minimize
the voltage drop created during the minimum tone fall time
specification, 5µs. A good choice would be to use a
capacitor for CD that is 40 times the value of CLOAD.
3.8
2.8
2.3
1.8
1.3
0.8
0.3
0.15
0.65
1.15
TCAP (µF)
1.65
2.15
FIGURE 14. TCAP CAPACITOR VALUE vs OUTPUT
TRANSITION TIME
The programmable output voltage rise and fall times can be
set by an external capacitor. The output rise and fall times
will be approximately 3400 times the TCAP value. For the
recommended range of 0.47µF to 2.2µF, the rise and fall
time would be 1.6ms to 7.6ms. Use of a 0.47µF capacitor
insures the PWM will stay below its overcurrent threshold
when charging a 120µF VSW filter cap during the worst case
13V to 19V transition. This feature only affects the turn-on
and programmed voltage rise and fall times. Figure 15
shows the 13V to 18V transition with TCAP = 1µF.
VOUT 2V/DIV
VO1 200mV/DIV
FIGURE 13. ZERO LOAD 22kHz TONE AT CATHODE OF
DIODE AND DRIVING CURRENT CHARGING AND
DISCHARGING CLOAD
5ms/DIV
FIGURE 15. 13V TO 18V TRANSITION
6
AN1083.1
May 6, 2005
Application Note 1083
Inductor
The ISL6421/ISL6425 operates with a 33µH standard
inductor over the entire range of supply voltages and load
currents. Choose an inductor that can handle at least the
peak switch current without saturating, and ensure that the
inductor has a low DCR (series resistance) to maximize
efficiency. The inductor saturation current must be greater
then the switch peak current,
V SW ( max ) ⋅ I OUT V IN ( min ) 
V IN ( min ) 
I PEAK = ---------------------------------------------
- + -----------------------  1 – --------------------------2L ⋅ f SW 
V SW ( max )
n ⋅ V IN ( min )
(EQ. 1)
L = Inductance, 33µH
VENDOR
SERIES
PACKAGE
Sanyo
OS-CON Electrolytic SMD/Through hole
Panasonic
EEUPC Electrolytic
TH
Nichicon
PL Electrolytic
TH
Sense Resistor
V SENSE
R SC < ----------------------I PEAK
fSW = PWM switching frequency, 220kHz Typical
n = Efficiency, 92% at maximum load
TABLE 2. RECOMMENDED INDUCTORS
PART NUMBER
TABLE 3.
The current sense resistor provides current loop feedback
and sets the overcurrent limit for static current mode. This
resistor value is calculated based on peak switch current per
Equation 2,
where,
VENDOR
ESR numbers, and for this reason, to improve efficiency and
output ripple, select a capacitor with higher voltage ratings.
ISAT
(A)
DCR
(mΩ)
PACKAGE
Coilcraft
MSS-1260-333MX
2.2
75
SMD
Falco
SD1016
2.8
66
SMD
(EQ. 2)
where Vsense is 200mV typical (see datasheet specification
table) and IPEAK is calculated from Equation 1. Make sure
the RSC value is always lower than the VSENSE/IPEAK ratio.
For the typical application conditions (VCC = 12V, IOUT
(max) = 450mA) a 100mΩ RSC value is a good choice.
If VIN < 10.5V the inductor peak current can be close to 2A,
then, it is necessary to decrease the RSC value.
Output Capacitors
The most important parameter for the output capacitors is
effective series resistance (ESR). The output ripple is
directly proportional to output capacitor ESR value.
A 68µF or less aluminum electrolytic output filter capacitor
with ESR lower than 80mΩ in parallel with a 470nF ceramic
capacitor is a good choice in most application conditions.
The ceramic capacitor is necessary to reduce the high
frequency switching noise.
A high output capacitance and low ESR will strongly reduce
the output ripple voltage and output switching noise and will
improve efficiency. Use the lowest possible ESR capacitor
for best performance.
The maximum value output capacitor is restricted by
transition time specifications between 13V to 18V. With a
high output capacitor the boost circuit will need higher peak
current from input supply to make transition from 13V to 18V
in a given transition time as set by TCAP value. Figure 14
shows the TCAP capacitor value versus transition time. Use
high TCAP capacitor value for high output capacitors to
allow sufficient time to charge the output capacitors in
maximum load conditions.
The capacitor’s voltage rating should be at least 35V, but
higher voltage electrolytic capacitors generally have lower
See Table 4 for some suggested SMD resistor part numbers.
TABLE 4.
VENDOR
SERIES
Meggitt
RL73
SEI Electronics
RMC1
Panasonic
ERJ
Layout Guidelines
Just like all switching power supplies, a proper PC board
layout is very important for a single channel
ISL6421/ISL6425 based power supply implementation.
Protect sensitive analog grounds by using a star ground
configuration. Also, minimize lead lengths to reduce stray
capacitance, trace resistance, and radiated noise. Minimize
ground noise by connecting PGND, the input bypass
capacitor ground lead, and the output filter capacitor ground
lead to a single point. Place bypass capacitors as close as
possible to the BYP pin and PGND and the DC/DC output
capacitor as close as possible to VSW.
Place the TCAP capacitor very close to the IC pins and use
the shortest possible ground return path.
Thermal Design
During normal operation, the ISL6421/ISL6425 dissipates
some power. The power dissipation of the output linear
regulator dominates the total power dissipated in the
7
AN1083.1
May 6, 2005
Application Note 1083
ISL6421/ISL6425. At the maximum rated output current, the
voltage drop on the linear regulator leads to a total
dissipated power that is about 1.2V*750mA = 0.9W. At
350mA maximum current, this power will be 1.2V*350mA =
0.42W. The heat needs to be removed with a heatsink to
keep the junction temperature below the over-temperature
threshold.
The simplest solution is to use a large, continuous copper
area of the ground layer to dissipate the heat. This area can
be the inner ground of multi-layered pcbs, or in a dual layer
pcb, an unbroken ground area on the opposite side of the
board where the IC is placed. In both cases, the thermal path
between the IC ground pins and the dissipating copper area
must exhibit a low thermal resistance.
Conclusion
The ISL6421/ISL6425 voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. The ISL6421EVAL1A/ISL6425EVAL2
is a complete reference design for providing power and
control functions to the LNB in advanced satellite set-top box
applications.
References
Intersil documents are available on the web at
http://www.intersil.com.
[1] ISL6421 Datasheet, Intersil Corporation, File No.
FN9031
[2] ISL6425 Datasheet, Intersil Corporation, File No.
FN9176
[3] DiSEqC Bus Functional Specification, EUTELSAT
http://www.eutelsat.com/docs/diseqc
[4] More information on the USB-I2CIO PC to I2C interface
board available at http://www.DeVaSys.com
8
AN1083.1
May 6, 2005
ISL6421EVAL1A Schematic
P2
L1
33µH
5.11
1500pF
L2
100nH
C14
1µF
8
7
6
5
D1
C13
1µF
C12
10µF
C11
10µF
C10
56µF
+
C5
1
2
3
4
C6
0.10
R4
C16
68K
1500pF
8
9
7
11
10
12
19
18
R3
100
C18
0.1µF
C8
4.7µF
GATE
CS
PGND
COMP
FB
VSW
VOUT
DSQIN
33 EP
P3
D2
STPS2L40U
P4
GND
1µF
0.47µF
D
E
C17
33pF
1000pF
E
100pF
E
C7
0.047µF
SP1
D
U1
ISL6421IR
NC
NC
PGND
NC
NC
NC
NC
NC
E
31
30
1
5
2
23
22
21
E
D E
VL
R9
100K
R10
100K
R11
100K
E
E
P9
P5
+5V/+3.3V
GND
P7
C19
0.1µF
P8
SCL
GND
GND
SDA
J1
1
2
3
4
1x4
ADDR
VL
R5
10K
R6
10K
P6
R7
100
JP1
JP2
JP3
D
D
D
R8
D
SEL18V
100
P10
D
DISQ
GND
Application Note 1083
C15
E
VOUT1
Q1
FDS6612A
R2
STPS2L40U
C4
E
17
27
29
26
25
24
5
32
C9
56µF
TCAP
VCC
NC
CPVOUT
CPSWIN
CPSWOUT
BYP
NC
9
R1
+ C1
C2
10µF
C3
0.047µF
E
SCL
SDA
ADDR
SGND
NC
AGND
SEL18V
28
NC
GND
P1
16
14
15
3
13
20
4
VIN
AN1083.1
May 6, 2005
Application Note 1083
ISL6421EVAL1A Bill of Materials
ITEM
REFERENCE
QTY
PART NUMBER
PART TYPE
DESCRIPTION
PACKAGE
1
U1
1
ISL6421IR
IC, Linear
Current mode PWM
Controller
2
Q1
1
FDS6612A
MOSFET Single
N-channel, 30V, 0.022Ω, SOIC8
8.4A
Fairchild
3
D1, D2
2
STPS2L40U
Diode, Schottky, Low
Drop Power
Schottky, 30V, 2A
STMicroelectronics
4
L1
2
DS3316P-333
Inductor
33µH, 20%, 0.334Ω, 1.4A DO3316
CoilCraft
5
L2
2
DN1050CT-ND
Inductor
100nH, 10%, 1175mW
SM_1210
API/Digikey
56µF, 20%, 25V
Radial
SANYO
32 Ld QFN
(5x5)
DO-214AA
VENDOR
Intersil
CAPACITORS
6
C1, C10
2
25SP56M
Capacitor, Aluminum
7
C2, C11, C12
3
TMK325BJ106M
Capacitor, Ceramic, X5R 10µF, 20%, 25V
SM_1210
Taiyo-Yuden/Generic
8
C3, C4
2
06033C473KAT2A
Capacitor, Ceramic, X7R 0.047µF, 10%, 25V
SM_0603
AVX/Generic
9
C5, C13, C14
3
12063C105KAT2A
Capacitor, Ceramic, X7R 1µF, 10%, 25V
SM_1206
AVX/Generic
10
C6
1
1210YC474KAT2A
Capacitor, Ceramic, X7R 0.47µF, 10%, 16V
SM_1210
AVX/Generic
11
C7
1
0603YC102KAT2A
Capacitor, Ceramic, X7R 1000pF, 10%, 16V
SM_0603
AVX/Generic
12
C8
1
1210YC475MAT2A
Capacitor, Ceramic, X7R 4.7µF, 20%, 16V
SM_1210
AVX/Generic
13
C9
1
08055C152KAT2A
Capacitor, Ceramic, X7R 1500pF, 10%, 50V
SM_0805
AVX/Generic
14
C15
1
06035A101KAT2A
Capacitor, Ceramic, NPO 100pF, 10%, 50V
SM_0603
AVX/Generic
15
C16
1
0603YC152KAT2A
Capacitor, Ceramic, X7R 1500pF, 10%, 16V
SM_0603
AVX/Generic
16
C17
1
ECJ-1VC1H330J
Capacitor, Ceramic, NPO 33pF, 5%, 50V
SM_0603
Panasonic/Generic
17
C18, C19
2
08053C104KAT2A
Capacitor, Ceramic, X7R 0.1µF, 10%, 25V
SM_0805
AVX/Generic
RESISTORS
18
R1
1
9C08052A5R11FKHFT Resistor, Film
5.11Ω, 1%, 0.1W
SM_0805
Yageo
America/Generic
19
R2
1
ERJ-L1WKF10CU
Resistor, Power metal
strip
0.1Ω, 1%, 1W
SM_2512
Panasonic/Generic
20
R3, R7, R8
3
ERJ-6ENF1000
Resistor, Film
100Ω, 1%, 0.1W
SM_0603
Panasonic/Generic
21
R4
1
Resistor, Film
68kΩ, 1%, 0.1W
SM_0603
Panasonic/Generic
22
R5, R6
2
Resistor, Film
10kΩ, 5%, 0.1W
SM_0603
Panasonic/Generic
23
R9, R10, R11
3
Resistor, Film
100kΩ, 5%, 0.1W
SM_0603
Panasonic/Generic
1x4 @ 0.1"
Molex
OTHERS
24
J1
1
22-03-2041
Connector
Header Strip, 1x4
25
JP1, JP2, JP3
3
68000-236-1x2
Header
1x2 Break Strip GOLD
26
JP1, JP2, JP3
3
S9001-ND
Jumper
2 pin jumper
Digikey
27
SP1
1
129 0701 202
Terminal, Scope Probe
Terminal, Scope Probe
Johnson
28
P1 - P10
10
1514-2
Turrett Post
Terminal post,through
hole,1/4 inch tall
29
4
PTH
Keystone
Bumpers
10
AN1083.1
May 6, 2005
Application Note 1083
ISL6421EVAL1A Layout
FIGURE 16. TOP SILKSCREEN
FIGURE 17. LAYER 1
11
AN1083.1
May 6, 2005
Application Note 1083
ISL6421EVAL1A Layout (Continued)
FIGURE 18. LAYER 2
FIGURE 19. LAYER 3
12
AN1083.1
May 6, 2005
Application Note 1083
ISL6421EVAL1A Layout (Continued)
FIGURE 20. LAYER 4
FIGURE 21. BOTTOM SILKSCREEN
13
AN1083.1
May 6, 2005
ISL6425EVAL2 Schematic
14
Application Note 1083
AN1083.1
May 6, 2005
Application Note 1083
Bill of Materials ISL6425EVAL2 REV.A
ITEM
REFERENCE
QTY
PART NUMBER
PART TYPE
DESCRIPTION
PACKAGE
VENDOR
1
U1
1
ISL6425ER
IC, Linear
Current mode PWM
Controller
32 Ld QFN
5x5
Intersil
2
Q1
1
FDS6612A
MOSFET Single
N-channel, 30V, 0.022Ω,
8.4A
SOIC8
Fairchild
3
D1, D3
2
STPS2L40U
Diode, Schottky, Low
Drop Power
Schottky, 30V, 2A
DO-214AA
STMicroelectronics
4
D2, D4
(DNP)
0
BZT52C5V6
Diode, Zener
Zener, 5.6V, 500mW
SOD123
Diodes Inc.
5
D5
1
S1A/B
Diode, Rectifying
Rectifying, 50V
SMB
Diodes Inc.
6
L1
1
MSS-1260-333MX
Inductor
33µH, 20%, 2.2A
MSS1260
CoilCraft
7
L2
1
1008PS-472K
Inductor
4.7µH, 10%, 1.0A
SM
CoilCraft
CAPACITORS
8
C1, C4
2
25SP56M
Capacitor, Aluminum
56µF, 20%, 25V
CASE-CC
SAYNO
9
C2, C5, C6, C8
8
C3225X7R1E106M
Capacitor, Ceramic, X7R 10µF, 20%, 25V
SM_1210
TDK/Generic
10
C3
(DNP)
1
DNP
SM_0603
TDK/Generic
11
C7, C13, C14
3
C2012X7R1E105K
Capacitor, Ceramic, X7R 1.0µF, 10%, 25V
SM_0805
TDK/Generic
12
C9
1
C1608X7R1H101K
Capacitor, Ceramic, X7R 100pF, 10%, 50V
SM_0603
TDK/Generic
13
C10
1
C1608COG1H330K Capacitor, Ceramic, COG 33pF, 10%, 50V
SM_0603
TDK/Generic
14
C11
1
C1608X7R1H152K
Capacitor, Ceramic, X7R 1500pF, 10%, 50V
SM_0603
TDK/Generic
15
C12, C15, C19
3
C1608X7R1H104K
Capacitor, Ceramic, X7R 0.1µF, 20%, 50V
SM_0603
TDK/Generic
16
C16
1
C1608X7R1H102K
Capacitor, Ceramic, X7R 1000pF, 10% , 50V
SM_0603
TDK/Generic
17
C17
1
C1608X7R1H473K
Capacitor, Ceramic, X7R 0.047µF, 10%, 50V
SM_0603
TDK/Generic
18
C18
1
C2012X7R1E224K
Capacitor, Ceramic, X7R 0.22µF, 10%, 25V
SM_0603
TDK/Generic
19
R1, R6, R13
(DNP)
0
DNP
Resistor, Film
SM_0603
Panasonic/Generic
20
R2
1
Resistor, Power metal
strip
0.1Ω, 1%, 1W
SM_2512
Panasonic/Generic
21
R3
1
Resistor, Film
68.1kΩ, 1%, 0.1W
SM_0603
Panasonic/Generic
22
R4
1
Resistor, Film
18.2Ω, 1%, 0.1W
SM_0603
Panasonic/Generic
23
R5, R10
2
Resistor, Film
100kΩ, 5%, 0.1W
SM_0603
Panasonic/Generic
24
R7, R8
2
Resistor, Film
1kΩ, 1%, 0.1W
SM_0603
Panasonic/Generic
25
R9
1
Resistor, Film
470Ω, 1%, 0.1W
SM_0603
Panasonic/Generic
26
R11, R12
2
Resistor, Film
10kΩ, 5%, 0.1W
SM_0603
Panasonic/Generic
28
J1
1
22-03-2041
Connector
Header Strip, 1X4
1X4@.1"
Molex
29
JP1, JP2, JP3
3
68000-236-1X2
Header
1X2 Break Strip GOLD
30
JP1, JP2, JP3
3
S9001-ND
Jumper
2 pin jumper
Digikey
31
SP1
1
131-4353-00
Terminal, Scope Probe
Terminal, Scope Probe
Tektronix
32
P1 - P9
9
160-2043-02-01-00
Turrett Post
Terminal post, through hole PTH
Cambion
RESISTORS
OTHERS
33
4
Bumpers
15
AN1083.1
May 6, 2005
Application Note 1083
ISL6425EVAL2 Layout
FIGURE 22. TOP SILKSCREEN
16
FIGURE 23. TOP LAYER COMPONENT SIDE
AN1083.1
May 6, 2005
Application Note 1083
ISL6425EVAL2 Layout (Continued)
FIGURE 24. LAYER 2
17
FIGURE 25. LAYER 3
AN1083.1
May 6, 2005
Application Note 1083
ISL6425EVAL2 Layout (Continued)
FIGURE 26. BOTTOM LAYER SOLDER SIDE
FIGURE 27. BOTTOM SILKSCREEN
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
AN1083.1
May 6, 2005