AN1173: DC/DC Module Trim with Digital Potentiometers

Application Note 1173
DC/DC Module Trim with Digital Potentiometers
Introduction
This Application Note describes the trimming technique for
DC/DC converter modules using industry standards for output
voltage trim. The DC/DC converter module design equations
are presented from the datasheets, a circuit model for the
DC/DC converter is shown, circuit equations for using a digital
pot (DCP) are derived and resistor values are shown for the two
most popular industry standards.
As of this writing, there are two standards for DC/DC converter
module that attempt to create standard pinouts, standard
package size, standard electrical specifications and standard
controls such as ON/OFF and output voltage setting.
The first standard was the Point of Load Alliance (POLA)
established by Texas Instruments, Artysen, Emerson Astec,
Ericsson and others. A typical POLA DC/DC converter module
is the Texas Instruments PTH12050, which features an
adjustable output voltage of 0.8V to 5.5V with a 6 amp output
current from a +12V input voltage. There are many other
variations of this DC/DC converter module for other input
voltages and load currents from any vendor that is part of the
POLA. Within their product families, all POLA modules are
interchangeable and, therefore, second sourced by any POLA
vendor. Appendix A on page 5 shows the typical voltage setting
technique and datasheet trim circuit.
It must be noted that POLA modules are not pin compatible
with DOSA modules. Also, DC/DC converter modules, which
are not part of POLA or DOSA may or may not be compatible
with DC/DC converter modules from other vendors.
Module trim with software control of a DC/DC converter
module output voltage is desirable for several reasons:
1. Margin testing is often required in the engineering
qualification test to four-corner test the system against
tolerance variations in the DC/DC converter output
voltages.
2. Margin testing is often performed as part of production
final system tests.
3. Margin testing can be done as part of a regular in-field
preventative maintenance test to attempt to predict a
system failure.
4. As the core voltage requirement of controllers, gate arrays,
etc. change with each new generation of devices it is
helpful to be able to perform software changes of output
voltage instead of requiring an ECO to change a resistor
value.
The second standard that is more recent is the Distributed
Power Open Standards Alliance (DOSA) founded by Tyco
Electronics and SynQor; recent members include Celestica,
Delta, Ericsson and Lambda. Their web site is
www.dosapower.com for additional information. A typical
DOSA DC/DC converter module is the Tyco Electronics Austin
Lynx II # ATA010A0X3-SR which features an adjustable output
voltage of 0.75V to 5.0V with a 10 amp output current from a
+12V input voltage. There are many other variations of this
DC/DC converter module for other input voltages and load
currents from any vendor that is part of the DOSA. Within their
product families, all DOSA modules are interchangeable and,
therefore, second sourced by any DOSA vendor. Appendix B on
page 5 shows the typical voltage setting technique and
datasheet trim circuit. Throughout this application note, the
Texas Instruments PTH12050 POLA module and TycoAustin
Lynx II # ATA010A0X3-SR DOSA module are shown in the
design examples. However, any module which complies with
the POLA or DOSA standard should be interchangeable.
April 22, 2015
AN1173.3
1
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Application Note 1173
POLA Modules DCP Circuit and
Table of Resistors Values
Figure 1 and Tables 1 and 2 show the circuit for interfacing POLA
modules to a DCP. For high output voltage (1.2V to 5.5V) POLA
modules (PTH12050W) the circuit and tables show the external
resistor values (RW, RY) for an ISL95810UIU8 256 tap, 50k DCP.
The ISL95810UIU8 DCP allows an adjustment range of nominal
VOUT ±10% by changing the DCP code from full scale value
(25510) to zero value (00010). The complete circuit analysis,
circuit model and design equations are shown in Appendix C on
page 6 and Appendix D on page 7.
For low output voltage (0.8 to 1.8V) POLA modules (PTH12050L)
Table 2 shows the external resistor values (RW, RY) for an
ISL95810UIU8 256 tap, 50k DCP.
TABLE 1. HIGH OUTPUT VOLTAGE RESISTOR VALUES FOR POLA
MODULE
NOMINAL
VOUT
(VDC)
MINIMUM
VOUT
(VDC)
MAXIMUM
VOUT
(VDC)
RSET
(kΩ)
RW
(kΩ)
RY
(Ω)
3.3
3.000
3.600
1.69
14.3
8.06k
2.5
2.250
2.750
3.83
26.1
2.49k
1.8
1.620
1.980
11
36.5
511
1.5
1.372
1.651
26.7
39.2
0
Minimum VOUT at Full Scale Code
Nominal VOUT at 1/2 Full Scale Code
Maximum VOUT at Zero Code
TABLE 2. LOW OUTPUT VOLTAGE RESISTOR VALUES FOR POLA
MODULE
NOMINAL
VOUT
(VDC)
MINIMUM
VOUT
(VDC)
MAXIMUM
VOUT
(VDC)
RSET
(kΩ)
RW
(kΩ)
RY
(Ω)
1.5
1.350
1.650
2.61
3.74
6.65k
1.2
1.080
1.320
11.5
21.5
422
1.0
0.900
1.100
44.2
32.4
0
PTH12050"x" MODULE
2
VOUT
±10% TRIM
TRACK
VIN
C1
100µF
3
C2
10µF
VIN
VO
6
INHIBIT GND ADJUST
4
1
C3
100µF
RY
5
RW
+5V
ISL95810UIU8
8
VCC
SCL
7 RH
SDA
2
5 RW
1
WP
3
I2C
INTERFACE
50k
RSET
6 RL
4
GND
"x" indicates W-suffix for 1.2V to 5.5V Module.
"x" indicates L-suffix for 0.8V to 1.8V Module.
FIGURE 1. CIRCUIT FOR POLA MODULE
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AN1173.3
April 22, 2015
Application Note 1173
DOSA Modules DCP Circuit and
Table of Resistors Values
TABLE 3. RESISTOR VALUES FOR DOSA MODULE
For DOSA modules (Tyco Austin Lynx II, # ATA010A0X3-SR)
Figure 2 and Table 3 show the external resistor values (RW, RY)
for an ISL95810UIU8 256 tap, 50k DCP. The ISL95810UIU8 DCP
allows an adjustment range of nominal VOUT ±10% by changing
the DCP code from full scale value (25510) to zero value (00010).
The complete circuit analysis, circuit model and design equations
are shown in Appendix C on page 6 and Appendix E on page 8.
NOMINAL
VOUT
(VDC)
MINIMUM
VOUT
(VDC)
MAXIMUM
VOUT
(VDC)
RTRIM
(kΩ)
RW
(kΩ)
RY
(Ω)
5.0
4.500
5.500
1.27
26.1
7.87k
3.3
3.000
3.600
2.87
47.5
4.32k
2.5
2.250
2.750
4.64
51.1
1.96k
1.8
1.620
1.980
8.66
59
309
1.5
1.372
1.651
12.7
68.1
0
1.2
1.080
1.320
23.7
66.5
0
Minimum VOUT at Full Scale Code
Nominal VOUT at 1/2 Full Scale Code
Maximum VOUT at Zero Code
TYCO AUSTIN LYNX II
ATA010A0X3-SR
3
SEQ
SENSE
VIN
2
CIN
4 x 47µF
VIN(+)
VO(+)
ON/OFF GND
TRIM
1
6
4
VOUT
±10% TRIM
7
+5V
5
COUT
100µF
RY
RW
RTRIM
ISL95810UIU8
8
VCC
SCL
7 RH
SDA
5 RW
WP
50k
2
3
1
I2C
INTERFACE
6 RL
4
GND
FIGURE 2. CIRCUIT FOR DOSA MODULE
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AN1173.3
April 22, 2015
Application Note 1173
Example of Vicor DC/DC
Converter Modules
For Vicor Generation 2 modules (#V48C5C100B for example)
Figure 3 and Table 4 show the external resistor values (RW, RY)
for an ISL95810UIU8 256 tap, 50k DCP. The ISL95810UIU8 DCP
allows an adjustment range of nominal VOUT ±10% by changing
the DCP code from full scale value (25510) to zero value (00010).
The complete circuit analysis, circuit model and design equations
are shown in Appendix F on page 8.
TABLE 4. RESISTOR VALUES FOR VICOR GENERATION 2 MODULE
NOMINAL
VOUT
(VDC)
MINIMUM
VOUT
(VDC)
MAXIMUM
VOUT
(VDC)
Rpot
End-End
(kΩ)
RW
(kΩ)
RY
(kΩ)
5.0
4.500
5.500
50
9.09
17.4
Discrete DC/DC Converter
Circuits Using Intersil Monolithic
2A Step-Down Regulator IC
The same technique for using a DCP to trim the output voltage of
a DC/DC converter module can also be applied to a discrete
DC/DC converter circuit as shown in Figure 4. The EL7532 circuit
is set for a nominal output voltage of 1.8V. The ISL95810UIU8
DCP allows an adjustment range of 1.62V to 2.00V (1.8V ±10%)
by changing the DCP code from full scale value (25510) to zero
value (00010). The circuit analysis for the output voltage vs code
is similar to the analysis for the POLA or DOSA module as
described in the Appendix C on page 6 and is available upon
request.
VOUT
±10% TRIM
VICOR #V48C5C100B
1
48RTN
2
+OUT
+IN
+5V
7
PC
CIN
3
COUT
PR
SC
4
-48V
-IN
-OUT
ISL95810UIU8
8
VCC
SCL
7 RH
SDA
WP
5 RW
50k
RY
RW
6
5
2
3
1
I2C
INTERFACE
6 RL
4
GND
FIGURE 3. CIRCUIT FOR VICOR GENERATION 2 MODULE
VIN (2.5 to 6V)
EL7532
4
10µF
7
100
5
0.1µF
8
6
VIN
EN
VDD
POR
RSI
VO
LX
FB
SGND
PGND
VO (1.8V AT 2A)
9
+5V
3
10
1.8µH
10µF
R1
124k
1
RY
5.11k
RW
2
R2
100k
475k
ISL95810UIU8
8
VCC
SCL
7 RH
SDA
WP
5 RW
50k
2
3
1
I2C
INTERFACE
6 RL
4
GND
FIGURE 4. CIRCUIT FOR DISCRETE DC/DC MODULE
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AN1173.3
April 22, 2015
Application Note 1173
Appendix A: Standard POLA
Output Voltage Settings and Trim
To set the output voltage of a POLA DC/DC converter module, an
external resistor, RSET, is added from the Adjust pin to the GND
pin as shown in Figure 5. With the TI #PTH12050 DC/DC
converter module there are two parts - one for high output
voltage (1.2V to 5.5V) indicated by a W suffix and a second for
low voltage (0.8V to 1.8V) indicated by an L suffix.
RSET = 10k/(Vo - VMIN) - Rs
Where Vo = Desired output voltage
VMIN = 1.2V for W-suffix part
Replacing the two resistors and FETs with a digital pot (DCP)
allows a large number of output voltages to be set under
software control. It will be shown in the next section that the
range of the output voltage can be set with two fixed resistors
connected to the DCP wiper and top terminal.
Appendix B: Standard DOSA
Output Voltage Settings and Trim
To set the output voltage of a DOSA DC/DC converter module, an
external resistor, RTRIM is added from the TRIM pin to the GND
pin as shown in Figure 7.
RTRIM = 10500 /(Vo - 0.7525) - 1000
= 0.8V for L-suffix parts
Where Vo = Desired output voltage
Rs = 1.82kΩ for W-suffix parts
= 7.87kΩ for L-suffix parts
VO+
SENSE+
VO+
TRIM
RLOAD
ADJUST
RTRIM
RLOAD
GND
RSET
FIGURE 7. DOSA OUTPUT VOLTAGE SET CIRCUIT
GND
FIGURE 5. POLA OUTPUT VOLTAGE SET CIRCUIT
Output voltage margining is implemented by adding external
resistors for margining up (RMARGIN-UP) and margining down
(RMARGIN-DOWN); the resistors are connected into the Trim pin
with external N-channel FETs Q1 and Q2. With this technique only
three output voltages can be set; nominal (both Q1 and Q2 off),
margin up output voltage (Q1 on) and margin down voltage
(Q2 on). No intermediate voltage steps are available.
Output voltage margining is implemented by adding external
resistors for margining up (RMARGIN-UP) and margining down
(RMARGIN-DOWN); the resistors are connected into the Trim pin
with external N-channel FETs Q1 and Q2. With this technique only
three output voltages can be set; nominal (both Q1 and Q2 off),
margin-up output voltage (Q1 on) and margin-down voltage
(Q2 on). No intermediate voltage steps are available.
SENSE+
VOUT
VO+
RMARGIN-DOWN
VOUT
VO+
RMARGIN-DOWN
Q1
Q1
TRIM
ADJUST
RTRIM
RMARGIN-UP
RSET
Q1
GND
Q1
GND
FIGURE 8. DOSA MARGIN CIRCUIT
FIGURE 6. POLA MARGIN CIRCUIT
Other POLA modules (PTH12060W) include Margin Up and
Margin Down pins for ±5% output voltage margining. However,
they require external FETs for controlling the Margin Up and
Margin Down pins.
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RMARGIN-UP
5
Replacing the two resistors and FETs with a DCP allows a large
number of output voltages to be set under software control. It will
be shown in the next section that the range of the output voltage
can be set with two fixed resistors connected to the DCP wiper
and top terminal.
AN1173.3
April 22, 2015
Application Note 1173
Appendix C: POLA and DOSA
DC/DC Converter Circuit Model
and Design Equations
For a DCP
RBOT = REE * Code/N
RTOP = REE - RBOT
To use a DCP for controlling the output voltage of a DC/DC
converter module it is necessary to obtain a circuit model of the
feedback circuit internal to the DC/DC converter module. Some
DC/DC converter module vendors show the circuit model on their
datasheets or application notes. If the circuit model is not
available, it is necessary to derive the model from the output
voltage vs adjust resistor equation.
Where REE = DCP end to end resistance
Code = Digital input code (0 to N)
N = Number of taps
Solving for Vo:
Vo = Vr * (X – R1/(B*D*Rs^2)) / (1 + E*R1/RS)
Where X = 1 + R1/Rs + R1/R2
The output voltage of a POLA or DOSA DC/DC converter module
can be adjusted for trimming and margining purposes by using
the circuit in Figure 9. Resistor RW sets the width of the
adjustment range and resistor RY is used to center the
adjustment range around its nominal output with the DCP set to
midscale. Because the DCP presents a “load” to the feedback
network, the resistance of both sides of the DCP must be
considered.
For analysis, the equivalent circuit with node assignments is used
(Figure 10).
Summing Currents at Each Node:
(Vo-Vr)/R1 + (V1-Vr)/RS + (0-Vr)/R2 = 0
(Node Vr)
(Vr–V1)/RS + (V2-V1)/RW + (0-V1) RADJ = 0
(Node V1)
(Vo-V2)/RT + (V1-V2)/RW + (0-V2)/Rb = 0
(Node V2)
B = 1/RS + 1/RW + 1/RADJ
C = 1/RT + 1/RW + 1/Rb
D = 1 – 1/(B*C*Rw^2)
E = 1/(B*C*D*Rw*RT)
RT = RTOP + RY
Since this is a very messy non-linear equation, an
Excel worksheet was prepared to calculate the DC/DC converter
module output voltage with a given DCP digital code.
In addition to the Excel worksheet, to calculate the output voltage
with a DCP code, RW and RY resistor values, the three node
equations were programmed into TK Solver (Universal Technical
Systems). TK Solver has the ability to back solve a set of
equations with any variable being set as an input or output
variable. The TK Solver rules sheet is available upon request.
A SPICE simulation could also be used to calculate the output
voltage with a DCP input code; however, SPICE does not provide
the ability to calculate resistor values. SPICE could only be used
to verify the circuit analysis and calculate the output voltage with
a DCP input code
VOUT
VOUT
±10% TRIM
Vo
RY
R1
10k
R1
ERROR AMPLIFIER
RS ADJ
RTOP (TOP HALF OF DCP)
RW
Vr
Rt
Rs
V1
Rw
V2
1820
VREF = 0.8V
R2
20k
RSET
GND
RB (BOTTOM HALF OF DCP)
NOTE: RT = RTOP + RY
FIGURE 9. POLA MODULE CIRCUIT MODEL WITH DCP
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R2
RADJ
RB
NOTE: RT = RTOP + RY
FIGURE 10. EQUIVALENT POLA
MODULE CIRCUIT WITH
NODE ASSIGNMENT
AN1173.3
April 22, 2015
Application Note 1173
Appendix D: POLA DC/DC
Converter Circuit Model
The POLA DC/DC converter module circuit model high output
voltage parts is shown in Figure 11.
For low output voltage (0.8V to 1.8V) POLA DC/DC converter
module, resistor R2 (20k) is removed and RS value is changed to
7.87k; the circuit model is shown in Figure 12.
VO
VOUT
VOUT = VREF * (1 + (R2 + RS + RSET)/(2 * (RS + RSET))
R1
ERROR AMPLIFIER
10k
RS
ADJUST
1820
R2
VREF = 0.8V
RSET
20k
GND
For VOUT between 1.2V and 5.5V with TI PTH12050W
FIGURE 11. HIGH OUTPUT VOLTAGE POLA MODULE CIRCUIT MODEL WITH DCP
VO
VOUT = VREF * (1 + R1/(RS + RSET))
R1
ERROR AMPLIFIER
VOUT
10k
RS
ADJUST
7.87k
RSET
VREF = 0.8V
GND
For Vout between 1.2V and 5.5V with TI PTH12050L
FIGURE 12. LOW OUTPUT VOLTAGE POLA MODULE CIRCUIT MODEL WITH DCP
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Application Note 1173
Appendix E: DOSA DC/DC
Converter Circuit Model
set to midscale. Because the DCP presents a “load” to the
feedback network, the resistance of both sides of the DCP
must be considered. For analysis, the equivalent circuit with
node assignments is used in Figure 14.
The circuit model for a DOSA DC/DC converter module is very
similar to the POLA modules as shown in Figure 13.
VO
ERROR AMPLIFIER
Summing Currents at V1 and V2 Node:
(VREF - V1)/R3 + (V2 - V1)/RW = 0
VOUT
Node V1
(V1 - V2)/Rw + (VOUT - V2)/(RY + RTOP) + (0 - V2)/Rbot = 0Node V2
The error amplifier will force V1 = Vx
R1
15k
RS
Resistors R1 and R2 are not shown on the datasheet or
application notes; however, it is easy to determine the ratio
R1/R2 based on circuit analysis when there is no trim applied.
ADJUST
1K
R2
200k
With no trim applied to the SC pin
RSET
Vnom = VREF * (1 + R1/R2) where Vnom is the output voltage with no
trim.
VREF = 0.7V
GND
R1/R2 = Vnom/VREF - 1
Summing Currents at Vx Node
FIGURE 13. DOSA MODULE CIRCUIT MODEL WITH DCP
(VOUT – Vx)/R1 + (0 – Vx)/R2 = 0
VOUT = Vx * (1 + R1/R2)
Appendix F: Vicor Generation 2
DC/DC Converter Circuit Model
and Design Equations
Plugging R1/R2 from the No Trim
Calculation
The output voltage of a Vicor Generation 2 DC/DC converter
module can be adjusted for trimming and margining purposes
by using the circuit shown in Figure 14. Resistor RW sets the
width of the adjustment range and resistor RY is used to center
the adjustment range around its nominal output with the DCP
To calculate the output voltage with a DCP code, RW and RY
resistor values, the two node equations, V1 = Vx and VOUT = Vx
* Vnom/VREF were programmed into TK Solver. The TK Solver
rules sheet is available upon request.
VOUT
VICOR GEN 2 MODULE
ERROR AMPLIFIER
VOUT = Vx * Vnom/VREF
VOUT
RY
R1
VX
SC
V1
R3
1k
VREF = 1.23V
RTOP (TOP HALF OF DCP)
RW
V2
R2
RB (BOTTOM HALF OF DCP)
GND
FIGURE 14. VICOR GENERATION 2 MODULE CIRCUIT MODEL WITH DCP
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
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