AN1256: Boost Converter Generates 5V at 375mA from Wide Range Negative Input Supply

Boost Converter Generates +5V at 375mA from
Wide Range Negative Input Supply
®
Application Note
May 8, 2006
AN1256.0
Author: Mike Wong
The Q1 and Q2 PNP transistor forms a translator that scales
the +5V output voltage referenced to ground to a feedback
voltage referenced to negative input. The transistor pair also
eliminates temperature change and voltage drop effects. As
the negative input voltage decreases, Q2 runs at a higher
current than Q1 causing additional transistor offset mismatch.
For optimal line regulation, one should set Q1 and Q2 to
operate at the same current as the nominal input voltage.
Figure 2 shows line regulation results. The maximum output to
input voltage difference must be within the boost converter
internal power FET drain to source breakdown voltage (Vds).
The EL7515 maximum Vds is 18V. For +5V output, the
minimum input voltage is -12V. 1V safety margin
compensates for the D1 diode drop and any voltage spikes on
the drain of the power FET. Figure 3 shows the load regulation
test results. The maximum output current is determined by the
input to output voltage ratio and the current limit setting of the
boost converter. As shown in Figure 4, this circuit yields over
80% efficiency at 200mA output.
Sometimes only a negative power source is available but a
positive voltage is desired. Using a standard boost converter
IC, a positive voltage can be generated from the negative
source. The boost converter is designed to generate an
output voltage higher than the input voltage. Since the
positive output voltage, 5V in this example, is higher than the
negative input voltage ground level, the boost converter
principle is not violated. Figure 1 shows the circuit
implementation using the EL7515, a standard boost
converter IC. The ground pins of the boost converter
connect to the negative input source; ground becomes the
“positive” input source. VOUT is determined by:
⎛ R 2⎞
37.5k
V OUT = – VFB × ⎜ -------⎟ = – 1.33V × ⎛ ---------------⎞ = – 5V
⎝ 10k ⎠
⎝ R 1⎠
L1
D1
VOUT (+5V)
10µH
C1
R4
1kΩ
10µF
1 PGND
LX 10
2 SGND
VDD 9
C4
R2
37.5k
0.1µF
Q1
R3
VIN- (-2V TO -12V)
C2
47µF
3 RT
FB 8
4 EN
SS 7
R1
10k
100k
LBO 6
5 LBI
Q2
R5
40k
C3
20nF
EL7515
FIGURE 1. CIRCUIT SCHEMATIC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
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Application Note 1256
5.1
4.98
5.08
IOUT = 180mA
5.04
4.97
5.02
VOUT (V)
VOUT (V)
VIN = -5V
4.975
5.06
5
4.98
4.965
4.96
4.96
4.94
4.955
4.92
4.9
-14
-12
-10
-8
-6
VIN (V)
-4
-2
4.95
0
0
EFFICIENCY (%)
FIGURE 2. LINE REGULATION
82
81
80
79
78
77
76
75
74
73
72
71
50
100
150
200
250
IOUT (mA)
300
350
400
FIGURE 3. LOAD REGULATION
-5V to +5V
0
50
100
150
200
250
IOUT (mA)
300
350
400
FIGURE 4. EFFICIENCY vs IOUT
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
2
AN1256.0
May 8, 2006
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