AN1298: Instrumentation Amplifier Application Note

Instrumentation Amplifier Application Note
®
Application Note
May 27, 2009
AN1298.2
Table of Contents
Introduction to the Instrumentation Amplifier................................................................................................................................... 2
Review of Standard Instrumentation Amplifier Design Techniques ................................................................................................ 2
Monolithic Instrumentation Amplifier Architecture ........................................................................................................................... 4
Introduction to Instrumentation Amplifier Product Family................................................................................................................ 4
Instrumentation Amplifier Specifications ......................................................................................................................................... 4
Instrumentation Amplifier Product Family Theory of Operation....................................................................................................... 6
Features of Instrumentation Amplifier Product Family .................................................................................................................... 7
Care and Feeding of Instrumentation Amplifiers ............................................................................................................................. 10
Application Circuits.......................................................................................................................................................................... 20
Pressure Sensor Interface Circuit ................................................................................................................................................... 21
Thermocouple Input with A/D Converter Output ............................................................................................................................. 22
Thermocouple Input with 4mA to 20mA Output Current ................................................................................................................. 23
RTD Input with A/D Converter Output ............................................................................................................................................. 24
Low Voltage High Side Current Sense............................................................................................................................................ 27
Multiplexed Low Voltage Current Sense ......................................................................................................................................... 30
Bi-Directional Current Sense........................................................................................................................................................... 32
1
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Application Note 1298
Introduction to the Instrumentation
Amplifier
An Instrumentation Amplifier is a confused animal –
confused by its cousin, the op amp.
This Application Note describes the Intersil bipolar and MOS
input (see Table 1). Instrumentation Amplifiers, theory of
operation, advantages, and typical application circuits.
These devices are micropower Instrumentation Amplifiers
which deliver rail-to-rail input amplification and rail-to-rail
output swing on a single 2.4V to 5V supply. These
Instrumentation Amplifiers deliver excellent DC and AC
specifications while consuming only 60µA typical supply
current. Because they provide an independent pair of
feedback terminals to set the gain and to adjust output level,
these Instrumentation Amplifiers achieve high
common-mode rejection ratios regardless of the tolerance of
the gain setting resistors. The ISL28271 and ISL28272 have
an ENABLE pin to reduce power consumption, typically less
than 5.0µA, while the Instrumentation Amplifier is disabled.
• Its symbol looks like an op amp (see Figure 1)
• It has many of the same basic properties and
specifications as an op amp Offset Voltage, Input Bias
Current, CMRR, PSRR, etc.
• You can make an Instrumentation Amplifier from a simple
op amp circuit.
But the behavior of an Instrumentation Amplifier is
profoundly different than an op amp! And it is very difficult to
make a precision Instrumentation Amplifier from a simple op
amp circuit – many have tried, but most have failed.
An Instrumentation Amplifier provides a voltage subtraction
block followed by a fixed gain block; i.e.
V OUT = ( IN+ – IN- ) × Gain
TABLE 1.
Often, there is an optional output reference input which
allows the output voltage to be shifted by a fixed voltage:
MINIMUM
CLOSED
BW
INPUT
# OF
STAGE AMPLIFIERS LOOP GAIN (kHz) ENABLE?
PART
EL8170
Bipolar
1
100
192
No
EL8171
PMOS
1
10
450
No
EL8172
PMOS
1
100
170
No
EL8173
Bipolar
1
10
396
No
ISL28270 Bipolar
2
100
240
No
ISL28271 PMOS
2
10
180
Yes
ISL28272 PMOS
2
100
100
Yes
ISL28273 Bipolar
2
10
230
No
ISL28470 Bipolar
2
100
240
No
VOUT
-
VOUT
GAIN
In contrast, an op amp by definition only provides extremely
high gain with provisions to apply negative feedback to
establish a fixed gain or unique transfer function, H(s), such
as an integrator or filter.
Review of Standard Instrumentation
Amplifier Design Techniques
Difference Amplifier
In its most basic topology, an Instrumentation Amplifier can
be configured from a single op amp and four resistors as
shown in Figure 4; this is often referred to as a Difference
Amplifier.
-VCC
-VCC
+
IN-
FIGURE 3.
VOUT
-
IN+
(EQ. 2)
VREF
+
+
-
V OUT = ( IN+ – IN- ) × Gain + V REF
+VCC
+VCC
(EQ. 1)
INSTRUMENTATION AMPLIFIER
OP AMP
FIGURE 1.
R2
R1
+
IN-
R2
R1
+
VOUT = (IN+ - IN-) * (1 + R2/R1)
IN+
FIGURE 2. TWO OP AMP INSTRUMENTATION AMPLIFIER
2
AN1298.2
May 27, 2009
Application Note 1298
and a common voltage of 10V, the inputs to the op amp will
be sitting at a voltage of 9.9V. This circuit would not be
possible if the op amp was operated with VCC of +5V since
the op amp input’s voltage would exceed the supply voltage.
R2
R1
IN-
-
IN+
+
VOUT
R2
100k
R3
R4
Vcm = 10V
VREF
VCC
R1
1k
-
VOUT
+
R3
1k
FIGURE 4.
R4
100k
In this configuration, the gain is set by resistors R1 and R2:
Gain = R 2 ⁄ R 1
(EQ. 3)
VREF
V OUT = ( IN+ – IN- ) × Gain + V REF
FIGURE 5.
(EQ. 4)
For the ability to reject a voltage that appears on both INand IN+ (i.e., common mode voltage), resistor values must
match such that R1 = R3 and R2 = R4. The common mode
rejection ratio (CMRR) is set by the matching ratio of R1:R3
and R2:R4. High common mode rejection ratio requires a
very high degree of ratio matching.
Two Amplifier Instrumentation Amplifier
To provide a high input impedance, a two amplifier
Instrumentation Amplifier can be used as in Figure 6.
R2
It can be shown that the CMRR is:
-
CMRR = 20 × log 10 (x)
(EQ. 5)
IN-
Where x = R 4 ⁄ ( R 3 + R 4 ) × ( R 1 + R 2 ) ⁄ R 1 – R 2 ⁄ R 1
(EQ. 6)
IN+
Worse case CMRR occurs when the tolerance of R4 and R1
are at their maximum, and R2 and R3 are at their minimum
value. The following table shows the relationship between
resistor tolerance and CMRR for gains of 1, 10, and 100.
TABLE 2.
RESISTOR
R1
CMRR
TOLERANCE
GAIN =1
GAIN = 10
GAIN =100
±5%
-20.4dB
-15.6dB
-14.8dB
±1%
-34.1dB
-28.9dB
-28.1dB
±0.1%
-54.0dB
-48.8dB
-48.0dB
±0.01%
-74.0dB
-68.8dB
-68.0dB
The Difference Amplifier has the advantage of simplicity and
the ability to operate with high common mode voltage on its
inputs, IN+ and IN-. However, the input resistance is set by
the resistor values R3 and R4, and does not provide high
input resistance as is common in most Instrumentation
Amplifier circuits.
+
R4
R3
-
VOUT
+
FIGURE 6. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER
In this configuration, the gain is set by resistors R3 and R4:
Gain = 1 + R 4 ⁄ R 3
(EQ. 7)
V OUT = ( IN+ – IN- ) × Gain
(EQ. 8)
The ability to reject a voltage that appears on both IN- and
IN+ (i.e., common mode voltage), depends on matched
resistor values such that, R1 = R3 and R2 = R4. The common
mode rejection ratio (CMRR) is set by the matching ratio of
R1:R3 and R2:R4, and, high CMRR requires a very high
degree of ratio matching. For example, with 10V of common
mode voltage, resistor tolerance’s must be at least ±0.01%
to achieve 12-bit accuracy (72dB).
Classic Three Amplifier Instrumentation Amplifier
By adding a third op amp, the “Classic Three Amplifier
Instrumentation Amplifier” can be configured as shown in
Figure 7.
Additionally, the REF input must be driven by a very low
source impedance since the CMRR will be degraded by any
source resistance that contributes to the value of R4 and
causes increased mismatch between R2 and R4.
Also note that the common mode voltage will bias internal
nodes at a voltage that is set by the ratio of R3 and R4, or the
gain of the circuit. For example, in Figure 5, for a gain of 100
3
AN1298.2
May 27, 2009
Application Note 1298
IN-
R1
+
Introduction to Instrumentation Amplifier
Product Family
R2
-
V2
R5
-
Rg
VOUT
VIN
V1
+
R6
-
IN+
INVOUT
VOUT
V4
R3
IN+
R4
VREF
+
FIGURE 7. CLASSIC THREE AMPLIFIER INSTRUMENTATION
AMPLIFIER
V3
FB+
FB-
Rf
Rg
Usually, resistors R1 through R6 are equal value resistors of
R and the gain:
Gain = ( 1 + 2 × R ⁄ R gain )
V OUT = ( IN+ – IN- ) × Gain + V REF
(EQ. 9)
FIGURE 8. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER
(EQ. 10)
This Application Note describes the Intersil Instrumentation
Amplifier Product Family, which includes the following
features:
With this circuit, the Gain can be set with a single resistor,
RGAIN and the input impedance is very high. However, the
common mode rejection ratio, CMRR, just like the Difference
Amplifier topology, is still set by the resistor matching
between R1, R2, R3, and R4. Extremely low tolerance
resistors or precision resistor trimming is required to achieve
high CMRR. The equations and Table shown for the
Difference Amplifier apply directly to the Classic Three
Amplifier Instrumentation Amplifier configuration.
Monolithic Instrumentation Amplifier
Architecture
Each of the three basic Instrumentation Amplifier architectures
that have been already discussed have been implemented in
standard integrated circuit packages. To achieve a high CMRR,
extensive resistor trimming is required with lasers or other
suitable techniques. While each of these devices provide
adequate specifications for a precision Instrumentation
Amplifier, each device has its own compromise based on
operating voltage range, supply current, common mode
operating range, input impedance, etc. These instrumentation
amplifiers use one external resistor to set the gain; while this
may seem to be an advantage, there are considerations which
make the single resistor configuration undesirable from a
design viewpoint. The temperature coefficient (TC) of the
external resistor will be a direct gain drift. Also, an external filter
can not be applied to the feedback network because it is
internal to the device.
4
1. Bipolar transistor inputs for low voltage noise
2. PMOS transistor inputs for low input bias current
3. Micropower operation requiring only 60μA supply current
4. Rail-to-rail inputs and rail-to-rail output swing
5. Single supply operation from 2.4V to 5V supply
6. An independent pair of feedback terminals to set the gain
and to adjust output level allow these Instrumentation
Amplifier to achieve high CMRR (>104dB) regardless of
the tolerance of the gain setting resistors.
7. Internal loop compensation to provide optimum
bandwidth trade-off as shown in Table 1
8. The ISL28271 and ISL28272 have an ENABLE pin to
reduce the supply current to a typical of less than 5µA and
tri-state the output stage to a high impedance state.
Instrumentation Amplifier Specifications
Many of the Instrumentation Amplifier specifications are very
similar to the standard specifications for operational
amplifiers. However, the unique architecture of the Intersil
Instrumentation Amplifiers make some of these
specifications differ slightly. Table 3 summarizes the
Specifications and Features of the Instrumentation Amplifier
Product Family.
AN1298.2
May 27, 2009
Application Note 1298
TABLE 3.
PARAMETERS
EL8170
Input Stage
Minimum Gain
Gain Set
Supply Current: Enabled
per Channel
Supply Current: Shutdown
-
ISL28270 ISL28470
EL8173
ISL28273
EL8171
ISL28271
EL8172
ISL28272
UNITS
Bipolar
Bipolar
PMOS
PMOS
100
10
10
100
2 Ext R
2 Ext R
2 Ext R
2 Ext R
65
65
65
60
65
60
µA
-
-
4
-
4
µA
-
-
Minimum VCC
2.4
2.4
2.4
2.4
VDC
Maximum VCC
5.5
5.5
5.5
5.5
VDC
Input Offset Voltage
200
150
150
1000
600
1500
600
300
500
μV
Offset Drift
0.24
0.7
0.7
2.5
0.7
1.5
0.7
0.14
0.7
µV/°C
Input Bias Current, Maximum
3000
2000
2500
2000
2500
50
30
50
30
pA
25
30
25
30
pA
Input Offset Current, Maximum
2000
2000
Input Bias Current Cancellation
Yes
Yes
Bandwidth (-3dB) at AV = 10
-
396
Bandwidth (-3dB) at AV = 100
192
240
240
Slew Rate (Typ)
0.55
0.5
0.5
265
450
0.55
180
0.6
0.55
0.5
170
100
kHz
0.55
0.5
V/µs
Rail-to-Rail Input
Yes
Yes
Yes
Yes
Rail-to-Rail Output
Yes
Yes
Yes
Yes
±26
±26
Output Current Limit, V+ = 5V
±26
Output in Shutdown Mode
Gain Accuracy
±29
±29
±26
-
±29
-
kHz
mA
-
HiZ
-
HiZ
±0.15
0.08
±0.2
-0.19
±0.35
±0.5
±0.5
±0.1
±0.12
CMRR (Typ)
114
110
110
106
110
PSRR (Typ)
106
110
110
90
95
90
100
eN at 1kHz
58
60
60
220
210
220
240
80
78
nv/√Hz
3.6
3.5
14
10
10
6
µVP-P
100
100
dB
100
dB
eN 0.1Hz to 10Hz
3.5
Input Protection - Diodes to
Rails
Yes
Yes
Yes
Yes
Input Protection - Diodes
across Inputs
Yes
No
No
No
Max Input Diode Current
5
5
5
5
SO8
SO8
SO8
SO8
-40 to +85
-40 to +85
-40 to +85
-40 to +85
Yes
Yes
Yes
Yes
Package
Operating Temp. Range
RoHS Compliant
5
%
mA
°C
AN1298.2
May 27, 2009
Application Note 1298
+Ven
I
I
I
Re
Va
V1
IN-
Re
Vb
Ix1
Q1
Ix2
Q2
IN+
V2
V3
I2
I1
I
Q3
FB+
I3
Q4
V4
FB-
I4
V5
V6
VOUT
I5
I6
Ry
GAIN = A
Ry
FIGURE 9. SIMPLIFIED SCHEMATIC
Instrumentation Amplifier Product Family
Theory of Operation
Each of the features specifications of the Intersil
Instrumentation Amplifier Product Family will be discussed in
more detail in a future section of this Application Note, but
first, let’s study the internal operation of this unique
Instrumentation Amplifier Product Family.
V5 = I5 × Ry = 2 × Ry × I + ( V1 – V2 ) × Ry ⁄ Re + ( V4 – V3 ) × Ry ⁄ Re
(EQ. 20)
V6 = I6 × Ry = 2 × Ry × I + ( V2 – V1 ) × Ry ⁄ Re + ( V3 – V4 ) × Ry ⁄ Re
(EQ. 21)
V OUT = A × ( V 5 – V 6 )
(EQ. 22)
where A is the gain of the output stage
A simplified schematic is shown in Figure 9.
( V 2 + V be2 ) – ( V 1 + V be1 )
I x1 = ----------------------------------------------------------------------, and since V be1 = V be2
Re
V2 – V1
I x1 = -------------------(EQ. 11)
Re
Assume Ry/Re = 1 (i.e., Re and Ry are equal value).
V OUT = A × [ 2 × R y × I + ( V 1 – V 2 ) + ( V 4 – V 3 ) –
[ 2 × R y × I + ( V 2 – V 1 ) + ( V 3 – V 4 ) ]]
(EQ. 23)
V OUT = A × [ ( V 1 – V 2 ) + ( V 4 – V 3 ) + ( V 1 – V 2 ) + ( V 4 – V 3 ) ]
Assuming β high transistors:
(EQ. 24)
I 1 = I + I x1 = I + ( V 2 – V 1 ) ⁄ R e
(EQ. 12)
V OUT = 2 × A × [ ( V 1 – V 2 ) + ( V 4 – V 3 ) ]
(EQ. 25)
V OUT ⁄ ( 2 × A ) = [ ( V 1 – V 2 ) + ( V 4 – V 3 ) ]
(EQ. 26)
Since A is very large:
I 2 = I – I x1 = I – ( V 2 – V 1 ) ⁄ R e
V OUT ⁄ ( 2 × A ) ⇒ 0
(EQ. 27)
Similarly for Q3 and Q4:
0 = ( V1 – V2 ) + ( V4 – V3 )
(EQ. 28)
I 3 = I + I x2 = I + ( V 4 – V 3 ) ⁄ R e
(EQ. 14)
Let VIN = V2 – V1, and V3 = FB+, V4 = FB-
I 4 = I – I x2 = I – ( V 4 – V 3 ) ⁄ R e
(EQ. 15)
(EQ. 13)
Summing currents:
0 = -V IN + ( FB- – FB+ )
(EQ. 29)
V IN + FB- – FB+
(EQ. 30)
or
I5 = I2 + I3 = I – ( V2 – V1 ) ⁄ Re + I + ( V4 – V3 ) ⁄ Re
(EQ. 16)
I5 = 2 × I + ( V1 – V2 ) ⁄ Re + ( V4 – V3 ) ⁄ Re
(EQ. 17)
I6 = I1 + I4 = I + ( V2 – V1 ) ⁄ Re + I – ( V4 – V3 ) ⁄ Re
(EQ. 18)
I6 = 2 × I + ( V2 – V1 ) ⁄ Re + ( V3 – V4 ) ⁄ Re
(EQ. 19)
6
IN+ – IN- = FB- – FB+
(EQ. 31)
As you can see from Equation 31, negative feedback is
applied around the amplifier so that the voltage applied to
the feedback terminals (FB+ - FB-) must be equal to the
voltage applied to the input terminals (IN+ - IN-).
AN1298.2
May 27, 2009
Application Note 1298
For the standard data sheet connection:
V2
VIN
The input terminals (IN+ and IN-) and feedback terminals (FB+
and FB-) are single differential pair devices aided by an Input
Range Enhancement Circuit to increase the headroom of
operation of the common-mode input voltage. As a result, the
input common-mode voltage range for all these Instrumentation
Amplifiers is rail-to-rail. The parts are able to handle input
voltages that are at or slightly beyond the supply and ground
making these in-amps well suited for single 5V or 3.3V low
voltage supply systems. There is no need then to move the
common-mode input voltage of the these Instrumentation
Amplifiers to achieve symmetrical input voltage.
IN+
V1
INVOUT
VOUT
V4
FB+
V3
Rf
FB-
The use of a bipolar transistor input stage vs. the MOSFET
input stage allows the user to choose low bias current, high
input resistance.
Rg
Rail-to-rail operation for both the inputs and outputs is an
important and unique feature. The rail-to-rail inputs allow the
input voltages to be slightly below the VS- rail (typically
Ground) to slightly above the VS+ rail.
FIGURE 10. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER
FB+ = 0V
FB- = V OUT × R g ⁄ ( R g + R f )
The conventional technique to achieve a rail-to-rail input
stage is to use two separate input stages, as shown in
Figure 12. One input stage (Q1 and Q2) provides common
mode input range to the top rail (VS+), and the other input
stage (Q3 and Q4) provides common mode input range to
the bottom rail.
V IN = FB- – FB+
V IN = V OUT × R g ⁄ ( R g + R f ) – 0
V OUT = V IN × ( 1 + R f ⁄ R g )
(EQ. 32)
Features of Instrumentation Amplifier
Product Family
A simplified schematic and block diagram is shown in
Figure 11 to illustrate the rail-to-rail operation for both the
input stage and the output stage. The same schematic
applies to the PMOS input devices when the PNP transistors
(Q1 to Q4) are replaced with P-Channel MOSFETs for
ultra-low input bias current.
VS+
INPUT RANGE ENHANCEMENT CIRCUIT
Ven = VS+ + 2V
I
I
I
Re
Vb
Va
Q1
IN-
I
Re
Q2
IBC
IN+
FB+
IBC
Q3
FB-
Q4
IBC
IBC
Q5
P-Channel
OUT
Ry
Ry
Q6
N-Channel
VSIBC => INPUT BIAS CURRENT CANCELLATION
FIGURE 11. SIMPLIFIED SCHEMATIC
7
AN1298.2
May 27, 2009
Application Note 1298
VS+
I
Q3
Q4
TRANSISTION
CIRCUIT
+IN
Q1
-IN
TO OUTPUT STAGE
INPUT OFFSET VOLTAGE (µV)
250
VDD = 5.5V
200
-40°C
150
100
+25°C
50
0
-50
-100
+85°C
-150
-200
-250
-0.5
Q2
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
COMMON-MODE INPUT VOLTAGE (V)
I
FIGURE 14. TYPICAL RAIL-TO-RAIL INPUT AMPLIFIER
FIGURE 12. 2 AMPLIFIER INSTRUMENTATION AMPLIFIER
Unless the input stages transistors are exactly matched,
changes in offset voltage and input bias current will result as
the common mode input range transitions between the two
input stages.
In contrast, the Product Family uses a single input stage for
the IN inputs and a single input stage for the FB inputs. An
Input Range Enhancement Circuit (IREC) provides a bias
voltage that is approximately 2V above the VS+ rail which is
used to bias the I current sources shown in the Block
Diagram. Since there is a single input stage, there is no input
stage transition point to create shifts in offset voltage and
bias current as the input common mode voltage changes.
The effectiveness of the Single Input Stage and IREC circuit
technique is evident as shown in the following Figures for the
offset voltage of a EL8170 (Figure 13) and a typical rail-torail input amplifier (Figure 14).
In addition to shifts in offset voltage as the input common
mode voltage changes, the input bias current will change
dramatically as the input stages transition from a PNP
transistor input stage to a NPN transistor input stage. The
following graphs compare the input bias current over the
common mode input range for the EL8170 (Figure 15) and a
typical rail-to-rail input amplifier (Figure 16).
AVERAGE INPUT BIAS CURRENT (pA)
VS-
1500
1000
VS = 3.3V
VS = 5.0V
500
0
VS = 2.9V
-500
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5
COMMON-MODE INPUT VOLTAGE (V)
250
200
+85°C
INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE
3
150
+25°C
100
50
-45°C
0
-0.5
0
0.5
1.0
1.5
2.0
2.5
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 13. EL8170
3.0
3.5
IIB - INPUT BIAS CURRENT - (nA)
INPUT OFFSET VOLTAGE (µV)
FIGURE 15. EL8170
2
VDD = 5V
TA = +25°C
1
0
-1
-2
-3
-4
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5
VIC - COMMON-MODE INPUT VOLTAGE (V)
FIGURE 16. TYPICAL RAIL-TO-RAIL INPUT AMPLIFIER
8
AN1298.2
May 27, 2009
Application Note 1298
The PNP input stage transistors are biased with an adequate
amount of current for speed, and consequently, their base
current increases. In order to keep the input bias current low,
an Input Bias Current Cancellation Circuit is used to apply
and equal but opposite compensation current to the inputs.
This compensation current subtracts from the base currents,
and the resulting input bias current is reduced to typically
around 500pA. This is shown in Figure 17 for the IN+ and INinputs, where the FB+ and FB- are identical for proper
matching between stages. The compensation current,
(Icomp) is derived from the IBC circuit and is equal to the
base current of Q1 and Q2.
Ven = VS+ + 2V
Re
Vb
Va
Q1
IN-
Q2
IN+
Icomp
Icomp
Q7
Q8
IBC
INPUT BIAS CURRENT
CANCELLATION
VS-
FIGURE 17. INPUT BIAS CURRENT CANCELLATION CIRCUIT
Since the feedback terminals are differential inputs, they can
be used in applications such as current sources for a true
Kelvin sense of the feedback voltage. In addition, a complex
network can be placed in the feedback path for frequency
shaping and filter circuits.
The basic Instrumentation Amplifier configuration is shown in
Figure 19:
Input Bias Current Cancellation Circuit is typically active
from 10mV above the negative rail (VS-) up to the positive
rail (VS+).
V2
Not only does the Input Bias Current Cancellation
compensation circuit keep the input bias current very small,
it also maintains a very small input bias current variation
over a wide operating range as shown in Figure 18 for +25°C
to +85°C.
AVERAGE INPUT BIAS CURRENT (pA)
Another unique feature built into the ISL28271 and ISL28272
is the ability to tri-state the output stage to a high impedance
state when the part is disabled via the ENABLE pin. This
allows several outputs to be wired together for a multiplexer
function. This feature will be shown in the Applications
section.
Because the Instrumentation Amplifier product family
provides an independent pair of feedback terminals to set the
gain and to adjust output level, these Instrumentation
Amplifiers achieve high CMRR regardless of the tolerance of
the gain setting resistors. The FB+ pin can be used as a REF
terminal to center or to adjust the output voltage. Because the
FB+ pin is a high impedance input, an economical resistor
divider can be used to set the voltage at the REF terminal
without degrading or affecting the CMRR performance. Any
voltage applied to the REF terminal will shift the output
voltage by VREF times the closed loop gain, which is set by
resistors RF and RG.
I
I
The operating voltage range of the Instrumentation Amplifier
product family is from 2.4V to 5.5V making it ideally suited
for operation on 3.3V or 5V power supplies. Also, it will
operate with a single 4.2 lithium ion battery. Additionally, they
are well suited for battery operation since the supply current
is only 66µA maximum.
1500
VIN
V1
INVOUT
VOUT
V4
V3
VS = 3.3V
IN+
FB+
FB-
Rf
1000
500
+85°C
0
+25°C
Rg
FIGURE 19. TYPICAL RAIL-TO-RAIL INSTRUMENTATION
AMPLIFIER
-500
-1000
-0.5
0
0.5
1.0
1.5
2.0
2.5
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 18.
9
3.0
3.5
The gain of this circuit is set by the ratio of Rf and Rg such
that:
V OUT = V IN × ( 1 + R f ⁄ R g )
(EQ. 33)
AN1298.2
May 27, 2009
Application Note 1298
In this configuration, adjustable gain is possible with external
resistors for gains from unity up to 10,000. Two external gain
setting resistors are used to minimize temperature
coefficient (TC) mismatch as is common with a single gain
setting resistor.
Notice that resistor value mismatches only effect the gain,
and CMRR is not degraded by resistor mismatches as is the
case with the other basic Instrumentation Amplifier
configurations discussed previously.
In this case:
V REF = V CC × R 2 ⁄ ( R 1 + R 2 )
(EQ. 37)
The feedback terminals can also be used to apply a
reference voltage to shift the output voltage as shown in
Figure 22 with Rg connected to VREF instead of ground.
IN+
VIN
INVOUT
VOUT
The feedback terminals can be used to apply a reference
voltage to shift the input voltage. These are a high
impedance reference input that is not affected by gain. The
basic circuit is shown in Figure 20:
VREF
FB+
FB-
Rf
IN+
VIN
Rg
INVOUT
VOUT
VREF
FB+
FIGURE 22.
Rf
FB-
V IN = FB- – FB+
FB- = V REF + R g × ( V OUT – V REF ) ⁄ ( R f + R g )
V IN = V REF + R g × ( V OUT – V REF ) ⁄ ( R f + R g ) – V REF
Rg
V OUT = V IN × ( 1 + R f ⁄ R g ) + V REF
FIGURE 20. BASIC CIRCUIT
If we go back to the equations derived previously:
V IN = FB- – FB+
(EQ. 34)
V IN = V OUT × R g ⁄ ( R f + R g ) – V REF
(EQ. 35)
V OUT = ( V IN + V REF ) × ( 1 + R f ⁄ R g )
(EQ. 36)
Since the FB+ is a high input impedance, a simple resistor
divider could be used to set the VREF voltage as shown in
Figure 21.
IN+
VIN
INVOUT
VOUT
VCC
Rf
VREF
FB+
Rf
FB-
Rg
Rg
(EQ. 38)
Since the current in Rg must flow into VREF, the driving point
impedance of VREF will effect the accuracy of this
configuration. Therefore, VREF should be a low impedance
from an op amp, voltage regulator, or voltage reference.
Alternately, if a resistor divider is used to obtain VREF, the
Thevenin resistance of the divider network must be much
lower than the values of Rf and Rg, or the Thevenin
resistance must be included in the value of Rg and VREF.
However, the CMRR is not affected by the reference voltage
or its source resistance.
Care and Feeding of Instrumentation
Amplifiers
As in any low voltage, high accuracy measurement system,
extreme care must be taken with any of the Instrumentation
Amplifiers with respect to grounding scheme, Kelvin sense
connections, guarding and shielding, and interface to the
digital world. If the PCB connections are made incorrectly,
the most perfect measurement circuit can still have errors
resulting from poor grounding considerations and not
understanding the impact of Ohm’s Law. Any analog or
mixed signal PCB must have a well thought-out grounding
scheme with multiple ground planes or traces. There must
be no heavy DC current or AC current in the analog ground
planes that connect system measurement points.
FIGURE 21.
10
AN1298.2
May 27, 2009
Application Note 1298
be sure there is no digital noise introduced into the Analog
Ground, the two grounds are tied together at only one point
at the A/D Converter. Furthermore, a 0Ω resistor can be
used to connect the two grounds; this ensures a separate
Net for each ground so the PCB layout software or layout
person does not arbitrarily connect the two grounds. The use
of a 0Ω resistor is cheap insurance against a noisy and
inaccurate analog system! This Thermocouple Circuit will be
discussed in more detail in the Applications section.
A one point measurement system must be established to
prevent high currents from interfering with the basic
measurement. This is shown in Figure 23 for interfacing a
thermocouple to an A/D Converter. The “High quality
measurement Ground” must only connect to the critical
ground points in the analog front-end; this ground must
make a single point connection to the A/D converter at its
Analog Ground pin (AGND). There must be no other
connections such as digital grounds or power supply returns
to the “High quality measurement Ground” except a single
connection at the A/D Converter pins (AGND and DGND). To
+5V
7
VS+
+5V
R1
R
INPUT FILTER
J-TYPE
THERMOCOUPLE
(51.7µV/C)
R2
R
IBIAS
+5V RETURN
LM35DM
(10m/C)
OPEN TC BIAS
R4
R
3
VS- 4
IN+
C1
C
(Vtc)
2
IN- V
OUT 6
(Vcjc) 8
R3
FB+
R
5
VOUT = (Vtc + Vcjc) * (1 + Rf/Rg)
Rf
191k, 1%
FB-
GAIN = 1 + Rf/Rg
GAIN = 1 + 191k/1k
GAIN = 192
R5
191k,
1%
R6
1k, 1%
A/D CONVERTER
s
VIN
ISL6007DIB825
Rg
1k, 1%
VOUT
(2.5V)
VREF
GND
HIGH QUALITY
MEASUREMENT GROUND
AGND
s
DGND
CONNECT AGND AND DGND
AT ONE POINT AT ADC
d
FIGURE 23.
Rs
1.2V
DC/DC CONVERTER
OUTPUT
PROCESSOR LOAD
10A, MAX
0.005Ω
10k
0.1µF
+5V
10k
7
VS+
EL8171, EL8173, ISL28273, ISL28271
3 IN+
2 INVOUT
6
VOUT = 0V to + 2.5V
8 FB+
5 FB- V S
Rf
48.7k, 0.1%
4
GAIN = 50
Rg
1k, 0.1%
FIGURE 24.
11
AN1298.2
May 27, 2009
Application Note 1298
Instrumentation Amplifiers can be used in high accuracy
current sense applications as shown in the circuit in Figure 24.
Notice the use of a Kelvin connection shown on the current
sense resistor Rs as indicated by the slanted connections to
the resistor. To avoid errors caused by IR drops, the
connections must be made directly at the leads of the
0.005Ω current sense resistor. Just 1mΩ of contact
resistance or PCB trace resistance will cause a 20% error in
the current reading.
Guarding and driven guards is a PCB layout technique to
reduce errors caused by PCB leakage currents and improve
high frequency CMRR. This can be done by surrounding
high impedance input leads with traces that are driven by a
low source impedance voltage that is equal to the common
mode voltage.
At any point in a circuit where dissimilar metals come in
contact a small thermocouple voltage is developed.
Fortunately, the copper lead frame of a surface mount device
is the same copper material as PCB etch, and the
thermocouple effect is minimized. However, there are many
other places where thermocouples can be generated; for
example, across a connector finger, across relay contacts, or
even across a resistor! Yes, a poorly constructed resistor
can show many µV/°C of thermocouple voltage. It has been
found that external components (resistors, contacts, sockets,
etc.) can create thermocouple voltages that exceed
10µV/°C.
It must be recognized that thermocouple voltages are
developed by the difference in temperature between the two
ends of dissimilar metal junctions, and not the absolute
ambient temperature. If both ends of the metal junctions are
isothermal (i.e., at the same temperature) there is no
thermocouple voltage developed. Therefore, the first rule to
avoid thermocouple effects is to eliminate hot spots on a
PCB (e.g., linear voltage regulators). If hot spots cannot be
avoided, then the two ends of metal junctions must be
oriented so they are on isothermal lines on the PCB.
The second rule to minimize thermocouple effects is to
balance the number of junctions in a loop so that the error
voltages are cancelled or become a common mode voltage
that is reduced by the CMRR of the op amps in the signal
chain. If the number of junctions are not balanced, then it
may be necessary to create a junction by adding a series
resistor that has no effect on circuit operation but balances
the number of junctions.
Unknown to most design engineers is the danger of internal
clipping when operating an instrumentation amplifier on a
single supply. Unfortunately, the internal nodes are invisible
to the user and impossible to measure; manufacturer’s data
sheets often ignore the issue, or they have obscure “typical
characteristics” graphs or misleading paragraphs that
attempt to explain the phenomena. Since the
Instrumentation Amplifiers operate in a current summing
12
mode as explained in the “Instrumentation Amplifier Product
Family Theory of Operation” on page 6 there is no possibility
of internal clipping.
If we review the classic three amplifier instrumentation
amplifier configuration shown in Figure 25, the effect of
internal clipping can be clearly shown.
VCC
INA1
VIN
Rg
100
IN+
A2
VO1
+
-
10k
R1
50k
10k
-
R2
50k
VOUT
+
10k
+
A3
VO2
10k
VREF
Vcm
FIGURE 25.
Simple circuit analysis shows that the two internal voltage
VO1 and VO2 are:
V O1 = V IN × ( 1 + R 1 ⁄ R g ) + V cm
(EQ. 39)
V O2 = V cm – V IN × R 1 ⁄ R g
(EQ. 40)
Two clipping conditions will occur if the effects of VIN and
Vcm are not considered:
1. VO1 cannot exceed the maximum output voltage for A1
which is the supply voltage (VCC) and the saturation
voltage of A1’s output stage.
V IN × ( 1 + R 1 ⁄ R g ) + V cm < V CC + V sat
(EQ. 41)
2. VO2 cannot go below Ground + the saturation voltage of
A2’s output stage.
V cm > V IN × R 1 ⁄ R g + V sat
(EQ. 42)
In reality, this places a such a severe restriction on single
supply operation that it makes this circuit almost impossible
to use as a general purpose single supply instrumentation
amplifier. For example, A2 output stage saturation voltage
prevents even 0V of common mode voltage!
To overcome this issue, modern monolithic IC
instrumentation amplifiers add PNP level shift transistors (Q1
and Q2) to raise the input voltages off Ground as shown in
the circuit in Figure 26.
AN1298.2
May 27, 2009
Application Note 1298
A1
VO1
+
Q1
there is no possibility of internal clipping. As long as the total
of the common mode voltage plus the input signal is
between 0V and the VS+ supply voltage there will be no
internal clipping. The output voltage will swing within its railto-rail output specification of 10mV to either rail for a 100kΩ
load. There is no restriction on differential input voltage or
common mode voltage provided the output voltage does not
exceed its full scale range due to input voltage level, gain,
CMRR, and VREF level.
-
IN-
VCC
VIN
Rg
100
R1
50k
R2
50k
-
Q2
+
IN+
VO2
A2
Vcm
FIGURE 26.
The two internal voltage VO1 and VO2 are now:
V O1 = V IN × ( 1 + R 1 ⁄ R g ) + V cm + 0.7V
(EQ. 43)
V O2 = V cm – V IN × R 1 ⁄ ( R g + 0.7V )
(EQ. 44)
Now, the danger of internal clipping situation has been
improved for A2 but made worse for A1 since an additional
0.7V has been added to VO1. For example, the maximum
common mode voltage is only 1.5V for this instrumentation
amplifier operating on a supply voltage of 5V ±5% with a
gain of 250 and a 10mV input signal! If you doubt the validity
of these statements, check vendor data sheets for analog
devices that exhibit these characteristics.
All input and feedback terminals of the Instrumentation
Amplifiers have internal ESD protection diodes to both
positive (VS+) and negative supply (VS-) rails, limiting the
input voltage to within one diode drop beyond the supply
rails. The EL8170, EL8172, ISL28270 and ISL28470 have
additional back-to-back diodes across the input terminals
and also across the feedback terminals. If overdriving the
inputs is necessary, the external input current must never
exceed 5mA. On the other hand, the EL8171, EL8172,
ISL28271, ISL28272 and ISL28273 have no diode clamps to
limit the differential voltage on the input terminals allowing
higher differential input voltages at lower gain applications. It
is recommended however, that the input terminals of these
devices are not overdriven beyond 1V to avoid offset drift.
An external series resistor may be used as an external
protection to limit excessive external voltage and current
from damaging the inputs. A 20k resistor can be used to
protect the inputs against 100V transients on the inputs. If
the overvoltage condition is continuous, the 20k resistor
must be rated at 1W for adequate power dissipation.
Since the Instrumentation Amplifiers operate in a current
summing mode as explained in the “Instrumentation
Amplifier Product Family Theory of Operation” on page 6,
Ven = VS+ + 2V
VS+
I
I
Re
VS+
VS+
IN-
I
I
Re
VS+
FB-
IN+
VS-
VS-
VS-
VSEL8170 ONLY
EL8170 ONLY
INPUT BIAS CURRENT
CANCELLATION
5mA MAXIMUM INTO ANY PROTECTION DIODE!
INPUT BIAS CURRENT
CANCELLATION
VS-
FIGURE 27. INPUT PROTECTION DIODES
13
AN1298.2
May 27, 2009
Application Note 1298
20k
VIN
20k
3
2
TRANSFORMER
COUPLED SOURCE
IN+
VIN
INVOUT
8
5
3
6
IN+
2
IN-
VOUT
VOUT
8
FB+
Rf
FB-
6
VOUT
FB+
5
Rf
FB-
Rg
Rg
FIGURE 28.
FIGURE 30.
Input bias current from the IN+ and IN- inputs of the
Instrumentation Amplifiers must find a DC path to their home
(i.e., Ground). While it seems obvious to the casual user, this
is an often ignored principle when designing with an
Instrumentation Amplifier, and results in many telephone
calls to the Applications Engineer. Many voltage sources do
not provide a DC path to Ground such as thermocouples,
microphones, transformer coupled circuits, and AC coupled
circuits. Without a DC return path, the input bias current will
accumulate on any stray capacitance on the inputs until they
are clamped to the rails by the protection diodes. The output
of the Instrumentation Amplifier will slowly increase or
decrease until it saturates into the VS+ or VS- rail.
AC COUPLED SOURCE
VIN
3
2
47k
IN+
INVOUT 6
47k
8
5
VOUT
FB+
FB-
Rf
Rg
A DC return path as shown in the following circuits must be
supplied to provide a return path for the input bias current.
3
VIN
2
FIGURE 31.
IN+
INVOUT
10k
8
5
6
VOUT
FB+
Rf
FB-
Rg
An error budget can be calculated by summing the factors
which contribute to the output voltage error. Most of the error
sources are referred to the input and multiplied by the Gain
to get an output voltage error term as shown in the following.
Offset voltage: Normally instrumentation amplifiers have
two offset voltage specifications - an input offset voltage
(VOSI) and output offset voltage (VOSO) specification such
that the input offset voltage is multiplied by the gain, and the
output offset voltage exhibits unity gain to the output voltage.
Therefore, the output voltage error from offset voltage is:
V OUT = Gain × V OSI + V OSO
FIGURE 29.
Due to the unique architecture of the Instrumentation
Amplifiers, there is only one offset voltage specification
required. The input offset voltage (VOSI) is the amount of
voltage applied the inputs terminals such that the voltage
across the FB is zero, or input offset voltage will be the
difference between the IN terminals and the FB terminals:
( IN+ – IN+ ) = ( FB+ – FB- ) + V OS
14
(EQ. 45)
(EQ. 46)
AN1298.2
May 27, 2009
Application Note 1298
V IB = R S × I OS
(EQ. 48)
0.1Hz to 10Hz Noise: The error introduced by voltage can
be modeled the same as an input offset voltage, Vn. If noise
is required in a wider bandwidth than 0.1Hz to 10Hz, the
noise can be calculated by evaluating the Input Noise
Voltage Density (en) over the desired bandwidth. Multiplying
the rms noise by six will give a good approximation for the
peak-to-peak noise.
V OUT ( I OS ) = Gain × R S × I OS
(EQ. 49)
V OUT ( V n ) = Gain × V n
V OUT ( V OSI ) = Gain × V OSI
(EQ. 47)
Offset bias current: Similar to an Op Amp circuit, the input
resistance creates an error source that can be modeled the
same as offset voltage such that:
Gain Error: Gain error results from two factors. The first is
the basic gain deviation from the ideal gain equation, Gain =
(1 + Rf/Rg); for the EL8173 this error (E.g.) is typically
±0.2%. Second is the tolerance (ERf and ERg) of the Rf and
Rg resistors which set the Gain.
Common Mode Rejection Ratio: The error introduced by
common mode voltage can be modeled the same as an
input offset voltage, VCMR.
CMRR = 20 × log
10
V CMR = V CMV × 10
( V CMR ⁄ V CMV )
(EQ. 50)
( CMRR ⁄ 20 )
V OUT = V IN × ( 1 + R f ⁄ R g ) × [ 1 – ( ER f + ER g + Eg ) ]
(EQ. 51)
V OUT ( CMRR ) = Gain × V CMR
Rs
PROCESSOR LOAD
10A, MAX
0.005Ω
10k
0.1µF
(EQ. 54)
Temperature Drift: The effect of operating over the
expected temperature range must be included in all these
calculations based on the data sheet specifications.
(EQ. 52)
1.2V
DC/DC CONVERTER
OUTPUT
(EQ. 53)
+5V
10k
EL8171, EL8173, ISL28273, ISL28271
7
VS+
3 IN+
2 INVOUT
6
VOUT = 0V to + 2.5V
8 FB+
Rf
48.7k, 0.1%
5 FB- V S
4
GAIN = 50
Rg
1k, 0.1%
FIGURE 32.
TABLE 4. ERROR BUDGET CALCULATION
ERROR SOURCE
SPECIFIED VALUE
REFEREED TO OUTPUT
% FS ERROR
Offset voltage
400µV
20mV
0.8%
Input Offset Current
0.5nA
0.25mV
0.01%
CMRR
104dB
0.24mV
0.01%
0.1Hz to 10Hz Noise
10µV
0.5mV
0.02%
Gain Error
0.2%
0.2%
Rf, Rg Tolerance
0.1%
0.2%
Total Error
15
1.24%
AN1298.2
May 27, 2009
Application Note 1298
Example of an Error Budget Calculation
Consider the circuit shown in Figure 32 for a CPU core
voltage current monitor circuit operating at +25°C.
The importance of an Error Budget as shown in Table 4 is
that it is shows the overall accuracy which can be expected
and which factors are determining the overall accuracy of
the circuit. In this circuit, the Offset voltage is the factor
which is driving the Total Error; if tighter accuracy is required
for the application, the offset term could be removed by
hardware calibration with a digital potentiometer or software
calibration. The Total Error could be reduced to 0.5% just by
decreasing the offset voltage term by a factor of 10.
within a few millivolts of the supply rails. At a 100kΩ load, the
PMOS sources current and pulls the output up to 4mV below
the positive supply, while the NMOS sinks current and pulls the
output down to 4mV above the negative supply, or ground in
the case of a single supply operation. As the load current is
increased, the maximum output voltage will decrease as a
result of the voltage drop caused by the sourced load current
times the top MOSFET ON resistance. Likewise, the minimum
output voltage will increase as a result of the voltage drop
caused by the sink load current times FET ON resistance.
The current sinking and sourcing capability is internally
limited to about 26mA with a 5V supply.
Because of the independent pair of feedback terminals
provided by Intersil’s Instrumentation Amplifiers, the CMRR
is not degraded by any resistor mismatches. Hence, unlike a
three op amp and especially a two op amp instrumentation
amplifier, the Intersil solution will reduce the cost of external
components by allowing the use of 1% or more tolerance
resistors without sacrificing CMRR performance. The CMRR
will be greater than 100dB regardless of the tolerance of the
resistors used.
Care must be taken with excessive load capacitance, CLOAD.
As shown in the following graphs, excessive load capacitance
will cause excessive peaking in the frequency response. The
result will be ringing in the output voltage under transient
conditions, and potentially oscillations resulting from unstable
operation. If the Instrumentation Amplifiers are used in
applications where there may be large load capacitance
(cable driving, filters, FET gates, etc.), a suitable buffer should
be used on the output of the Instrumentation Amplifier.
The effects of loading the rail-to-rail output stage must also be
considered too since the output stage exhibits an “ON” state
resistance. A pair of complementary MOSFET devices with
approximately 50Ω ON resistance drives the output VOUT to
Noise calculations for the Instrumentation Amplifiers are very
similar to those for an op amp circuit. The noise model is shown
in the following where the Input Noise Voltage and Input Noise
Current noise sources are lumped into the IN+ terminal.
25
30
VS = ±2.5V
25
MAGNITUDE (dB)
MAGNITUDE (dB)
20
VS =
15
VS =
10 A = 10
V
RL = 1kΩ
C = 10pF
5 RL/R = 9.08Ω
F G
RF = 178kΩ
RG = 19.6kΩ
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
FIGURE 33. EL8171 FREQUENCY RESPONSE vs SUPPLY
VOLTAGE
20
CL = 27pF
15
A = 10
10 VV = 5V
S
RL = 10kΩ
5 RF/RG = 9.08Ω
RF = 178kΩ
RG = 19.6kΩ
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
FIGURE 34. EL8171, EL8172 FREQUENCY RESPONSE vs
CLOAD
50
30
CL = 47pF
CL =
20
CL = 27pF
15
A = 10
10 VV = 5V
S
RL = 10kΩ
R
5
F/RG = 9.08Ω
RF = 178kΩ
RG = 19.6kΩ
0
100
1k
10k
100k
FREQUENCY (Hz)
CL =
1M
CL =
40
CL = 820pF
35
30
FIGURE 35. EL8171 FREQUENCY RESPONSE vs CLOAD
16
45
MAGNITUDE (dB)
25
MAGNITUDE (dB)
CL =
CL = 47pF
AV = 100
VS = 5V
RL = 10kΩ
RF/RG = 99.02Ω
RF = 221kΩ
RG = 2.23kΩ
25
100
1k
CL = 390pF
10k
100k
FREQUENCY (Hz)
1M
FIGURE 36. EL8172 FREQUENCY RESPONSE vs CLOAD
AN1298.2
May 27, 2009
Application Note 1298
en(V)
en(I1)
en(I2)
en(Rs)
en(Rfg)
V
V
V
V
V
IN+
IN-
Rs
VOUT
VOUT
FB+
Rf
FB-
Rg
NOISE MODEL
FIGURE 37.
Where: en(V) is the Input Noise Voltage over the desired
bandwidth en(I1) is the voltage noise generated by the Input
Noise Current over the desired bandwidth and the source
resistance (Rs):
The 1.57 term in the equations is the noise equivalent
bandwidth representing a 1st order roll-off equivalent as if
there is a brick wall filter at 1.57*Fh. If we have a brick wall
filter that cuts off right (infinitely steep) at Fh then this term is 1.
e n ( I1 ) = I IN × R s
1st order = 1.57
2nd order = 1.11
3rd order = 1.05
4th order = 1.025
(EQ. 55)
en(I2) is the voltage noise generated by the Input Noise
Current over the desired bandwidth and the feedback and
gain resistors (Rf || Rg):
e n ( I2 ) = I IN × R f || R g
(EQ. 56)
en(Rs) is the thermal noise over the desired bandwidth of Rs.
en(Rfg) is the thermal noise over the desired bandwidth of
Rf || Rg
Rs is the source resistance
2
2
2
2
2
2
e n = ( 1 + R f ⁄ R g ) × ( e n ( V ) + e n ( I1 ) + e n ( I2 ) + e n ( I2 ) + e n ( Rs ) + e n ( Rfg ) )
(EQ. 59)
The peak-to-peak output noise is typically 6 times the rms
value (rule of thumb).
Rf and Rg are the gain setting resistors
To calculate rms noise, N over a desired bandwidth:
N = N O ( F C × ln ( F h ⁄ F l ) + 1.57 × F h – F l )
To determine the total rms output noise from all the sources,
the rms summation is taken multiplied by the gain.
en ( P – P ) = 6 × en
(EQ. 60)
(EQ. 57)
eno(pp) = 6 * eno
where: NO is the specified noise density in nV/√Hz
Fc is the corner frequency
Fh is the upper frequency of interest
Fl is the lower frequency of interest
To calculate resistor thermal noise over a desired bandwidth:
Nr =
4kTR × ( 1.57 × F h – F l )
(EQ. 58)
where: R is the resistor value
k is Boltzman’s Constant, 1.39*10-23
T is temperature in Kelvins
Fh is the upper frequency of interest
Fl is the lower frequency of interest
17
AN1298.2
May 27, 2009
Application Note 1298
+5V
Rb1
1k
Rb3
1k
+5V
R1
7.5k
3
R2
7.5k
2
IN+
7
VS+
INVOUT
Rb2
1k
Rb4
1k
8
5
6
VOUT + 0V to 2.5V
FB+
FB- VS-
Rf
100k
4
Rg
100k
FIGURE 38.
Example of Noise Calculation:
Consider the circuit shown in Figure 38 for a bridge amplifier operating in a 0.5Hz to 100Hz bandwidth with a full scale output
voltage of 2.V.
eN = 50nv/√Hz
From the EL8170 data sheet specifications
Fc = 100Hz
From the EL8170 data sheet performance curves
iN = 0.1pA/Hz
From the EL8170 data sheet specifications
Fc = 50Hz
From the EL8170 data sheet performance curves
Rs = 8kΩ
Balanced bridge Thevenin resistance + 7.5kΩ resistor
Rfg = 990Ω
Rf || Rg = 90.9k || 1k
e n ( V ) = 50nV ⁄ Hz × 100Hz × L n ( 100Hz ⁄ 0.5Hz ) + 1.57 × 100Hz – 0.5Hz
= 0.81 μV, rms
(EQ. 61)
e n ( I1 ) = 0.1pA ⁄ Hz × 50Hz × L n ( 50Hz ⁄ 0.5Hz ) + 1.57 × 100Hz – 0.5Hz × 8k
= 0.12 μV, rms
(EQ. 62)
e n ( I2 ) = 0.1pAnV ⁄ Hz × 50Hz × L n ( 50Hz ⁄ 0.5Hz ) + 1.57 × 100Hz – 0.5Hz × 990
= 0.0014 μV, rms
e n ( Rs ) =
(EQ. 63)
( 4 × k × 300°K × 8k × ( 100Hz – 0.5Hz ) )
= 0.12 μV, rms
e n ( Rfg ) =
(EQ. 64)
( 4 × k × 300°K × 990 × ( 100Hz – 0.5Hz ) )
= 0.04 μV, rms
(EQ. 65)
18
AN1298.2
May 27, 2009
Application Note 1298
2
2
2
2
+5V
2
e n = ( 1 + R f ⁄ R g ) × ( e n ( V ) + e n ( I1 ) + e n ( I2 ) + e n ( Rs ) + e n ( Rfg ) )
2
2
2
2
7
3
2
= ( 1 + 90.9k ⁄ 1k ) × (0.81μV +0.012μV +0.0014μV +0.12μV +0.04μV )
= 100 × 0.82μV
(EQ. 66)
= 82 μVrms
VIN
2
To determine the total rms output noise from all the sources,
the rms summation is taken multiplied by the gain.
8
Note that the total output noise is dominated by basic Input
Noise Voltage and higher source resistance could be used
without degrading the overall error resulting from noise.
e n ( P – P ) = 6 × 82μV
5
IN+
VS+
IN-
VOUT 6
VOUT
FB+
Rf
100k
FB- VS-
Rf
12k
Cx
0.1µF
4
(EQ. 67)
= 492 μV P – P
GAIN = 100 BELOW 14Hz
GAIN = 100 BELOW 140Hz
Rg
1k
This represents an error of 0.02% for a 2.5V full scale output.
A very unique feature of the Intersil Instrumentation
Amplifiers is the ability to put a filter circuit in the feedback
network to shape the frequency response of the amplifier.
This ability is not possible with other monolithic
Instrumentation Amplifiers because they use a single
resistor at the input stage to set the gain. Adding filter circuits
in the feedback network of an Instrumentation Amplifier
implemented with discrete components (op amps and
resistors) is very difficult because capacitor mismatch will
result in very poor high frequency CMRR.
GAIN = 100
GAIN = 10
14Hz
Flp
140Hz
Fhp
FIGURE 39.
A complex impedance network can be added as shown in
the following for a low pass function. The low frequency gain
is set by Rf and Rg using the standard equation:
For this circuit, it can be shown that low frequency pole and
higher frequency zero are:
Gain = 1 + Rf ⁄ R g
Flp = 1 ⁄ ( 2 × π × C x × ( R f + R x ) )
(EQ. 68)
The Instrumentation Amplifiers are not unity gain stable; i.e.,
they require gains greater than 10 or 100 depending on the
device. Therefore, they must never be allowed at unity gain
even at high frequencies! If Rx was not included in this
circuit, Cx would dominate at high frequencies, and the
Instrumentation Amplifier would be unstable and oscillate.
Lab tests have shown that Cx >33pF is enough to cause an
oscillation. Adding Rx in series with Cx creates a zero in the
transfer function so that at higher frequencies Rx parallels Rf
so that the new Rf = 10.7k, and the gain at high frequency is
11.7 which is a stable condition. Lab tests have shown that
any value can be used for Cx with no oscillations.
19
Pole Frequency
= 1 ⁄ ( 2 × π × 0.1μF × ( 100k + 12k ) )
= 14Hz
Flp = 1 ⁄ ( 2 × π × C x × R x )
(EQ. 69)
Zero Frequency
= 1 ⁄ ( 2 × π × 0.1μF × 12k )
= 140Hz
(EQ. 70)
AN1298.2
May 27, 2009
Application Note 1298
6
7
8
3
1
2
A2
A1
VIN+
SW0 CLOSED
V+ 10 +5V
SW1 CLOSED
4
INH
SW2 CLOSED
SW3 CLOSED
A2
A1
NO0
NO1
NO2
NO3
Com 9
U1
ISL43640
GND
Vcm
MEASURE VIN+ - VINMEASURE CMRR TO ZERO
MEASURE VOS TO ZERO
MEASURE 25mV CAL REFERENCE
5
VIN-
R2, 1M
A2
A1
NO0
NO1
NO2
NO3
GND
5
6
(VREF)
R3
100k
R1, 10k
REQ = 9900Ω
V+ 10
+5V
INH 4
WRITE
PROTECT
U2
ISL43640
VOUT VIN
C2
0.01µF
C1
10µF
R9
309
R5
48.7k
R7
66.5k
R6
1k
-5V
U3
ISL6007DIB825
OFFSET CORRECTION (±25mV)
VOUT
R8
150k, 1%
5 FB-
RW 5
50k
RL 6
2 +5V
GND
1 4
R4, 2k
s
VOUT 6
8 FB+
8
VCC
1 WP-L
RH 7
GND
U5 4
ISL95810
s
+5V
VS- 4
2 IN-
2 SCL
RP1
I2C BUS
3 SDA
Com 9
VS+ 7
3 IN+
+5V
6
7
8
3
1
2
U4
EL8173
+5V
8
VCC
7 RH
WP-L 1
5 RW
50k
6 RL
SCL 2
RP2
SDA 3
GND
4
R10
1.37k, 1% s
s
WRITE
PROTECT
I2C Bus
U6
ISL95810
PROGRAMMABLE GAIN, 90 TO 110
CALIBRATION REFERENCE (25mV)
FIGURE 40. ANALOG FRONT-END CIRCUIT
Application Circuits
Instrumentation Amplifier With Auto Zero and
Auto Gain Calibration
The circuit shown in Figure 40 shows an analog front-end
circuit with an Auto Zero and Auto Gain Calibration to eliminate
the offset voltage and gain errors of the EL8173. It is intended
to be part of an overall data acquisition system with an A/D
Converter and microprocessor to perform an auto zero/gain
software routine. Figure 40 does not include the A/D Converter
or processor hardware/software.
TABLE 5.
A2
A1
SWITCH
CLOSED
MODE
0
0
SWO
Measure the input voltage VIN+ - VIN-
0
1
SW1
Calibrate with external common mode
voltage applied
1
0
SW2
Calibrate offset voltage to zero
1
1
SW3
Calibrate gain with 25mV reference
voltage applied
During the calibration mode, analog switches S1 and S2
connect the inputs of the EL8173 to calibration source voltages
of zero volts, an external common mode voltage, or a 25mV
reference voltage. Digital potentiometer (D-Pot) U5 applies a
programmable offset voltage of ±25mV to the FB+ pin of the
EL8173 to adjust the EL8173 output to zero voltages. Digital
potentiometer (D-Pot) U6 programs the gain of the EL8173
from 90 to 110 for a 2.5V output with the +25mV reference
voltage applied to the inputs.
20
Since the offset calibration voltage is operating at very close
to zero voltages (±25mV), the driving point impedance is
kept very low (1k, R6) to avoid variations caused by the
increasing bias current. The configuration of U5, R5, and R7
is carefully selected so that the D-Pot never is operated at a
negative voltage.
The ±25mV offset calibration source is obtained by
programming U5 with the appropriate digital code in
Equation 71.
1
1
5∗ ⎛ --------------------------⎞ – ------⎝R + R ⎠ R
1
pot
2
Vcal = ----------------------------------------------------------1
1
1
⎛ -------------------------⎞ + ------- + ------⎝R + R ⎠ R
1
pot
2 R3
(EQ. 71)
The +25mV reference voltage is obtained with the ISL6007’s
2.5V output voltage divided down by a factor of 100 with R1,
R2, and R3. The accuracy of the gain calibration is
determined by the accuracy of the ISL6007 and the
tolerance of resistors R1 and R2. Therefore, it is
recommended to use very low tolerance resistors for R1 and
R2, or use a precision resistor divider network.
The gain of the EL8173 is programmed by D-Pot, U6
according to Equation 72:
R 8 + R 9 + R 10
Gain = --------------------------------------------Code
R 10 + --------------- × R g
255
150000 + 309 + 1370
Gain = -------------------------------------------------------Code
1370 + --------------- × 309
255
151.7k
Gain = -------------------------------------------------1370 + 1.2 × Code
(EQ. 72)
AN1298.2
May 27, 2009
Application Note 1298
Another complication of SPPT application is the large
temperature dependence of both total bridge resistance and
peizosensitivity (the ratio of bridge output to excitation
voltage times pressure). Bridge resistance increases with
temperature while peizosensitivity decreases. Some SPPT
designs (e.g. the Nova Sensor NPC-410 series) carefully
equalize these opposite-sign tempcos. The payoff comes
when such SPPTs are excited with constant current because
the increase with temperature of bridge resistance (and
therefore of bridge excitation voltage) then cancels the
simultaneous decrease of peizosensitivity.
Other nominal gains and gain adjustment range can be
made by changing the values of R8, R9, and R10.
Pressure Sensor Interface Circuit
Programmable Pressure Transducer Circuit
The silicon piezoresistive-bridge pressure transducer (SPPT)
is a dominant technology in automotive, industrial, medical,
and environmental pressure sensor applications. All SPPTs
share a similar architecture in which a thin (5µm to 200µm)
micro machined silicon diaphragm incorporates an implanted
piezoresistive Wheatstone-bridge strain-gauge. Applied
pressure bends the diaphragm, imbalances the strain gauge,
and thereby produces a differential output signal proportional
to the product of pressure times bridge excitation voltage.
A 10mV/psi pressure-proportional strain gauge signal is
outputted differentially on pins 2 and 4 of the sensor; this signal
is superimposed on a common mode voltage of 1.2V from the
bridge excitation voltage. The low level differential output
voltage is amplified by the EL8173 with a nominal gain set at
50. The high common mode rejection capability of the EL8173
eliminates the common mode output voltage of the bridge. The
bridge is biased from a constant current source (Q2) and two
digitally controlled potentiometers provide for zero (DPOT1)
and full scale (gain) adjustments (DPOT2).
SPPTs must be supported by appropriate signal conditioning
and calibration circuits. Finite elasticity limits the SPPT
diaphragm to relatively small deflections which generate only
±1% modulation of the bridge resistance elements and low
signal output levels, creating the need for high gain, low-noise,
temperature-stable DC amplification. The signal conditioning
circuit must also include stable, high resolution, preferably
non-interactive, zero and span trims. The automation of the
calibration of the sensor circuit is an enormous benefit in the
production environment.
In the detailed circuit shown in Figure 41, the U2b and U3
circuit provides for the precision offset adjustment, via
DPOT1, of any transducer initial null offset error. To
+5V
R3
402
R2
402
CURRENT MIRROR FOR LOW HEADROOM
FROM +5V SUPPLY
Q2
DMMT3906
BRIDGE EXCITATION, 600µA CURRENT SOURCE
U2a +5V
1/2 ISL28276
U1
+5V
IN OUT
GND
ISL60002-11
(1.200V)
Q1
2N3904
4k
4k
U2b
1/2 ISL28276
+5V DPOT VOLTAGE ALWAYS POSITIVE
R3
39.2k
DPOT1
1/2 X95820
50k, 256 TAPS
R6
20k
U3
EL8176
R4
54.9k
-5V
4k
R1
2k
Vbridge, MAX = 600µA*6k = 3.6V
R5
20k
U4
EL8173
IN+
C1
1000pF
BUFFERED
+Vbridge
Zin = Zout = 4k, TYP
(2.5k TO 6k)
3
VS+
OUT+ 2
3
OUT- 4
2
IN+
IN-
IN-
1
8
5
+5V
4
s
IN-
4k
8
VS-
7
VOUT
VOUT
0.5V/PSI
6
FB+
FB-
R8
115k
GAIN = 40 TO 60
PS1
NPC-410
0PSI TO 5PSI
(±25mV AT MAX Vbridge = 3.6V)
(±10mV AT MAX Vbridge = 1.5V)
GAIN CALIBRATION CIRCUIT
R7
1k OFFSET CALIBRATION CIRCUIT
R9
1k
DPOT2
50k, 256 TAPS
1/2 X95820
R10
1.96k
-Vbridge
FIGURE 41.
21
AN1298.2
May 27, 2009
Application Note 1298
accomplish this, the bridge excitation voltage is
programmably attenuated by DPOT1 and applied to the FB+
pin of the EL8173. The range for the zero adjustment voltage
is from +25mV to -25mV. The resolution is 200µV and is
proportional to the bridge excitation voltage, thus improving
the temperature stability of the zero adjustment.
The 10mV/psi bridge output signal is amplified by 50x to a
convenient 0.5V/psi output level with the EL8173 its
feedback and calibration network consisting of R8, R9, R10,
and DPOT2. The gain of U3 can be varied from 40 to 60 with
a resolution of 0.10.
Bridge bias is provided by the constant current circuit (U1, U2a,
and Q1) which sets a current in Q1 of 1.2 V/2k = 600µA. A
current mirror (Q2, R2, R3) reflects the output current so as to
source the 600µA into the top of a grounded bridge (PS1).
The net result of the combination of transducer and the
EL8173 circuitry is a signal conditioned precision pressure
sensor that is compatible (thanks to DPOT1 and DPOT2)
with full automation of the calibration process, is very low in
total power draw (<2mA), most of which goes to transducer
excitation and current mirror circuit.
Thermocouple Input with A/D Converter
Output
Thermocouples are the industry standard temperature
sensor for measuring a wide range of temperatures from
-250°C to + 2300°C. The four most popular thermocouple
types are shown in Table 6; however, any time two dissimilar
metals are placed in contact, a thermocouple is created via
the Seebeck Effect.
Thermocouples present several unique challenges when
interfacing them to a real world measurement system.
1. Thermocouples generate a very low output voltage that
must be amplified with a high gain amplifier. Each
thermocouple type requires a different gain when
interfacing to an A/D Converter with a fixed full scale
voltage, VFS/VoMAX.
2. Thermocouples do not generate an absolute voltage that
is proportional to temperature. Instead, they generate a
voltage that is a relative voltage that is the proportional to
the temperature difference between the “hot” end and the
“cold” end. All thermocouple tables showing output
voltage vs temperature are for the “cold” end placed in an
ice bath at 0°C. Since it is very impractical to place an ice
bath on a PCB, electronic cold junction compensation is
used. Each thermocouple type requires a cold junction
compensation rate, dVO/dT.
3. The output voltage of a thermocouple is non-linear, and is
dependant on the type of thermocouple. Linearization is
most often done with diode break-point techniques or via
microprocessor software, and is not covered in this
Application Note.
The circuit shown in Figure 42 uses the unique features of
the Intersil EL8173 Instrumentation Amplifier to simplify the
Thermocouple interface to a high resolution A/D Converter
(U5). A programmable gain digital pot (U3) and
programmable temperature sensor (U2) allows digital
selection of the four most popular thermocouple types: E, J,
K, and T.
TABLE 6. POPULAR THERMOCOUPLE TYPES
TEMPERATURE RANGE
VO at TMIN
VO at TMAX
dVO/dT 0°C to +50°C
TYPE
MINIMUM
MAXIMUM
(mV)
(mV)
(µV/°C)
E
-200°C
-328°F
+900°C
+1652°F
-8.83
68.79
61.00
J
0°C
+32°F
+750°C
+1382°F
0.00
42.30
51.70
K
-200°C
-328°F
+1250°C
+2282°F
-5.89
50.64
40.50
T
-250°C
-328°F
+350°C
+662°F
-5.60
17.82
40.70
22
AN1298.2
May 27, 2009
Application Note 1298
U1
EL8173
E, J, K, T TYPE
THERMOCOUPLE
8Hz INPUT FILTER
VS+ 7
R1
1k
(VTC)
R3
(VCJC)
1M
R2
1k
+5V
I2C
BUS
SLAVE
ADDRESS BUS
(0101000x)
5
6
3
2
1
R7
4.53k
7 RH
4
s
1.6Hz LPF
s
ISL21400
OSC1
OSC2
16
13 AVDD DVDD 15
5 RW
R5
10.7k
6 RL
COLD JUNCTION COMPENSATION
R8
1.05k
s
SCLK 1
CLOCK
(VOUT)
12 VINHI
SDIO 3
DATA I/O
R6
150.0k
11 VINLO
SDO 2
DATA OUT
+5V
8
VCC
WP-L 1
SCL 2
50k
3
SDA
SYNC 19
10 VCM
8 VRLO
6 DGND
CS 4
DRDY 5
RST 18
SYNC
CS
DATA READY
RESET
MODE 20
9 VRHI
WRITE
PROTECT
GND
4
U3
s ISL95810
I2C BUS
+5V
2 VIN VOUT
GND
U4 1 4
ISL21009-25
PROGRAMMABLE GAIN
GAIN = 30 TO 150
s
+5V
7 AVSS
-5V
14 AGND
SCL
R4
SDA
7 357k
VOUT
A0
A1
C2
10µF
A2 VSS
U2
VOUT
8 FB+
6
5 FB-
s
8
VCC
+5V
s
2 IN-
10Mhz
17
+5V
3 IN+ VS- 4
C1
10µF
Y?
U5
HI7190
6
C3
0.01µF
R9
2k
C4
10µF
s
FIGURE 42.
The programmable gain amplifier (U1, U3) provide a gain
from 30 to 150 that is programmed via the I2C bus with the
digital pot for each of the thermocouple types as shown in
Table 7.
TABLE 7. THERMOCOUPLE TYPES
TC TYPE
MAX VOUT
GAIN
D-POT
CODE10
E
68.97mV
36.34
195
J
42.30mV
59.10
094
K
50.64mV
49.37
126
T
17.82mV
140.3
000
Cold junction compensation is provided by a programmable
reference/temperature sensor (U2) and resistor divider
network R4 and R5 according to the following table with
AV = 1 and N register = 0.
TABLE 8. COLD JUNCTION COMPENSATION
TC TYPE
VCJC (µV)
M REGISTER
E
61.0
0
J
51.7
20
K
40.5
43
T
40.7
43
23
Low pass filters (R1, R2, C1) provide noise filtering with a
8Hz cut-off frequency. R3 is used for a return current path for
the EL8173 input bias current. An additional low pass filter
(R4, R5, C2) attenuates the ISL21400’s output noise voltage
with a 1.6 Hz cut-off frequency.
A high resolution (24-bit) Sigma-Delta A/D Converter,
HI7190, converts the output of the instrumentation amplifier,
EL8173, with a full scale input voltage of 2.5V set by the
ISL21009-2.5 voltage reference.
Thermocouple Input with 4mA to 20mA
Output Current
Another output option for a thermocouple input circuit is an
industry standard 4mA to 20mA current transmitter. The
theory of operation for a 4mA to 20mA current transmitter
circuit is described in Intersil Application Note AN177 with
Figures 33, 34, and 35; this theory of operation applies to the
thermocouple circuit shown in Figure 43, and therefore, will
not be repeated.
AN1298.2
May 27, 2009
Application Note 1298
+5V
J-TYPE
THERMOCOUPLE
(51.7µV/C)
U1
EL8173
8Hz INPUT FILTER
R1, 1k
R2, 1k
D2
BAT54C
+5V
PROG.
8
VCC
I2C BUS
U2
ISL21400
(VTC)
2 IN-
R3
1M
VOUT 6
(VCJC) 8
FB+
+5V
R14 R15
SCL
SDA
C1
10µF
7
VS+
3 IN+ VS- 4
R4
357k
5 FB-
VOUT 7
5 SCL
(51.7µV/C)
6 SDA
4 VSS
A0 A1 A2
R5
3 2 1
10.7k, 1%
SLAVE ADDRESS
(010100x)
RTN
PROG.
COLD JUNCTION COMPENSATION
GAIN = 58.6
U5
ISL60002BIH325Z-TK
LM2936M-5.0
U4
1 VOUT VIN 8
VOUT VIN
GND
GND
C3
C4
0.001µF
10µF
2 3 6 7
C5
4.7µF
+5V
R8
U3
Q1
499k
EL8176
IRLL014N
7
(0V TO 2.5V)
3
6
R9
2
R13
127k R10
10
80.6k
4 R12
R6
100k
57.6k, 1%
D1
B140
+Vloop
7VDC TO 30VDC
LOOP
RESISTOR
(INTERNAL "GROUND")
R11
100
R7
1k, 1%
1.6Hz LPF
CURRENT TRANSMITTER
C2
10µF
ISL21400 REGISTER VALUES
AV = 1, N = 0
J-TYPE
M = 20
VCJC = 51.7µV/C
FIGURE 43.
The circuit uses the unique features of the Intersil EL8173
Instrumentation Amplifier to simplify the Thermocouple
interface to a 4mA to 20mA Current Transmitter circuit.
Since this is circuit is shown for a single J-type
thermocouple, a fixed gain of 58.6 is used so that the output
voltage of the EL8173 is +2.5V at the maximum
thermocouple temperature. The ISL21400 programmable
voltage reference/temperature sensor is used for cold
junction compensation. Since the ISL21400 has non-volatile
storage of the register values, it can be programmed either
prior to PCB assembly or programmed via the I2C bus as
shown in this schematic. It must be cautioned that the I2C
programming “ground” is not at the same potential as the
“Internal Ground” or loop supply ground; therefore, when
programming U2, the loop supply power supply or
associated grounds must not be connected, or the I2C
programming system must be floating off ground.
Low pass filters (R1, R2, C1) provide noise filtering with a
8Hz cut-off frequency. R3 is used for a return current path for
the EL8173 input bias current. An additional low pass filter
(R4, R5, C2) attenuates the ISL21400’s output noise voltage
with a 1.6Hz cut-off frequency.
Since the 4mA to 20mA loop voltage can be as high as
24VDC, a high voltage linear voltage regulator (U5) is used
to generate an internal +5V supply.
24
RTD Input with A/D Converter Output
Another popular industry standard temperature sensor is the
RTD whose resistance varies with temperature, and is
typically specified with a nominal resistance at +25°C. For
example, a PT100 RTD has a resistance of 100Ω at 0°C.
The shape of the resistance vs temperature curve is
described by Equation 73, a second order equation, with a
unique alpha value as defined by DIN EN 60751. For a
PT100 RTD with alpha = 0.385%/ °C:
2
3
RTD = R 0 ( 1 + A∗ T + B∗ T + C∗ ( T – 100 )∗ T )
(EQ. 73)
Where: A = 3.9083 E-3, B = -5.775 E-7, C = -4.183 E-12
below 0°C and zero above 0°C.
RTDs are typically biased with 1mA to 5mA to minimize selfheating effects; this low operating current generates very low
voltage levels shown in Table 9.
TABLE 9. TYPICALLY BIAS RTD’s
TEMPERATURE
(°C)
RTD
(Ω)
VRTD @ 1mA
(mV)
-40
84.3
84.3
0
100.0
100.0
+100
138.5
138.5
+200
175.8
175.8
AN1298.2
May 27, 2009
Application Note 1298
In the circuit shown in Figure 44, RTD excitation current is
supplied by R1 and R2 operating from +5V. It would appear
that this current is not accurate enough for a high precision
temperature measurement. And, that is true except for the
trick that is played by utilizing the ratiometric mode of
operation with the A/D Converter.
Since the RTD is often operated a great distance from
receiving electronics, the use of differential voltage sensing
is used to reduce the errors generated by high mode voltage
induced noise.
The circuit in Figure 44 shows an RTD interface to a high
resolution A/D Converter using an EL8173 Instrumentation
Amplifier to differentially sense the RTD output and provide
the proper gain for the input to the A/D Converter. Ratiometric
mode operation of the A/D Converter eliminates the error
introduced by variations in the RTD excitation current.
TABLE 10.
TEMP.
(°C)
RTD
(Ω)
IEXT
(mA)
VRTD @ 1mA
(mV)
CODE
OUT10
-40
84.3
1.22
84.3
7 778 756
0
100.0
1.22
100.0
9 227 469
+100
138.5
1.21
138.5
12 780 044
+200
175.8
1.20
175.8
16 240 345
IEXT
Rw
+
VOUT
RTD
Rw
-
Rw
FIGURE 44.
R1
2k
+5V
Y1
R2
2k
Rw1
RTD
PT100
3-WIRE
U1
EL8173
VS+ 7
3 IN+
+5V
VS- 4
s
2 IN-
(VOUT)
VOUT 6
Rw2
+5V
8 FB+
R3
10k
5 FB-
Rw3
GAIN = 11
16
OSC2
13 AVDD
DVDD 15
+5V
9 VRHI
SCLK 1
CLOCK
8 VRLO
SDIO 3
DATA I/O
12 VINHI
SDO 2
DATA OUT
11 VINLO
SYNC 19
14 AGND
R4
1k
+5V
17
OSC1
10 VCM
GAIN = 11
Rw1, Rw2, Rw3 - LEAD RESISTANCE
#22 AWG WIRE - 0.0168Ω/Ft
-5V
10MHz
CS 4
DRDY 5
6 DGND
RST 18
7 AVSS
MODE 20
SYNC
CS
DATA READY
RESET
U5
HI7190
24 BIT SIGMA DELTA
A/D CONVERTER
R5
10k
R6
1k
FIGURE 45.
25
AN1298.2
May 27, 2009
Application Note 1298
A/D CONVERTER
VCC
Code = 2N*(VOUT - 0)/(IEXT*R1)
Code = 2N*Gain*IEXT*RTD/(IEXT*R1)
REFHI
Code = 2N*Gain*RTD/R1
R1
Now, the output code is only dependant on the gain of the
EL8173 and value of R1, and the variations of IEXT are
cancelled out by the ratiometric operation of the A/D
Converter.
REFLO
Iext
Also, there is an error created by the wire resistance from
the RTD leads from the RTD to the voltage sensing point.
Therefore, RTDs are often connected with 3-wire and 4-wire
lead configurations to reduce the effect of wire resistance.
By far, the most common configuration is the 3-wire
connection, and many general purpose 3-wire RTDs are
available. Three different configurations for RTD wiring are
summarized in the following.
IN+
VOUT
Rtd
IN-
IN+
IN-
EL8173
GAIN
FIGURE 46.
In the simplified circuit shown in Figure 46, IEXT = VCC/(R1 +
RTD) and VRTD = IEXT*RTD, VOUT = Gain*IEXT*RTD
For the A/D Converter, the digital output code,
N
2 × ( IN+ - IN- )
CODE = -------------------------------------------------REF HI – REF LOW
(EQ. 74)
Where N = Resolution
However, even with a 3-wire configuration, there is still an
error associated with the voltage drop caused by the wire
resistance. The RTD circuit incorporates a technique which
provides 4-wire accuracy with a 3-wire RTD, and the effect of
wire resistance is eliminated completely.
The voltage drop created by the wire resistance, Rw, is
multiplied by the same gain as the EL8173, and then the
differential input of the A/D Converter (U5) subtracts off the
effect of the wire resistance, Rw.
REFHi - REFLo = IEXT*R1
Iext
Iext
Iext
Rw
Rw
Rw
RTD
PT100
2-WIRE
VOUT
Rw
RTD
PT100
3-WIRE
VOUT
Rw
Rw
VOUT = Iext*(RTD + 2*Rw)
ERROR = Iext*2*Rw
VOUT = Iext*(RTD + Rw)
ERROR = Iext*Rw
FIGURE 47A. 2-WIRE CONNECTION
FIGURE 47B. 3-WIRE CONNECTION
RTD
PT100
4-WIRE
Rw
VOUT
Rw
Rw
VOUT = Iext*RTD
ERROR = 0
FIGURE 47C. 4-WIRE CONNECTION
FIGURE 47.
26
AN1298.2
May 27, 2009
Application Note 1298
Rs
0.005Ω
1.2V OUTPUT
10A
OUTPUT VOLTAGE
REMOTE SENSE AFTER Rs AT POINT OF LOAD
Ra
FB OR SENSE
POWER SUPPLY CIRCUIT
Rb
3.3V
R1
10k
7
R2
10k
EL8173
VS+
2 IN-
Ra AND Rb SET THE
OUTPUT VOLTAGE
3 IN+
C1
0.1µF
VOUT 6
8 FB+
C2
0.1µF
5 FBVS4
GAIN = 50
VOUT = 0V to +2.5V
0.25V/A
Rf
48.7k
Rg
1k
FIGURE 48.
Low Voltage High Side Current
Sense
Due to the rail-to-rail input stage of the EL8173, high side
current sensing is very easy to implement, as shown in
Figure 48.
This circuit is appropriate for any power supply circuit with or
without remote sense capability. The output current is
measured by a current sense resistor, Rs that is scaled for
the desired output voltage and resistor power rating. R1, R2,
C1, and C2 are a simple low pass filter to attenuate the
power supply output ripple and noise. Resistors Rf and Rg
set the gain of the EL8173 for the desired full scale output
voltage.
Rf
V OUT = I OUT × R S × 1 + ------R
(EQ. 75)
g
In this circuit, Equation 76 shows a full scale voltage of 2.5V.
1 + 48.7K
V OUT = I OUT × 0.005 × ⎛ -------------------------⎞
⎝
⎠
1K
V OUT = 0.25 × I OUT
(EQ. 76)
An accurate output voltage is obtained since remote sense is
used by connecting Ra after the sense resistor, Rs. If remote
sense is not possible, care should be exercised to minimize
the voltage drop across Rs.
The previous circuit uses an external sense resistor to
monitor the output current. If the DC/DC is a buck converter
which uses an internal controller with current mode control,
27
there is often a current sense resistor used to monitor the
inductor current. If this is the case, the output current can be
measured with that current sense resistor since the average
value of the inductor current is equal to the load current in a
buck regulator.
The circuit shown in Figure 49 is an example of using the
current sense resistor, Rs, that is already a part of the current
mode control loop to sense load current. There is a ripple
voltage across Rs that is the inductor ripple current * Rs. The
inductor ripple current is usually 30% to 50% of the load
current and is set by the switching frequency and inductor
value. This ripple voltage is essential for the current mode
control loop, but must be filtered to obtain the output load
current; this filter is performed by R1, R2, C1, and C2. Notice
that even though the input voltage of the DC/DC converter is
+12V, the common mode voltage that is applied to the
EL8173 is the output voltage; in this case, 1.2V. As long as
the output voltage is <5V, the input voltage can be much
higher.
If the inductor current is sensed by using the switching FET’s
ON resistance as a current sense element, this method is
not possible with the EL8173 circuit.
The output current can also be sensed by using the
inductor’s DCR (DC Resistance) as a current sense element
as shown in the following circuit. This example in Figure 50
shows using the EL7566, but this method applies to any
buck mode switching regulator.
AN1298.2
May 27, 2009
Application Note 1298
VIN = 12V
Q1
TG
CURRENT MODE
PWM CONTROLLER
Rs
0.005Ω
L1
1.2V OUTPUT
10A
Cout
Q2
BG
+IS
-IS
3.3V
R1
10k
7
R2
10k
EL8173
VS+
2 IN3 IN+
C2
0.1µF
C1
0.1µF
VOUT 6
8 FB+
VOUT = 0V TO +2.5V
0.25V/A
Rf
48.7k
5 FBVS4
GAIN = 50
Rg
1k
FIGURE 49.
P/O EL7566
LX
+5V
L1
COILCRAFT, DO3316P-272HC
2.7µH
DCR = 12mΩ
2.5V OUTPUT
6A
C5
150µF
EL7566 DEMO BOARD
+5V
R1
10k
R2
10k
7
VS+
EL8173
2 IN3 IN+
C1
0.1µF
C2
0.1µF
VOUT 6
VOUT = 0V to +3.0V
0.5V/A
8 FB+
5 FBVS-
Rf
40.2k
4
GAIN = 41.7
Rg
1k
FIGURE 50.
28
AN1298.2
May 27, 2009
Application Note 1298
sensing the output current. Due to the high currents, the use
of current sense resistors become very impractical due to
their low values to minimize their power dissipation. For
example, with a 50A output current, the current sense
resistor must be <400µΩ to keep the power dissipation <1W.
In addition, it is very difficult from a PCB layout viewpoint to
break a high current power plane to insert a current sense
resistor, and that forces the plane to neck-down to a very
narrow current flow path.
In the circuit shown in Figure 50, the R1 and C1 filter is
extremely important because it remove the voltage square
wave (swinging between the input voltage and ground) that
is applied to the inductor. The values for R1 and C1 should
be selected to attenuate the signal to a level that is
appropriate for the VOUT noise that is acceptable.
Since the DCR of the inductor is being used as a current sense
resistor, there are several factors which degrade the accuracy
of this approach. First, most inductors are specified for only
maximum DCR; for example, the Coilcraft DO3316P-27HC
shown above is specified for a DCR of 12mΩ, maximum. Actual
lab measurements should the DCR to be 9mΩ. Vishay offers a
product line of inductors with a specified tolerance on the
inductor DCR; for example, IHLP2525CZ-07 product family
guarantees a DCR with ±5% tolerance.
High current DC/DC converter outputs now take advantage
of advances in multi-phase DC/DC converters where a
multiple lower current DC/DC conversion stages are
connected in parallel to obtain the necessary high output
current. Rule of thumb operates each phase at 15A to 20A
so that for a 40A output current either 2- or 3-phases can be
operated in parallel.
Second, the inductor’s internal winding’s have a temperature
coefficient of +0.393%/°C (copper wire) which can be a large
error source if the inductor is allowed to get hot from ambient
temperature or self-heating due to core losses and DCR
power loss. If the error from this source is critical to the
application, a thermistor could be mounted in close proximity
to the inductor and be used to compensate the temperature
coefficient of the copper windings.
With multi-phase DC/DC converters the output current of
each phase can be measured with a current sense resistor
or DCR current sensing. The output from each current sense
circuit is summed together to get the total load current. An
additional feature of this scheme is that the current balance
of each phase can be monitored. The circuit using a
ISL28273 (dual EL8173) current sense circuit is shown in
Figure 51 for a 30A, two phase circuit.
High current (>30A) DC/DC converter outputs for
microprocessor cores present very unique challenges for
VIN = 5V
Q1
L1
0.33µH
VOUT = 1.2V AT 30A
Cout
Q2
U1
ISL28273
+5V
16
R1
10k
VS+
6 IN+A OUTA 2
R2
10k
5 IN-A
VIN = 5V
Q3
C1
0.1µF
R5
61.9k
FB-A 4
C2
0.1µF
L2
0.33µH
U2
ISL6568
F = 600kHz
L1, L2:
IHLP-2525CZ-07
±5% DCR TOLERANCE
DCR = 3.2mΩ
R9
4.99k
TOTAL Iout
Vout = 0V to +3.0V
100mV/A
R6
1k
FB+A 3
Q4
PHASE 1 Iout
Vout1
200mV/A
R3
10k
11
R4
10k
12 IN-B
C3
0.1µF
R10
4.99k
OUTB 15
IN+B
FB-B 13
C4
0.1µF
FB+B 14
R7
61.9k
PHASE 2 Iout
Vout2
200mV/A
GAIN = 62.5
R8
1k
VS8
FIGURE 51.
29
AN1298.2
May 27, 2009
Application Note 1298
The output current of each phase is measured by the DCR
of L1 and L2 as explained in the previous example. VOUT1
and VOUT2 are proportional to the output current of each
phase with a scale factor of 200mV/A. The two outputs,
VOUT1 and VOUT2, are summed together with R9 and R10 to
give a total output current, Total IOUT, with a scale factor of
100mV/A.
This basic scheme can be extended to any number of
phases for extremely high output currents exceeding 100A.
Multiplexed Low Voltage Current
Sense
In a multiple voltage computer power supply, it is often
necessary to monitor the output current from each DC/DC
converter with an A/D Converter. When the EN pin of the
ISL28271 and ISL28272 are enabled (i.e., device shutdown),
the output stage goes into a high impedance state. This
allows multiple VOUT pins to be connected together for
multiplexed output applications. Since the output stage is in
a high impedance state, only one set of feedback resistors
(Rf, Rg) are required if all the amplifiers are operating with
the same gain. Likewise, if different gains are required for
each amplifier, separate feedback resistors can be used to
set a unique gain on each amplifier.
Figure 52 demonstrates the multiplexing scheme for a power
system with four output voltages; 1.2V at 20A, 1.8V at 10A,
3.3V at 4A, and 5.0V at 7.5A.
The dual instrumentation amplifier, ISL28271, is used to
minimize parts count and circuit size. Each power supply
load current is monitored with a low value current sense
resistor (RS1, RS2, RS3, and RS4) to minimize voltage drop
across the resistor. Input protection resistors (R1 to R8) limit
the input fault current to <5mA in case of a short circuit on
the OUT connection.
30
For this application, it is assumed VOUT would be measured
with a microprocessor A/D Converter with a full scale voltage
of 2.5V. Each channel is scaled for an output voltage, VOUT,
equal to 2.0V at maximum load current to provide an
overload measurement capability of 25%.
For each amplifier,
Sensed voltage, Vs = IOUT*Rs
VOUT = Gain*Vs
VOUT = Gain*Rs*IOUT
TABLE 11. SENSED VOLTAGE
VOUT AT
MAX LOAD
CURRENT
(V)
GAIN
EN
IOUT(AMPS)
VOUT
SENSITIVITY
(V/A)
1
20
0.10
2.0
100
2
10
0.20
2.0
100
3
4.0
0.50
2.0
100
4
7.5
0.27
2.0
134
The gains of the two amplifiers of U1 are both set to 100 by a
single feedback resistor divider network, R9 and R10. The
gains of U2 are different in order to get the same VOUT
sensitivity using standard current sense resistor values.
Gain A is set to 100 by R11 and R12, and Gain B is set to 134
by R13 and R14.
The EN lines (EN1, EN2, EN3, EN4) select the desired
measurement channel.
AN1298.2
May 27, 2009
Application Note 1298
Rs1 0.001Ω
1.2V IN
1.2V OUT, 20A
Rs2 0.002Ω
1.8V IN
R1
1k
EN1
+5V
16
8
R3
1k
R2
1k
R4
1k
1.8V OUT, 10A
U1
ISL28271
7
6
5
11
12
VS+
ENA
IN+A
IN-A
IN+B
IN-B
VOUTA
VS-
ENB
FB+A
FB-A
FB+B
FB-B
VOUTB
3
4
10
14
2
VOUT
15
R9
97.6k
13
EN2
GAIN A = GAIN B = 100
R10
1.0k
Rs3 0.005Ω
3.3V IN
3.3V OUT, 4A
Rs4 0.002Ω
5.0V IN
5.0V OUT, 7.5A
R5
1k
EN3
+5V
16
8
R6
1k
R7
1k
R8
1k
U1
ISL28271
7
6
5
11
12
VS+
ENA
IN+A
IN-A
IN+B
IN-B
VOUTA
VS-
ENB
FB+A
FB-A
FB+B
FB-B
VOUTB
3
4
10
14
EN4
13
2
15
R11
97.6k
R13
133k
R12
1.0k
R14
1.0k
GAIN A = 100
GAIN B = 133.5
FIGURE 52. MEASUREMENT OF POSITIVE AND NEGATIVE CURRENT FLOW
31
AN1298.2
May 27, 2009
Application Note 1298
LOAD CURRENT = 2A, MAX
X1 AND X2 MUST BE 0V TO +5V
Rs
0.01Ω
X1
X2
R2
4.7k
R1
4.7k
+5V
U1
EL8170
+5V
7 VS+
4 VS-
D1
BAT54S
VOUT 6
2 IN-
VOUT = IOUT + 2
R3
250k
3 IN+
8
R5
100k
(20mv)
FB+
5
FBR4
1.0k
R6
1.0k
FIGURE 53. CURRENT MONITORED WITH LOW VALUE RESISTOR
Bi-Directional Current Sense
TABLE 12.
The use of the FB pins of the EL8170 make it an ideal choice
for a bi-directional current sense circuit for battery gas
gauging or current monitor in a H-bridge configuration as
shown in the following circuits.
In Figure 53, current is monitored with the use of a low value
resistor Rs. R1, R2, and D1 protect the EL8170 from
overvoltage which would be applied with excessive load
current or a short circuit on the output, X1 or X2. The
amplifier is set for a gain of 100 with R5 and R6. R4 and R5
offset the FB+ pin at 20mV to center 0A at mid-range of the
output voltage VOUT.
LOAD CURRENT (ILOAD)
VOUT
-2A
0.0V
0A
+2.0V
+2A
+4.0V
The range of the measured current can easily be changed
by proper selection of Rs, Gain and FB+ voltage.
The circuit in Figure 54 shows the EL8170 set-up as a
battery gas gauge to monitor both charging current and
discharging current.
In this circuit, when the battery is charging, the current in Rs
will be negative (i.e., flowing from X2 to X1). The EL8170
output voltage will be between 0V and +2V. When the
battery is being discharged, the current flow will be from X1
to X2, and the EL8170 output voltage will be between +2V
and +4V.
Sensed voltage is shown in Equation 77.
V S = I LOAD∗ R S
V OUT = Gain∗ ( V S + V FB+ )
V OUT = Gain∗ ( I LOAD × R S + V FB+ )
+5 × R 4
V FB+ = --------------------R4 + R5
V OUT = 100∗ ( I LOAD × 0.01 + 0.02 )
V OUT = ( I LOAD + 2 )
(EQ. 77)
32
AN1298.2
May 27, 2009
Application Note 1298
BATTERY CHARGER, POWER SUPPLY
D3
Rs
0.01Ω
SYSTEM LOAD
X2
X1
D2
+5V
BT1
R1
4.7k
LITHIUM-ION
(4.2V)
R2
4.7k
+5V
U1
EL8170
7 VS+
4 VS-
D1
BAT54S
VOUT 6
2 IN-
VOUT = IOUT + 2
R3
250k
3 IN+
FB+
FB-
R5
100k
8 (20 mv)
5
R4
1.0k
R6
1.0k
FIGURE 54. EL8170 SETUP AS A BATTERY CHARGER
If a more direct measurement for the current polarity and
increased output voltage sensitivity is required, the circuit
shown in Figure 55 can be used.
In Figure 55, U1 is used to measure positive current flow (X1
to X2) and U2 is used to measure negative current flow (X2
to X1). The polarity of the current is detected by U3 which is
being used a zero crossing detect comparator. The EN pins
of the EL8170 (U1, U2) are used to turn on the proper
amplifier depending if the current flow is positive or negative.
In the above circuit, current is monitored with the use of a
low value resistor Rs. R1, R2, and D1 protect the EL8170’s
from over-voltage which would be applied with excessive
load current or a short circuit on the output, X1 or X2. When
this bi-directional current sense circuit is used in a PWM
application such as a H-bridge, C1 and C2 can be added to
filter the PWM signal for an average current value.
Figure 56 shows the bi-directional current source circuit
configured to monitor the motor current in a H-bridge circuit.
The direction of the motor (CW, CCW) is monitored by the
polarity bit depending on the direction of current flow in the
motor. The rail-to- rail input capability of the EL8170 allows
current sensing at ground level (Q1 and Q4 ON) or at +5V
(Q3 and Q2 ON). If pulse width modulation is used to control
the speed of the motor, filter capacitors C1 and C2 should be
used to obtain the average value of the motor current. The
value of the capacitors should be selected based on the
PWM frequency and desired overall accuracy.
The amplifiers are set for a gain of 100 with R5 and R6. The
minimum sensed current is set by the EL8170 offset voltage.
V OS
I MIN = -----------RS
0.25mV
I MIN = --------------------0.01Ω
(EQ. 78)
I MIN = 25mA
33
AN1298.2
May 27, 2009
Application Note 1298
Rs
0.01Ω
X2
X1
R1
4.7k
D1
BAT54S
C1
SEE TEXT
R2
4.7k
+5V
C2
SEE TEXT +5V
U1
ISL28271
7 VS+
ENA 7
4 VS-
VOUTA 2
3 IN+
FB+A 3
2 IN-
FB-A 4
10k
+Iout AMP
+5V
U1
ISL28271
7 VS+
ENB 10
4 VS-
VOUTB 15
3 IN+
FB+B 14
2 IN-
FB-B 13
-Iout AMP
+5V
VOUT
1V/A
R3
100k
R4
1.0k
AV = 100
U2
ISL28271
7 VS+
ENA 7
4 VS-
VOUTA 2
3 IN+
FB+A 3
2 IN-
FBA- 4
+Iout
-Iout
Q1
2N7002
POLARITY DETECT
FIGURE 55. MEASUREMENT OF POSITIVE AND NEGATIVE CURRENT FLOW
34
AN1298.2
May 27, 2009
Application Note 1298
+5V
Q1
Q3
+
-
Rs
0.01Ω
MOTOR
X2
VOUT
X1
POLARITY
VOUT = Imotor
CLOCKWISE = +5V
COUNTER CLOCKWISE = 0V
EL8170 CIRCUIT
Q2
Q4
(GAIN = 100)
FIGURE 56. BI-DIRECTIONAL CURRENT SOURCE CIRCUIT
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
35
AN1298.2
May 27, 2009