AN1333: Designing Multi-Cell Li-ion Battery Packs Using the ISL9208 Analog Front End

Designing Multi-Cell Li-ion Battery Packs
Using the ISL9208 Analog Front End
Application Note
July 17, 2007
AN1333.0
Description
Battery Connection
This application note discusses some of the hardware and
software design decisions and shows how to select external
components for a multi-cell Li-ion battery pack using a
microcontroller and the ISL9208 analog front end.
The ISL9208 supports multiple series connected Li-ion cells.
The bottom three cells (CELL1, CELL2, and CELL3) and the
top cell in the string are always required. CELL4, CELL5,
and CELL6 are optional. This allows the ISL9208 to be used
in battery packs of 4- to 7-cells1. Connection guidelines for
each cell combination are shown in Figure 1.
A microcontroller provides the primary control of the
operation of the battery pack. However, several factors in the
multi-cell series Li-ion pack require the use of circuitry
around the microcontroller. They are:
7-CELLS
• The voltages involved in a multi-cell series battery pack
(up to 30V for 7-cells in series), are far higher than most
microcontrollers are rated. So, the pack needs a voltage
regulator to power the microcontroller. The microcontroller
cannot just operate on the voltage from one of the string of
Li-ion cells (typically 3.0V to 4.2V) because higher current
from only one cell will cause an imbalance in the battery
pack. This will shorten the life of the pack. A later
discussion highlights the effects of unbalanced cells and
how to rebalance the pack.
• The high voltage of the cells in the pack preclude the
microcontroller from reading the voltage on each cell as
needed to properly manage the charge and discharge
limits in each cell. So the pack needs circuits that level
shift the voltages across each cell down to a ground
referenced voltage that the microcontroller can read using
its internal analog to digital (A/D) converter.
• In order to balance the cells in the pack, the
microcontroller needs circuitry that will activate the
balancing circuit of each cell. Most of these circuits are at
a voltage too high for direct microcontroller control.
The ISL9208 meets all of these needs and supports battery
pack configurations consisting of 4- to 7-cells in series and
1-cell or more in parallel.
The ISL9208 is a very flexible device that can be used in a
variety of ways to implement the battery pack. It provides
integral overcurrent protection circuitry, short circuit
protection, an internal 3.3V voltage regulator, internal cell
balancing switches, cell voltage monitor level shifters, and
drive circuitry for external FET devices that control pack
charge and discharge. Each of these features have some
flexibility in how they are used.
VCELL7
CB7
VCELL6
CB7
VCELL6
CB6
VCELL5
CB6
VCELL5
CB5
VCELL4
CB5
VCELL4
CB4
VCELL3
CB4
VCELL3
CB3
VCELL2
CB3
VCELL2
CB2
VCELL1
CB2
VCELL1
CB1
VSS
CB1
VSS
4 -CELLS
VCELL7
VCELL7
CB7
VCELL6
CB7
VCELL6
CB6
VCELL5
CB6
VCELL5
CB5
VCELL4
CB5
VCELL4
CB4
VCELL3
CB4
VCELL3
CB3
VCELL2
CB3
VCELL2
CB2
VCELL1
CB2
VCELL1
CB1
VSS
CB1
VSS
Note: Multiple cells can be connected in parallel
FIGURE 1. BATTERY CONNECTION OPTIONS
1.
1
VCELL7
5- CELLS
• Because the microcontroller is relatively slow to respond
to high speed overcurrent events, (such as a short circuit
condition) the pack needs circuits that shut down the pack
quickly and autonomously of the microcontroller to protect
the cells and the electronics in the pack.
6-CELLS
Battery packs with 4-cells have not been tested.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Application Note 1333
If possible, when connecting the cells to the pack, provide
separate “Kelvin” connections from the cell to the VCELLN
pin. This is to minimize the change in input voltage when the
cell balance circuit turns on (see Figure 2). This connection
will reduce by half the input variation of a cell that is also
being balanced. The difference between the cell voltage
when being balanced and when not being balanced may still
be significant enough that cell measurement can only be
made when not balancing.
VCELL7
PCB
CB7
VCELL6
CB6
VCELL5
CB5
VCELL4
CB4
VCELL3
starts up. If the microcontroller has code that puts the pack
to sleep when a cell voltage is too low, then the pack could
go to sleep immediately on initial connection of these three
cells.
One way to avoid this initial power down is to connect the
cells from the top down (CELL7 to VSS). In this way, the
voltage regulator does not power up until all cells are
connected. Another way to handle this is in software, with
the code waiting a while before shutting down in response to
a low cell voltage.
The ISL9208 powers up when the voltages on VCELL1,
VCELL2, VCELL3, and VCC all exceed their POR threshold.
At this time, the ISL9208 turns on the RGO output.
RGO provides a regulated 3.3VDC voltage at the RGO pin. It
does this by using a control signal on the RGC pin to drive
an external NPN transistor. The transistor should have a
beta of at least 70 to provide ample current to the device and
external circuits and should have a VCE of greater than 30V
(preferably 50V) for a 7-cell pack.
CB3
VCELL2
VCC
C1
500
CB2
VCELL1
CB1
RGC
VSS
VSS
• VCELL7 VCELL6
VCELL6 VCELL5
VCELL5 VCELL4
VCELL4 VCELL3
VCELL3 VCELL2
VCELL2 VCELL1
• Each cell input voltage differential never exceeds the
specified limit, as shown in the ISL9208 datasheet.
When connecting the cells in sequence from bottom to top,
once cells 1, 2, and 3 are connected, the regulator may try to
turn on2. Depending on the current needed by the external
circuits, and without a VCC connection, the regulator may
not be able to maintain regulation and could turn off. There is
a possibility that this starts a turn on/turn off oscillation in the
power supply until cells are connected to the VCC pin.
If the regulator does power-up with only VCELL1, VCELL2,
and VCELL3 connected, then the microcontroller software
2
C2
GND
System Power Up/Power Down
The cells can also be connected in almost any sequence as
long as the VCELL inputs comply with the following
guidelines:
3.3V
RGO
FIGURE 2. CELL AND CELL BALANCE WIRING WITH VCELL
KELVIN CONNECTION
FIGURE 3. VOLTAGE REGULATOR CIRCUITS
A 500 resistor is recommended in the collector of the NPN
transistor to minimize initial current surge when the regulator
turns on. Without the collector resistor, the initial turn-on
current surge could be large. If there is also a relatively high
resistance on the VCC input, and if the VCC capacitor is too
small, then the initial application of power can cause the
voltage at VCC to drop momentarily. If this voltage drops
below the minimum VCC power up voltage, then the
regulator may start to turn off. As it does, the current drops
and the VCC voltage rises, again starting the regulator. This
“oscillation” prevents proper power up of the ISL9208. In a
2.
The data sheet indicates that VCC needs to be at least 9.2V
to guarantee power-up of the ISL9208. However, VCC may
only need to be 4V before power-on can happen. Because of
the internal ESD structures on the CBn inputs, (assuming
there are cell balance resistors as shown in Figure 1)
connecting CELL1, CELL2, and CELL3 may apply enough
voltage on VCC to reach the turn on threshold.
AN1333.0
July 17, 2007
Application Note 1333
normal battery pack operation, this oscillation is not likely,
because the battery-cell has a very low impedance.
parallel with a 0.01µF capacitor being connected between
VCELL1 and GND.
The 500 resistor also serves another function. It helps to
protect the Q1 transistor from excessive voltage and current
and minimizes the consequences of a failure in Q1.
For development work, or if the sequence of cell connections
cannot be guaranteed, or if there are potential voltage
excursions on the cell inputs that violate the specified 5V
maximum, the use of 4.7V zener diodes across each cell
input is recommended. These diodes protect the cell inputs
from both the maximum cell voltage and the input surge
current.
An intuitive approach to improving the power up reliability is
to increase the capacitance of C1 (see Figure 3). However,
there is a potential problem with this. If the cells are
connected in “random” order, then cell 6 and VSS could be
the first two connections. If this happens, the capacitor on
VCC is charged at high voltage through the CB7 cell balance
ESD structure and cell balancing resistor. If the capacitor is
large enough and the series resistance is small enough, the
energy dissipation in the CB7 structure as a result of the
surge current will cause a failure inside the ISL9208. Higher
cell balancing resistors prevent this, but this also limits the
effectiveness of cell balancing. See Figure 4.
The best trade-off is to use:
- a 0.01µF capacitor on VCC
- a parallel combination of 4.7µF and 0.1µF caps on
VCELL1,
- a 500 series resistor on the NPN collector, and
- 4.7V zener diodes on each cell input (unless cells
connect in sequence). See Figure 5.
VCC
C1
VCC/VC7
0.01µF
4.7V
CB7
POTENTIAL
EOS
VSS
CB7
VCELL6
VSS
4.7V
CB6
CB6
VCELL5
4.7V
CB5
NOT YET
CONNECTED
4.7V
CB4
4.7V
CB3
4.7V
CB2
CB1
4.7µF 0.1µF
4.7V
CB5
VCELL4
CB4
VCELL3
CB3
VCELL2
CB2
VCELL1
CB1
VSS
VSS
FIGURE 4. CONNECTION SEQUENCE CAUTION
Adding a series resistor on each of the cell inputs reduces
the initial current surge through the ISL9208 inputs.
However, this needs to be carefully considered, because it
effects the accuracy of the cell measurements. A series
resistance of 15 will add about 1mV of error to the cell
voltage reading. It is possible that this error can be calibrated
out, but it also requires that external cell balancing FETs be
added. For more information about this design configuration,
See “Input Filtering” on page 22.
Another condition that can effect the proper operation of the
ISL9208 is when a motor being powered by the pack turns
off. This has the potential for generating significant noise.
This noise (if it reaches the ISL9208 VCELL1 input) can
cause the loss of the ISL9208 internal register contents.
Prevent this with the use of a 4.7µF capacitor (or larger) in
3
FIGURE 5. RECOMMENDED INPUT CONNECTIONS
In addition to the VCELL1 capacitors, the microcontroller
code should periodically check the ISL9208 register contents
and reload the desired values, if they have changed.
Once powered up, the device remains in a wake up state
until put to sleep by the microcontroller or until the VCELL1,
VCELL2, VCELL3, or VCC voltages drop below their POR
threshold.
Voltage Regulator
The ISL9208 can provide 350A or more of output current to
the RGC pin. Using an NPN transistor with a gain of 100, the
ISL9208 regulator can supply up to 35mA to an external load
and maintain the output at 3.3V ±10%. A typical external
load of 3mA and a transistor gain of 100, results in the
ISL9208 supplying 30µA to the NPN transistor base.
AN1333.0
July 17, 2007
Application Note 1333
The voltage at the emitter of the NPN transistor is monitored
and regulated to 3.3V by the control signal at RGC. The
RGO voltage also powers many of the ISL9208 internal
circuits.
Following is some characterization data gathered over 30 units.
This shows the regulation accuracy at no load and at
“maximum” load of 35mA (assuming an NPN transistor with a
gain of 100). Typically, the load will be much less than the
maximum load, so the variation of RGO will be much less. But,
if the microcontroller A/D converter accuracy is dependent on
the RGO voltage, then a calibration step is likely needed to trim
the accuracy of the A/D for cell voltage measurements.
Generally, this calibration can be done once at room
temperature, because the variation over-temperature is low.
However, for measurements more accurate than ±25mV at a
cell voltage of 4.2V, a voltage reference is recommended.
RGO REGULATION OVER-TEMPERATURE/CELL VOLTAGE
(NO EXTERNAL LOAD)
3.40
RGO VOLTAGE (V)
TYP 4.3V
3.35
3.34
MIN 4.3V
3.30
MIN 2.3V
3.28
3.26
3.24
3.22
3.20
-40
25
TEMPERATURE (°C)
85
FIGURE 6. RGO VOLTAGE - NO LOAD
RGO REGULATION OVER-TEMPERATURE/CELL VOLTAGE
(350µA RGC CURRENT)
3.38
RGO VOLTAGE (V)
3.36
3.34
3.32
3.30
3.28
3.26
MAX 4.3V
TYP 4.3V
3.22
3.20
-40
MAX 2.3V
TYP 2.3V
3.24
MIN 4.3V
MIN 2.3V
25
WKUP
(STATUS)
5V
230k*
WAKE UP
CIRCUITS
CELL1
WKPOL
(CONTROL)
VSS
* Internal resistor
only connected when
WKPOL = 1.
In an active LOW connection (WKPOL bit = ’0’ - default), the
device wakes up by connecting a charger to the pack. (See
Figure 8). In this case a pack requires only two terminals
(Pack+ and Pack-). No additional terminals are needed on
the pack for wake up.
MAX 2.3V
TYP 2.3V
3.32
WKUP
FIGURE 8. WAKE UP CONTROL CIRCUITS
MAX 4.3V
3.38
ISL9208
85
TEMPERATURE (°C)
FIGURE 7. RGO VOLTAGE - 35mA LOAD (NPN GAIN = 100)
In this mode, when the pack is asleep, the FETs are off and
the WKUP pin is pulled high with a resistor external to the
ISL9208. Connecting the pack to a charger creates a voltage
divider, which pulls the WKUP pin low. When the WKUP pin
voltage goes below the WKUP threshold, the ISL9208
wakes up and turns on the 3.3V voltage regulator. (See
“Active LOW WKUP Pin Operation” on page 4 for more
details).
In an active HIGH configuration (WKPOL = ’1’), the device
wakes up when either the load or a charger is connected to
the pack, but configuration requires an extra pack terminal to
operate.
In this mode, the WKUP pin connects through a resistor and
an additional pack terminal to the PACK+ terminal outside
the pack (See Figure 10). The resistor, combined with a
resistor internal to the ISL9208, forms a resistor divider.
When a charger or load connects to the pack, the divider
pulls the voltage at the WKUP pin high and wakes up the
pack. With no tool or charger connected, the internal resistor
pulls WKUP low to prevent the pack from waking up
inadvertently. (See “Active HIGH WKUP Pin Operation” on
page 5 for more details.)
Active LOW WKUP Pin Operation
WKUP Pin Operation
Once the microcontroller puts the ISL9208 to sleep, there
are two ways to wake it up again (without power cycling the
device). One way uses the WKUP pin in an active LOW
mode. The other uses the WKUP pin in an active HIGH
mode.
4
When the ISL9208 devices use the WKUP pin in the active
LOW (default) mode, the WKUP pin threshold is normally set
such that a fully charged pack can still be waken by a
charger supplying the regulated charge voltage. For
example, for a 7-cell pack in sleep mode, the fully charged
AN1333.0
July 17, 2007
Application Note 1333
pack voltage is 29.4V. The wake up level should be set such
that a charger with a regulated 29.4V output wakes the pack.
The recommended external connection of the WKUP pin is
shown in Figure 9. The resistors needed for the
recommended wake-up threshold are calculated as follows.
R2
V WKUP2 min  -------------------  CELLmax  N
R1  R2
(EQ. 1)
where N is the number of cells in the pack, and VWKUP2min
is calculated at the maximum cell voltage.
In selecting resistors, first choose the R1 value as the
highest value that is reasonable to use, since this primarily
determines the current consumption of this circuit. Then
calculate the value for R2. The actual value of R2 chosen
should be smaller than the value calculated.
The value of the chosen R2 resistor is not too critical, since
the WKUP voltage should go well above the WKUP falling
edge threshold level when the ISL9216 is in the sleep mode
and the FETs are off. So, an R2 that is much smaller than the
calculated value would be OK, with the understanding that a
lower resistance value will draw more current. It is best to
use the largest value for R2 that does not exceed the
calculated value.
WKUP THRESHOLD (MAX) =
VCELL1 - 1.2V
R1
1.2M
voltage on the VMON pin will go well below GND without the
use of Diode D1, which is required to prevent this condition.
Diode D2 is an optional diode to prevent higher leakage
current from the cells with a load connected and the power
FETs off.
Use the following equation (for the circuit shown in Figure 9)
to determine the minimum unloaded voltage necessary from
the charger to wake a fully charged pack, using the resistors
in Figure 9.
R2 + R1
 CellV  max   N – V WKUP2 min   ------------------- = V ch arg er
R1
(EQ. 2)
where N is the number of cells in the pack.
For a 7-cell pack, the charger voltage needs to be at least
29.37V to wake a fully charged pack (Pack voltage = 29.4V).
In this active low configuration, the pack cannot detect the
presence of a load when in sleep mode. Instead, the pack
wakes up only when the charger is connected to the pack.
Active HIGH WKUP Pin Operation
When the ISL9208 uses the WKUP pin in the active HIGH
mode, the external resistor needed to select the proper
wake-up threshold is shown in Figure 9 and Equation 3 for
setting the value:
CellV  min   Numcells
V WKUP1  max 
R 1  ---------------------------------------------------------------- – 1  R
WKUP  min 
(EQ. 3)
D1
ISL9208
VCHG
WKUP
VSS
R2
68k
LOAD
D2
Assuming a 7-cell pack and a minimum cell voltage of 2.3V,
a minimum internal resistance (RWKUP) of 130k(from the
data sheet) and a WKUP threshold of 6.6V (0.1V above the
max threshold in the data sheet), Equation 4 for R1 is:
2.3  7
6.6
(EQ. 4)
R 1  ----------------- – 1  130k = 187k
P+
OFF
OFF
FIGURE 9. SETTING THE THRESHOLD FOR THE ISL9208
ACTIVE LOW WKUP PIN (WKPOL = LOW)
SWITCH CLOSED ONLY
WHEN LOAD OR CHARGER
IS CONNECTED
R1 = 187k
As shown in Figure 9, the voltage at the WKUP pin with no
charger connected, and with the power FETs on, is always
less than the WKUP threshold. When the FETs are off, as in
sleep mode, the voltage at the WKUP pin is well above the
threshold.
When the pack is asleep and the FETs are off, connecting
the pack to the charger causes the voltage on the WKUP pin
to drop below the input threshold — and the ISL9208 wakes
up.
The values are calculated with a full pack, because this is
the worst case condition. When a charger is connected to a
pack that is in sleep mode due to low voltage cells, the
5
ISL9208
WKUP
C/L
5V
230k*
VSS
30V
(OPTIONAL)
VCHG
LOAD
P* Internal resistor
only connected when
WKPOL=1.
FIGURE 10. SETTING THE THRESHOLD FOR THE ISL9208
ACTIVE HIGH WKUP PIN (WKPOL = HIGH)
AN1333.0
July 17, 2007
Application Note 1333
internal threshold settings, however an external resistor
divider can provide more flexibility in some situations (see
“Current Sense Resistor” on page 8).
CFET
DFET
CSENSE
The ISL9208 controls pack operation through one, two, or
three power FETs on the negative terminal of the pack. The
power FETs can connect in two basic different ways, a single
charge/discharge path and separate charge and discharge
paths.
VSS
Power Path Connections
DSENSE
ISL9208
DSREF
The zener diode in the circuit of Figure 10 is optional to
prevent noise spikes caused by load switching to cause
voltages on the WKUP pin that exceed the absolute
maximum VCC voltage. This will likely only occur if the
switch is closed and the microcontroller sets the WKPOL bit
to “0”.
R1
Single Charge/Discharge Path
The CFET output of the ISL9208 actively turns the charge
FET on, the same as the DFET output, but the ISL9208
relies on an external resistor to turn off the FET
(see Figure 11). This is because the charge FET VGS
voltage may go well below the ISL9208 ground voltage when
connected to a charger, preventing the ISL9208 from
supplying the voltage necessary to turn the FET off. The
selection of the charge FET resistor is determined by the
Cgs capacitance of the FET and how fast the charge FET
needs to turn off. This resistor also cannot be so small that it
clamps the FET gate voltage below the FET turn on
threshold. For example, the output current of the ISL9208
CFET pin is 80A minimum. For a FET with a Vgs of 3V, R1
needs to be at lease 37.5k or the FET may never turn on.
Figure 11 shows the two FETs being used in a single path. It
also shows a sense resistor being used for current
monitoring of both discharge and charge current. Because
the sense resistor is the same for both charge and
discharge, the ratio of the charge overcurrent limits and the
charge short circuit limits is primarily determined by the
6
DFET
CSENSE
ISL9208
DSENSE
When the ISL9208 turns off the DFET, either as a result of a
protection mechanism, or under microcontroller control, the
ISL9208 pulls the DFET gate low with a high current
(>100mA). This turns off the FET very fast.
An optional single path connection uses only the discharge
FET for pack protection. This connection assumes that the
external charger protects the cells in the pack from an over
charge condition, since the pack electronics will not be able
to stop the charge. To do this, the charger communicates
with the pack during the charge operation. During this
communication, the cell voltages are passed to the charger.
These cell voltages become part of the charger over charge
limit algorithm.
DSREF
The DFET output of the ISL9208 actively controls both the
turn on and turn off of the discharge FET. When the
microcontroller sets the DFET bit in the ISL9208, the
ISL9208 outputs a current to the gate of the DFET causing
the gate to charge up. When the gate voltage reaches the
FET turn on threshold, the FET turns on. The ISL9208
continues to output the turn on current until the voltage
reaches the VCELL3 voltage. It is clamped at this level.
FIGURE 11. BACK TO BACK POWER FETs IN SINGLE
CHARGE/DISCHARGE PATH
VSS
The most common connection of power path FETs is to use
both a charge and discharge FET in a single
charge/discharge path. In this connection, back-to-back
FETs provide both discharge and charge protection for the
pack (See Figure 11). In this way, any “out of bounds”
conditions in the pack cause the cells in the pack to be
isolated from external conditions.
Shown with parallel
discharge FETs
for higher current
applications
FIGURE 12. DISCHARGE POWER FET ONLY IN SINGLE
CHARGE/DISCHARGE PATH
The major advantages of using the single FET are:
• More of the cell voltage is applied directly to the load
resulting in less power loss in the pack.
• It is less costly to use the single FET, especially in high
current applications where it may be necessary to parallel
AN1333.0
July 17, 2007
Application Note 1333
• This configuration allows the pack to be charged, even if
the cell voltages drop too low for the ISL9208 to remain
powered.
Separate Charge/Discharge Path
Another method of connecting the power FETs is to provide
separate charge and discharge paths. This is shown in
Figure 13. In this case, the pack requires only a single
discharge FET (Q1), but requires “back-to-back” charge
FETs (Q2 and Q3). The charge path needs both FETs
because without Q2, the Q3 body diode creates a discharge
path, even if the discharge FET is off. This can present a
safety hazard for the pack.
By designing a separate charge and discharge path, the
current sense elements can be different sizes, so the
overcurrent threshold limits are better able to meet the
application requirements. Also, since the peak charge
current is usually much lower than the peak discharge
current, the size (and cost) of the charge FETs can be much
less.
Problems with this connection concern space and cost. Even
though smaller FETs can be used for the charge connection,
two FETs generally still cost more than one FET and take
more board space. This coupled with the need for an
additional pin on the pack and the possibility of having to
parallel the discharge FET, makes this a more costly, if more
flexible, solution.
Q2
The ISL9208 continually monitors the charge current and
discharge current by monitoring the voltage at the CSense
and DSense pins (respectively). If either voltage exceeds a
selected value for a time exceeding a selected delay, then
the device enters an overcurrent or short circuit protection
mode. In these modes, the device automatically turns off
both power FETs and hence prevents current from flowing
through the terminals P+ and P-.
The voltage thresholds and the response times for discharge
overcurrent, charge overcurrent, and discharge short circuit
conditions are each selected by bits in a control register. In
the default condition, the bits are generally set to the safest
state. In this condition, the FETs are off, the overcurrent and
short circuit settings are at the minimum threshold level and
the short circuit setting has the minimum time delay.
See Table 1 and Table 2 for threshold and timing options.
The power-up condition for all registers is “0”.
TABLE 1. OVERCURRENT VOLTAGE THRESHOLD
SETTINGS
REGISTER 5
Q3
R1
CHARGE
Q1
Overcurrent Protection Functions
REGISTER 6
CFET
DFET
DSENSE
CSENSE
DSREF
VSS
ISL9208
over-temperature conditions. These functions are described
in more detail, starting with current protection mechanisms.
REGISTER 5
the power FETs to achieve the necessary current handling
capability of the pack.
BIT 6
OCDV1
BIT 5
OCDV0
OVERCURRENT DISCHARGE
VOLTAGE THRESHOLD
0
0
VOCD = 0.10V
0
1
VOCD = 0.12V
1
0
VOCD = 0.14V
1
1
VOCD = 0.16V
BIT 3
SCDV1
BIT 2
SCDV0
SHORT CIRCUIT DISCHARGE
VOLTAGE THRESHOLD
0
0
VSCD = 0.20V
0
1
VSCD = 0.35V
1
0
VSCD = 0.65V
1
1
VSCD = 1.20V
BIT 6
OCCV1
BIT 5
OCCV0
OVERCURRENT CHARGE VOLTAGE
THRESHOLD
0
0
VOCD = 0.10V
0
1
VOCD = 0.12V
1
0
VOCD = 0.14V
1
1
VOCD = 0.16V
DISCHARGE
FIGURE 13. POWER FETS IN A SEPARATE
CHARGE/DISCHARGE PATH CONNECTION
Protection Functions
In the default condition, the ISL9208 automatically responds
to discharge overcurrent, discharge short circuit, charge
overcurrent, internal over-temperature and external
7
AN1333.0
July 17, 2007
Application Note 1333
REGISTER 6
REGISTER 6
REGISTER 5
TABLE 2. OVERCURRENT DELAY TIME SETTINGS
TABLE 3. SHORT CIRCUIT TO OVERCURRENT RATIOS
BIT 1
OCDT1
BIT 0
OCDT0
OVERCURRENT DISCHARGE
TIMEOUT
SETTING
0
0
tOCD = 160ms (2.5ms if DTDIV = 1)
1
1.20V
0.10V
12.0
0
1
tOCD = 320ms (5ms if DTDIV = 1)
2
1.20V
0.12V
10.0
1
0
tOCD = 640ms (10ms if DTDIV = 1)
1
1
tOCD = 1280ms (20ms if DTDIV = 1)
3
1.20V
0.14V
8.6
BIT 1
OCCT1
BIT 0
OCCT0
4
1.20V
0.16V
7.5
OVERCURRENT CHARGE TIMEOUT
5
0.65V
0.10V
6.5
0
0
tOCC = 80ms (2.5ms if CTDIV = 1)
6
0.65V
0.12V
5.4
0
1
tOCC = 160ms (5ms if CTDIV = 1)
7
0.65V
0.14V
4.6
1
0
tOCC = 320ms (10ms if CTDIV = 1)
1
1
tOCC = 640ms (20ms if CTDIV = 1)
8
0.65V
0.16V
4.1
BIT 4
SCLONG
Short
circuit long
delay
When this bit is set to ‘0’, a short circuit
needs to be in effect for 190µs before a
shutdown begins. When this bit is set to
‘1’, a short circuit needs to be in effect
for 10ms before a shutdown begins.
9
0.35V
0.10V
3.5
10
0.35V
0.12V
2.9
11
0.35V
0.14V
2.5
12
0.35V
0.16V
2.2
CTDIV
Divide
charge
time by 32
When set to “1”, the charge overcurrent
delay time is divided by 32.
When set to “0”, the charge
overcurrent delay time is divided by 1.
13
0.2V
0.10V
2.0
14
0.2V
0.12V
1.7
DTDIV
Divide
discharge
time by 64
When set to “1”, the discharge
overcurrent delay time is divided by 64.
When set to “0”, the discharge
overcurrent delay time is divided by 1.
15
0.2V
0.14V
1.4
16
0.2V
0.16V
1.3
BIT 3
BIT 2
SHORT CIRCUIT OVERCURRENT
THRESHOLD
THRESHOLD
RATIO
14.0
12.0
10.0
RATIO
After the ISL9208 detects any overcurrent condition, and
both power FETs are turned off, the ISL9208 sets a status
flag. A discharge overcurrent condition sets the DOC bit, a
charge overcurrent condition sets the COC bit, and a
discharge short circuit condition sets the DSC bit. (When the
FETs turn off, the DFET and CFET bits also reset to zero.)
8.00
6.00
4.00
Current Monitoring
The ISL9208 monitors the current by comparing the voltage
at the CSENSE or DSENSE pins relative to an internal
threshold level. An external circuit generates a voltage from
the current. Several methods are available for establishing
this current limit threshold. These include using a sense
resistor, a sense FET, and techniques for translating the FET
rDS(ON).
A battery pack with a single charge/discharge path uses the
same element to monitor the two different levels of current
encountered in an overcurrent condition and a short circuit
condition. When designing the current sense circuit, use the
setting in Table 3 to pick a setting in which the ratio between
the short circuit and overcurrent thresholds most closely
matches the desired ratio. (These ratios are shown
graphically in Figure 13.) This determines the settings for the
ISL9208 discharge thresholds.
2.00
0.00
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SC/OC SETTING
FIGURE 14. SHORT CIRCUIT TO OVERCURRENT RATIO
Current Sense Elements
CURRENT SENSE RESISTOR
Sense resistors (Figure 15) are the easiest and most flexible
method of monitoring current in the charge or discharge path
(or both). This is a relatively accurate solution, but has some
limitations. An application with high current limits will likely
require the use of high power sense resistor. These can be
expensive and will generate heat in the pack. Also, a sense
resistor can introduce significant voltage drop and power
loss to the load.
In the simplest solution a sense resistor is used for a
relatively low current application (See Example 1 on page 9).
In this solution, first select the thresholds and external sense
resistor for a pack by using Table 3 to select the closest ratio
8
AN1333.0
July 17, 2007
Application Note 1333
to the desired short circuit/overcurrent ratio. Use the settings
in the table to select the overcurrent and short circuit current
thresholds. Next, select a sense resistor that provides the
selected overcurrent threshold at the desired current limit.
From this, verify the short circuit limit..
Using the circuit of Figure 11.
15A
5A
3.0
Choose Table setting 10:
Short circuit threshold = 0.35V
Overcurrent threshold = 0.12V
2.9
Choose lowest charge O.C. threshold:
Choose sense resistor:
R
2
------------------ = 0.48
With a single charge/discharge path, there are not many
options for charge and discharge current limits, since the
same resistor is used for both charge and discharge. If the
current limits are small enough, the following external circuit
can give some flexibility to the pack design (See Figure 15.)
In this case, select the sense resistor for the lower of the
charge and discharge current limits. The sense resistor
provides the voltage for this lower limit. Then, the resistor
divider provides the other limits.
(EQ. 5)
R2 = 96k
R3 = 104k
Results:
Overcurrent threshold (charge) =
Overcurrent threshold (discharge)=
Short circuit threshold =
2A
5A
14.6A
While the technique in Example 2 provides a flexible method
of addressing the charge and discharge overcurrent
settings, it has a limitation. This method requires the use of a
larger sense resistor to provide for the use of the voltage
divider. In higher current applications this can be a
significant drawback. Consider the next example that does
not include the resistor divider, but shows the consequences
of using a sense resistor in a high current design.
Example 3: Using a sense resistor in a high current
application.
CFET
DFET
CSENSE
DSREF
DSENSE
ISL9208
VSS
2.9
R2 + R3
Overcurrent (charge) options: 4A, 4.8A, 5.6A, 6.4A.
R3
R1
FIGURE 15. USING A RESISTOR DIVIDER TO SELECT
CHARGE AND DISCHARGE OVERCURRENT
LEVELS
Desired Short Circuit Current Level:
Desired Overcurrent Level:
Ratio (SC/OC):
120A
20A
6.0
Choose Table setting 10:
Short circuit threshold = 0.65V
Overcurrent threshold = 0.1V
6.5
Pick a sense resistor of 0.1V/20A = ~0.005Ohm.
Results:
Overcurrent threshold = 20A
Short circuit threshold = 130A.
Power dissipation in resistor at 20A: 2W
(could be continuous)
Select 5W resistor to minimize heating.
Power dissipation at 120A:
(until SC shutdown)
9
0.1V
0.05
Pick a resistor divider of (2A/5A)*(0.12/0.1) = 0.48.
Select the divider resistors:
Results:
Overcurrent threshold = 4.8A
Short circuit threshold = 14A.
R1
15A
5A
2A
3.0
Determine the short circuit to overcurrent ratio:
Choose Table setting 10:
Short circuit threshold = 0.35V
Overcurrent threshold = 0.12V
Pick a sense resistor of 0.12V/5A = ~0.025.
R2
Using the circuit of Figure 15.
Desired Short Circuit Current Level:
Desired Overcurrent Level (discharge):
Desired Overcurrent (charge):
Ratio (SC/OC):
Example 1: Designing discharge current limits.
Desired Short Circuit Current Level:
Desired Overcurrent Level:
Ratio (SC/OC):
Example 2: Designing discharge and charge current
limits using a sense resistor and resistor divider.
72W
AN1333.0
July 17, 2007
Application Note 1333
SENSE FET
As shown in Figure 16, the sense resistor is replaced by a
resistor in the sense path of a special type of FET called a
sense FET. Sense FETs provide two additional pins. One of
these provides a “Kelvin” connection to the FET source to
get a low current reference path. The second connection
provides an output current proportional to the load current.
One type of sense FET provides a sense current that is
about 2600 times lower than the load current.
In dealing with relatively high current applications, the sense
FET has several advantages over a sense resistor. There is
no power loss across the sense resistor, improving the
efficiency of the pack. There is no heating of the pack due to
the sense resistor. There is more flexibility in the setting of
the overcurrent threshold because the resistor in the sense
lead is much higher resistance. Using a senseFET may be
less expensive than a sense resistor, because the additional
cost of a sense FET may be more than offset by not using a
large wattage sense resistor.
Using a senseFET allows somewhat higher power
applications to be considered. For example, using a 6Ohm
resistor in the sense lead of a sense FET above allows the
designer to set an overcurrent threshold of 45A and short
circuit threshold of 450A. These are limits that make sense
resistors somewhat impractical.
The most significant drawbacks of using a sense FET is that
there are relatively few choices of devices, they should be
matched with a non-senseFET for a “back-to-back” pair, and
they cannot be used to measure the charge current.
.
VMon
ISL9208
CFET
DSENSE
DSREF
CSENSE
DFET
B-
FIGURE 16. MEASURING CURRENT WITH A SENSE FET
FET DESATURATION
This technique uses changes in the discharge FET rDS(ON)
as the current increases to detect an overcurrent condition
and turn off the pack discharge.
As shown in Figure 17, the sense resistor is replaced by a
diode (or two diodes, in order to get the voltage at point A to
about 1V above the FET drain to source voltage) and three
resistors.
10
VMon
ISL9208
CFET
R1
50k
100
DSENSE
DSREF
CSENSE
DFET
R3
1M
A
R2
1M
B-
FIGURE 17. MEASURING CURRENT USING FET
DESATURATION
A more complete analysis of this solution is planned for
another application note, but some guidelines for designing
this circuit follow.
The value of R3 must be fairly large, because internal to the
ISL9208 is a 5k resistance from VCELL3 to the DFET pin.
If R3 is too small, the voltage at the DFET pin could drop
significantly.
The R1 and R2 series resistance also needs to be fairly
large. The recommendation is that this resistance be greater
than 1M. The reason for this is to allow for the largest
swing of voltage across the discharge FET. The maximum
voltage at point P is set by the resistor divider formed by R3
and (R1+ R2). With the values in Figure 17, the maximum
voltage at point A, with a minimum cell voltage of 2.3V, is
4.5V. With a 1.2V drop across the diode, the maximum drainsource voltage (VDS) that can be monitored is 3.3V. This can
be increased a little by reducing the diode drop.
Though not shown in Figure 17, it is also be possible to
detect a charge overcurrent condition using this circuit. By
adding a transistor and some resistors, and inverter can be
built that changes the polarity of the voltage at point A. This
can then be divided and connected to the CSense pin. This
needs to be designed so it does not load the DFET output or
affect the performance of the discharge sense circuit.
This method of overcurrent protection has a number of
advantages. First, it does not use a sense resistor in series with
the discharge path. This allows more power to be applied to the
load, instead of being burned in the sense resistor. The diode
and three resistors are also a very cost effective replacement
for an often very expensive sense resistor.
The voltage at point A can be monitored by the microcontroller
to get a representation of the pack current (both charge and
discharge). This may not be accurate enough to be used for
coulomb counting, but it is useful for detecting the presence of
charge and discharge currents. The designer can use this
knowledge to build in power management routines, create
automatic cell balance algorithms, and make decisions about
pack shutdown operations.
AN1333.0
July 17, 2007
Application Note 1333
• As the FET heats, the rDS(ON) increases, accelerating
further FET heating. This can happen even without an
increase in load current.
• When the pack is supplying a large load when the pack
capacity is low, the high current spikes could periodically
and for short durations drop the cell voltages to 2.3V (or
less). This drops the FET gate voltage to less than 6.8V. At
this lower gate voltage, the rDS(ON) increases.
If these conditions go on long enough, in a system using a
sense resistor, the FET can fail even though the current
never reached the shutdown threshold.
The main limitation of this technique is that the rDS(ON) of
the FET can vary over a relatively wide range. So, designing
this circuit will be a trade-off between protecting the internal
components and providing maximum power to the load.
Another approach to the same technique is to use a small
FET in parallel with the power FET and divide the voltage to
get an overcurrent level. This has some advantages over the
previous version, i.e. it does not load the DFET output and it
allows monitoring a higher drain to source voltage. But, it is
probably a more expensive solution and the voltage during
charge is negative, so is not useful for monitoring with the
microcontroller.
VMON
ISL9208
CFET
R1
50k
100
100
DSENSE
DSREF
CSENSE
DFET
R2
1M
B-
FIGURE 18. MEASURING CURRENT USING FET
DESATURATION (ALTERNATE APPROACH)
Overriding Automatic Overcurrent Response
An alternative method of providing the protection function, if
desired by the designer, is to turn off the individual automatic
overcurrent responses in the ISL9208. See Table 4 for
control bits that turn off the automatic control. In this case,
11
.
TABLE 4. AUTOMATIC CURRENT RESPONSE OVERRIDE
SETTINGS
BIT 7
DENOCD
Turn off
automatic
OC
discharge
control
When set to ‘0’, a discharge overcurrent
condition automatically turns off the
FETs.
When set to ‘1’, a discharge overcurrent
condition will not automatically turn off
the FETs.
In either case, this condition sets the
DOC bit, which also turns on the
TEMP3V output.
BIT 4
DENSCD
Turn off
automatic
SC
discharge
control
When set to ‘0’, a discharge short circuit
condition turns off the FETs.
When set to ‘1’, a discharge short circuit
condition will not automatically turn off
the FETs.
In either case, the condition sets the
SCD bit, which also turns on the
TEMP3V output.
BIT 7
DENOCC
Turn off
automatic
OC charge
control
When set to ‘0’, a charge overcurrent
condition automatically turns off the
FETs.
When set to ‘1’, a charge overcurrent
condition will not automatically turn off
the FETs.
In either case, this condition sets the
COC bit, which also turns on the
TEMP3V output.
REGISTER 5
• The repeated cycling of the load causing current surges
that heat the FET.
To facilitate a microcontroller response to an overcurrent
condition, especially if the microcontroller is in a low power
state, the charge overcurrent flag (COC), discharge
overcurrent flag (DOC), or short circuit flag (DSC) being set
causes the ISL9208 TEMP3V output to turn on and pull high.
(See Figure 20). This output can be used as an external
interrupt by the microcontroller to wake-up quickly to handle
the overcurrent condition.
REGISTER 5
• A long period of high current (but not overcurrent) is
applied to the load, as might be the case if a motor stalls.
the ISL9208 device still monitors the conditions and sets the
status bits, but it takes no action in overcurrent or short
circuit conditions. Safety of the pack depends, instead, on
the microcontroller to send commands to the ISL9208 to turn
off the FETs.
REGISTER 6
This overcurrent circuit is also adaptive and shuts down the
pack earlier if the FET heats up, regardless of the pack
current. This situation might occur under the following
conditions:
When an overcurrent or short circuit condition occurs and
the delay time elapsed, the DSC, DOC, or COC bits are set
in the Status register (addr: 01H).
One way to use these status bits is to design the system
such that the microcontroller is in a sleep state to conserve
power. It uses both a timer and the TEMP3V input as
interrupt sources. The microcontroller periodically wakes up
to monitor the cells and goes back to sleep. In an
“emergency” overcurrent condition, the microcontroller
wakes up in response to the TEMP3V interrupt and turns off
the FETs.
In practice, when any of the three overcurrent status bits are
set, the TEMP3V output turns on and does two things:
1. This turns on the ISL9208 external over-temperature
monitor circuit. (There is no harm in turning this on too
AN1333.0
July 17, 2007
Application Note 1333
often, except that the circuit consumes about 400A of
current until TEMP3V turns off).
2. If the microcontroller is in a sleep mode, TEMP3V wakes
up the microcontroller by applying a voltage to the
interrupt. When the microcontroller services the interrupt,
it reads the status register to determine if there was an
overcurrent or short circuit condition. Reading the status
register resets the status bits, which turns off the
TEMP3V output.
If the microcontroller is not in the sleep mode the
microcontroller can disable the TEMP3V interrupt, so that a
TEMP3V input does not disrupt other code, or it can leave
the interrupt on to provide the microcontroller a hardware
response to an overcurrent condition. If the interrupt is left
on, then reading the external temperature with the AO3:AO0
bits also causes an interrupt to the microcontroller. But a
simple scan of the status register indicates whether this was
an overcurrent condition, or a normal temperature scan.
Load Monitoring
Once the power FETs turn off as a result of an overcurrent
condition, they are not automatically turned back on by the
ISL9208. They are turned on again by the external
microcontroller. The micro can turn on the FETs right away,
but if the load or short circuit is still present, there will be a
big current surge through the FETs. If this turn-off and turnon oscillation is not controlled, then the FETs can heat and
possibly fail. So, before the microcontroller turns on the
power FETs after an overcurrent condition, it is best to check
to see if the load has been removed before turning the FETs
on again.
DISCHARGE LOAD MONITORING
For pack discharge conditions, the ISL9208 provides a
mechanism for detecting the removal of the load from the
pack following an overcurrent or short circuit condition. This
is called the load monitor and uses the VMON pin on the
ISL9208.
The load monitor function is normally not active to minimize
current consumption. To use it, the circuit must be activated
by the microcontroller. It works by internally connecting the
VMON pin to VSS through a current sink. This internal sink
and the external load form a voltage divider with the VMON
pin reflecting the divided voltage. The VMON pin is
compared to an internal reference. If VMON is above the
reference, then the pack load is still present. If the voltage at
VMON is below the threshold, then the load has been
released enough to allow the power FETs to be turned on
again. The circuit operates shown as in Figure 19.
In operation, when an overcurrent or short circuit event
happens, the discharge and charge FETs turn off. At this
time, the RL resistance is small and the load monitor is off.
As such, the voltage at VMON rises to nearly the pack
voltage.
12
Once the power FETs turn off, the microcontroller activates
the load monitor by setting the LDMONEN bit. This turns on
a FET that activates the current sink in the load monitor
circuit. While still in the overload condition, the combination
of the load resistor, an external adjustment resistor (R1), and
the internal current sink form a voltage divider. R1 is chosen
so that when the load is released to a sufficient level, the
LDFAIL condition resets. For the ISL9208, the value of R1
can be zero.
Diode D4 is optional and prevents the voltage at the VMON
pin from going negative when the charger is connected. The
pin is rated at VSS - 22V, but if there is concern about the
pin, the diode will protect VMON, while not affecting the
performance of the circuit.
.
P+
VSS
SENSE
OPEN
RESISTOR
RL
OPEN
PDFET
CFET
R1
VMON
ISL9208
VREF
LDFAIL
=1 if VMON > VVMON
=0 if VMON VVMON-VVMONH
IVMON
D4
30V
LDMONEN
VSS
VSS
FIGURE 19. LOAD MONITOR CIRCUIT
Load Monitor Example:
Removing an overcurrent or short circuit condition results in
the value of RL increasing. To determine where the load
monitor always detects the release of the load and to set the
value of R1, use Equation 6:
 CellV  Numcells  – V VMON  min 
R L + R 1  --------------------------------------------------------------------------------------------------I VMON  max 
(EQ. 6)
For a 7-cell pack, the minimum combined resistance at a
pack voltage of 29.4V (ISL9208: 7-cells) is:[
29.4 – 1.1V
R L + R 1  ------------------------------ = 471.7k
60A
(EQ. 7)
At a depleted pack voltage of 2.5V per cell, P+ is 17.5V and
the RL+ R1 resistance is 273k. So, in this case, if R1 is set
to 250k, the load resistance must exceed 23k to recover
from an overcurrent when the pack is depleted, and exceed
210k when the pack is fully charged.
AN1333.0
July 17, 2007
Application Note 1333
At the opposite extreme, for a fully charged pack (based on
ISL9208 parameter variations):
 CellV  Numcells  – V VMONH  min 
R L + R 1  ------------------------------------------------------------------------------------------------------I VMON  min 
(EQ. 8)
[
29.4 – 1.1V
R L + R 1 = ------------------------------ = 1.42M
20A
(EQ. 9)
The RL+R1 for a fully depleted pack 820k. These values
are summarized in the table below.
TABLE 5. RL+R1 MIN OVERCURRENT RECOVERY
RESISTANCE
FULLY
CHARGED PACK
FULLY
DEPLETED
PACK
Max VMON current
472k
273k
Min VMON current
1.42M
820k
RL + R1
* At the minimum VMON threshold voltage
CHARGE LOAD MONITORING
The ISL9208 load monitor circuit does not provide detection
of charger removal after a charge overcurrent condition,
because it is likely that the voltage on the charger will be
higher than the pack voltage and the VMON pin would be
negative.
In the event that the pack FETs turn off due to an overcurrent
condition during charge, the microcontroller will need to use
a timing based procedure for turning the FETs on again. The
recommended procedure for responding to a charge
overcurrent is to wait for a period of time, then turn the FETs
on again. This delay time is dependent on the choice of
FETs and its power handling capabilities. The time should be
set long enough for the FET to cool off.
After the FET turns back on, if another charge overcurrent
happens within a fixed time period, then the microcontroller
might decide to wait much longer before turning the FETs on
or it might keep the FETs off (effectively disabling the pack).
Repetitive overcurrent conditions during charge could
indicate a pack failure, charger failure, or the use of the
wrong pack/charger combination. The specific algorithm
requirements are up to the pack/system designer.
Over-Temperature Safety Functions
EXTERNAL TEMPERATURE MONITORING
The external temperature is monitored by using a voltage
divider consisting of a fixed resistor and a thermistor. This
divider is powered by the ISL9208 TEMP3V output. This
output is normally controlled so it is on for only short periods
to minimize current consumption.
Without microcontroller intervention, the ISL9208
continuously turns on TEMP3V output (and the external
13
temperature monitor) for 4ms every 512ms. In this way, the
external temperature is monitored even if the microcontroller
is asleep. If the ATMPOFF bit is set, this automatic
temperature scan is turned off.
The TEMP3V pin turns on when the microcontroller sets the
AO3:AO0 bits to select that the external temperature voltage
be placed AO. As long as the AO3:AO0 bits point to the
external temperature the TEMP3V output remains on.
The microcontroller can over-ride both the automatic
temperature scan or the microcontroller controlled
temperature scan by setting the TEMP3ON configuration bit.
This turns the TEMP3V output on all the time to keep the
temperature control voltage on indefinitely. This will
consume a significant amount of current, so it is likely this
feature would be used for special or test purposes.
When the TEMP3V output is on, the external temperature
voltage is compared with an internal voltage divider that is
set to TEMP3V/13. When the voltage is below this threshold
for more than 1ms, the external temperature fail condition
exists.
To set the external over-temperature limit, determine the
resistance of the desired thermistor at the temperature limit.
Then, select a fixed resistor that is 12x that value.
Example 4: Selecting the resistor/thermistor for external
over-temperature limit.
Selected Thermistor:
MuRata XH series
Desired Over-Temperature Limit:
+55°C
Thermistor resistance at limit:
3.54k
Calculate RX value (see Figure 20):
3.54k*12 = 42.48k
Pick an RX resistor:
42.2k
Results:
Calculated temperature threshold: 42.2k/12 = 3.517V
Temperature limit (MuRata table look up): +55.17°C
PROTECTION
When the ISL9208 detects an internal or external
over-temperature condition, the FETs are turned off, the cell
balancing function is disabled, and the IOT bit or XOT bit
(respectively) is set.
While in an over-temperature condition, the ISL9208
prevents cell balancing and the power FETs are held off.
This continues until the temperature drops back below the
temperature recovery threshold. During a temperature
shutdown, the microcontroller can monitor the internal
temperature through the analog output pin (AO), but any
writes to the CFET bit, DFET bit, or cell balancing bits are
ignored.
The automatic response for the ISL9208 was chosen to
prevent damage to the IC, the cells, and the pack. If the
internal temperature reaches the internal temperature limit, it
AN1333.0
July 17, 2007
Application Note 1333
uses its internal A/D converter to monitor the AO voltage.
See Figure 21.
4ms
ATMPOFF
TMP3ON
SCL
SDA
ISL9208
CHARGE OC
DISCHARGE OC
DISCHARGE SC
OSC
OVERCURRENT
PROTECTION CIRCUITS
508ms
I2C
REGISTERS
I2C
I2C
DECODE
To
µC
EXT TEMP
AO
2
MUX
12R
TEMP3V
AO
RX
XOT
LEVEL
SHIFT
VCELL2
LEVEL
SHIFT
VCELL1
VSS
EXT TEMP.
TEMPI
(ISL9208/ISL9216
ONLY)
R
INT
TEMP
VSS
TEMP FAIL
INDICATOR
FIGURE 20. EXTERNAL TEMPERATURE MONITORING AND
CONTROL
is most likely due to heating from cell balancing, perhaps as
a result of a faulty microcontroller or runaway code. Keeping
the cell balance resistors on when the ISL9208 internal
temperature is above the threshold temperature is not
advised.
If the ISL9208 detects the external temperature reaching its
limit, it is possible that the cells are over heating due to a fast
charge or discharge. The external temperature protection
circuit turns the power FETs off to prevent further heating,
which can lead to thermal runaway in some cells. Turning off
the cell balance also limits the discharge from the cells to
minimize heating.
If this automatic response is not desired, the microcontroller
can prevent an automatic shutdown of the power FETs and
cell balancing operation after either an internal or external
over-temperature detect by setting the DISITSD bit to “1”
(internal temperature) or the DISXTSD bit to “1” (external
temperature). In either of these cases, the IOT and XOT bits
continue to be set, to indicate an over-temperature condition,
but it is up to the microcontroller to detect the condition and
respond.
Analog Multiplexer Selection
The ISL9208 individually provides battery cell voltages and
temperatures on the AO pin. Using the I2C interface, the
microcontroller selects the voltage to be monitored, then
14
VCELL6
MUX
TEMPI
1ms
DELAY
EXTERNAL
TEMP
MONITOR
LEVEL
SHIFT
AO3:AO0
DECODE
VSS (ON)
VC7/VCC
REGS
RGO
AO3:AO0
LEVEL
SHIFT
FIGURE 21. ANALOG OUTPUT MONITORING DIAGRAM
The output of the AO pin is sensitive to noise in the system,
but the ability to filter the output is minimal. First, a resistor in
series with the AO pin and the A/D input can result in a
voltage drop, if the input impedance of the A/D converter is
low. Second, the ISL9208 AO amplifier does not handle
large capacitance loads very well.
There are two ways to approach this. First, the use of a 
A/D converter provides some inherent filtering, so the noise
showing up on AO is inconsequential. If using a successive
approximation A/D, then an RC filter may be required. For
this filter, the recommendation is a series resistor of 500
and a filter capacitor of 1000pF.
Using a 500 resistor in series with the NXP (formerly
Freescale) microcontroller A/D input results in a voltage drop
of 0.5mV at an AO voltage of 1.75V. The RC combination
reduces the noise significantly and has little ringing.
However, the AO output does have a longer settling period
after a large jump in the AO voltage, so a delay of 10s is
recommended between changing the AO output and
sampling with the A/D converter. This is usually shorter than
the time required to terminate the I2C communication that
selects the AO source, so usually no extra code or delay
timing is required.
Voltage Monitoring
Since the voltage on each of the Li-ion Cells are normally
higher than the regulated supply voltage, the ISL9208 both
level shifts and divides the voltage from the cells. To get into
the voltage range required by the external A/D converter, the
voltage level shifter divides the cell voltage by 2. Therefore,
AN1333.0
July 17, 2007
Application Note 1333
a Li-ion cell with a voltage of 4.2V is reported via the AO pin
to be 2.1V.
Then, the graph shows the minimum, typical, and maximum
errors over the 30 units.
The variation in the cell voltage from cell to cell is typically
less than the variation from device to device. The variation of
any cell voltage over the voltage range of the cells is less
than the variation of the cell to cell voltage, and the variation
of the output of any one cell over-temperature is even less.
As such, the addition of a calibration step when testing the
PCB can significantly improve the performance of the
design. Below are characterization data showing the
accuracy of the ISL9208. The following data was taken over
30 units.
This gives the minimum and maximum variation of error for
any one device.
20.00
15.00
ERROR (mV)
10.00
(EQ.10)
15.00
MAX (-40°C)
10.00
MAX (+85°C)
MAX (+25°C)
0.000
MIN (-40°C)
MIN (+25°C)
-15.00
25.00
CELL1 CELL2 CELL3 CELL4 CELL5 CELL6 CELL7
MAX (-40°C)
ERROR (mV)
MAX (+85°C)
15.00
MAX (+25°C)
5.000
0.000
-5.000
MIN (+25°C)
MIN (-40°C)
-20.00
-20.00
MIN
CELL1 CELL2 CELL3 CELL4 CELL5 CELL6 CELL7
For Figure 26, it is assumed that the error at room
temperature and 4.2V per cell for each device is zero. Then
the error for the cell inputs on each device at 2.3V were
compared with the error on the same cell at 4.3V, according
to Equation 12:
Error = ErrorCell N  2.3V  – ErrorCell N  4.2V 
(EQ.12)
The chart then shows the minimum and maximum errors
over the 30 units.
-10.00
-15.00
TYP
-5.000
FIGURE 25. TYPICAL, MINIMUM, AND MAXIMUM ANALOG
OUTPUT ERROR FOR 30 UNITS AT CELL
VOLTAGES OF 4.3V, RELATIVE TO CELL 3
20.00
10.00
0.000
-15.00
MIN (+85°C)
FIGURE 22. MIN/MAX ANALOG OUTPUT ERROR FOR
30 UNITS AT CELL VOLTAGES OF 2.3V
30.00
MAX
5.000
-10.00
-10.00
-20.00
CELL1 CELL2 CELL3 CELL4 CELL5 CELL6 CELL7
20.00
10.00
-5.000
MIN
FIGURE 24. TYPICAL, MINIMUM, AND MAXIMUM ANALOG
OUTPUT ERROR FOR 30 UNITS AT CELL
VOLTAGES OF 2.3V, RELATIVE TO CELL 3
15.00
5.000
-5.000
-20.00
ERROR (mV)
ERROR (mV)
20.00
TYP
-15.00
30.00
25.00
0.000
-10.00
Figure 22 and Figure 23 show absolute error with the results
of each cell compared to the input voltage. The data shows
the minimum and maximum extremes of error for each cell.
These figures show the device to device variation.
Error =  CellVoltage –  AO  2   – CellVoltage
MAX
5.000
MAX (+85°C)
CELL1 CELL2 CELL3 CELL4 CELL5 CELL6 CELL7
FIGURE 23. MIN/MAX ANALOG OUTPUT ERROR FOR
30 UNITS AT CELL VOLTAGES OF 4.3V
For Figure 24 and Figure 25, the error for the cells on each
device was compared with the error on cell3 of that same
device according to Equation 11:
Error = ErrorCell N – ErrorCell 3
15
(EQ.11)
AN1333.0
July 17, 2007
Application Note 1333
5
CELL4 MAX
CELL3 MAX
10
CELL6 MAX
CELL5 MAX
CELL7 MAX
5
CELL2 MAX
CELL1 MAX
CELL2 MIN
CELL1 MIN
-5
ERROR (mV)
ERROR (mV)
0
CELL6 MIN
CELL7 MIN
CELL5 MIN
-10
2.3
CELL VOLTAGE (V)
4.3
CELL5 MIN
CELL4 MIN
CELL3 MIN
CELL6 MIN CELL7 MIN
Error = ErrorCell N  (Hot,Cold)  – ErrorCell N  Room 
(EQ.13)
Then, the graph shows the minimum and maximum errors
over the 30 units at two different cell voltages.
CELL1 MAX
CELL2 MAX
CELL6 MAX
CELL4 MAX
CELL5 MAX
CELL7 MAX CELL3 MAX
0
CELL7 MIN
CELL3 MIN
CELL4 MIN
CELL6 MIN
CELL5 MIN
CELL2 MIN
-10
-40
25
25
TEMPERATURE (°C)
85
FIGURE 28. MINIMUM AND MAXIMUM ANALOG OUTPUT
ERROR FOR 30 UNITS AT CELL VOLTAGES OF
4.3V RELATIVE TO +25°C
For Figure 27 and Figure 28, the error for the cells on each
device at hot and cold were compared with the error on
same device at room temperature, according to the
Equation 13:
-5 CELL1 MIN
0
-10
-40
FIGURE 26. MINIMUM AND MAXIMUM ANALOG OUTPUT
ERROR FOR 30 UNITS AT CELL VOLTAGES
FROM 2.3V, RELATIVE TO 4.3V
5
CELL7 MAX
CELL3 MAX
CELL2 MIN
CELL4 MIN
10
CELL6 MAX
CELL4 MAX
CELL5 MAX
-5 CELL1 MIN
CELL3 MIN
-15
ERROR (mV)
CELL1 MAX
CELL2 MAX
85
TEMPERATURE (°C)
FIGURE 27. MINIMUM AND MAXIMUM ANALOG OUTPUT
ERROR FOR 30 UNITS AT CELL VOLTAGES OF
2.3V, RELATIVE TO +25°C
Because the accuracy of the ISL9208 is better when looking
at each device (rather than assuming all devices are the
same) and because the variation of the voltage
measurement is less over voltage and temperature, the
performance of the ISL9208 can be improved by performing
a calibration at room temperature when the board is
assembled.
A calibration procedure might consist of the following steps:
3. Power the board and program the microcontroller with
standard pack code, using the microcontroller internal
Flash and a download interface. Next, power down the
board, so on re-start the pack code is operational.
4. Power up again with a known voltage of 4.200V on every
cell input (room temperature is OK). This powers the
board and starts the microcontroller. The downloaded
microcontroller code runs normally, and assumes that
there are no errors in the cell voltage readings. However,
the code includes a calibration mode that is activated
through a debugger or a dedicated pin.
5. Use the debugger or pin to start the calibration mode.
Inside the microcontroller, the code successively selects
each cell input and compares the cell voltage reading
with the expected 4.20V input. Any differences are
temporarily stored in separate locations in RAM. Since
there is a difference between readings at 4.2V and 2.3V,
it is more important to calibrate at 4.2V, since accuracy is
more critical when the cells are fully charged.
6. After all cell voltages are read, the code writes the offset
values to Flash and uses these calibration values in
future scans of the cells.
The process of powering up the board, programming it, and
calibrating the inputs should take less than 15s. Most of this
time is taken up by the initial download of the microcontroller
code and this process can be completed before connection
of the board to the battery cells.
16
AN1333.0
July 17, 2007
Application Note 1333
Temperature Monitoring
The voltage representing the external temperature applied at
the TEMPI terminal is directed to the AO terminal through a
MUX, as selected by the AO control bits (see Figures 20 and
21.) The external temperature voltage is not divided by 2 as
are the cell voltages. Instead it is a direct reflection of the
external temperature voltage divider. The microcontroller
takes this monitored voltage and typically converts it to a
temperature using a table. To get resolution of less than
+5°C, there typically needs to be some interpolation
between table set points. See some sample code in
Figure 29.
A similar hardware operation occurs when monitoring the
internal temperature through the AO output, except there is
no external “calibration” of the voltage associated with the
internal temperature. For internal temperature monitoring,
the voltage at the output is linear with respect to temperature
and has a slope and offset. (See Operating Specifications for
information about the output voltage at +25°C and the output
slope relative to temperature.) Based on the data sheet, an
equation that translates internal temperature in volts to
internal temperature in °C is:
AO IntTemp – 1.31
IntTemp C = --------------------------------------------------- + 25
– 0.0035
(EQ.14)
Cell Balancing
Overview
A typical ISL9208 Li-ion battery pack consists of four to
seven cells in series, with one or more cells in parallel. This
combination gives both the voltage and power necessary for
power tool, e-bikes, electric wheel chairs, portable medical
equipment, and battery powered industrial applications.
While the series/parallel combination of Li-ion cells is
common, the configuration is not as efficient as it could be,
because any capacity mismatch between series-connected
cells reduces the overall pack capacity. This mismatch is
greater as the number of series cells and the load current
increase. Cell balancing techniques increase the capacity,
and the operating time, of Li-ion battery packs.
There are two kinds of mismatch in the pack, State-ofCharge (SOC) and capacity/energy (C/E)3 mismatch, with
SOC mismatch being more common. Each problem limits
the pack capacity (mAh) to the capacity of the weakest cell.
It is important to recognize that the cell mismatch results
3.
In SOC mismatch, the cells all have the same inherent
capacity, but through charge and discharge inefficiencies,
they have arrived at a condition where the state of charge
are different cell to cell. In C/E mismatch, the cells begin
with different inherent capacities. In this type of mismatch,
an imbalance between cells is inherent in the pack, even if
there are no charge/discharge inefficiencies. Because
Li-ion manufacturing is improving, the C/E mismatch is less
common.
17
more from limitations in process control and inspection than
from variations inherent in the Lithium Ion chemistry.
The use of cell balancing can improve the performance of
series connected Li-ion Cells by addressing both State-ofCharge and Capacity/Energy issues. SOC mismatch can be
remedied by balancing the cell during an initial conditioning
period and subsequently only during the charge phase. C/E
mismatch remedies are more difficult to implement and
harder to measure and require balancing during both charge
and discharge periods.
Definition of Cell Balancing
Cell balancing is defined as the application of differential
currents to individual cells (or combinations of cells) in a
series string. Normally, of course, cells in a series string
receive identical currents. A battery pack requires additional
components and circuitry to achieve cell balancing. For the
ISL9208, the only external components required are
balancing resistors.
Battery pack cells are balanced when all the cells in the
battery pack meet two conditions.
1. If all cells have the same capacity, then they are balanced
when they have the same relative State of Charge (SOC.)
In this case, the Open Circuit Voltage (OCV) is a good
measure of the SOC. If, in an out of balance pack, all cells
can be differentially charged to full capacity (balanced),
then they will subsequently cycle normally without any
additional adjustments. This is mostly a one shot fix.
2. If the cells have different capacities, they are also
considered balanced when the SOC is the same. But,
since SOC is a relative measure, the absolute amount of
capacity for each cell is different. To keep the cells with
different capacities at the same SOC, cell balancing must
provide differential amounts of current to cells in the
series string during both charge and discharge on every
cycle.
In an unbalanced battery pack, during charging, one or more
cells will reach the maximum charge level before the rest of
the cells in the series string. During discharge the cells that
are not fully charged will be depleted before the other cells in
the string, causing early undervoltage shutdown of the pack.
These early charge and discharge limits reduce the usable
charge in the battery.
Manufactured cell capacities are usually matched within 3%.
If less than optimal Li-ion cells are introduced in to a series
string pack or cells have been on the shelf for a long period
prior to pack assembly, a 150mV difference at full charge is
possible. This could result in a 13% to 18% reduction in
battery pack capacity.
AN1333.0
July 17, 2007
Application Note 1333
/***************************************************************************************************
This function converts voltage from the AO output to external temperature. It uses a table lookup
based on the muRata NCP03XH103J05RL thermistor */
short calculate_externaltemp(short voltage)
unsigned short Rtable[22]={
1963, 1768, 1577, 1393, 1219, 1061, 918, 793, 682, 585, 501, 429, 368, 316, 271, 233, 201, 174, 151,
131, 114, 100
char i,j;
short temperature;
short temp1, temp2;
for(i=0;i<22;i++){
if(scan_control.ISL9208Temp[0] > Rtable[i])
break;
temperature = (-20+i*5);
/* use the following formula to interpolate values inside a 5degree grid
temperature = (-20+i*5) + ((scan_control.ISL9208Temp[0]-Rtable[i]) * -5)/(Rtable[i-1]-Rtable[i]);
*/
temp1 = scan_control.ISL9208Temp[0]-Rtable[i];
temp1 = 5*temp1;
temp2 = Rtable[i-1]-Rtable[i];
for(j=0;j<5;j++){
if(temp1<(j+1)*temp2)
break;
temperature += (4-j);
return temperature;
FIGURE 29. SAMPLE CODE FOR CONVERTING EXTERNAL TEMP VOLTAGE TO °C
Soft-shorts
Soft-shorts are the primary cause of cell imbalance in Li-ion
cells. Due to tiny imperfections in cell construction the cell
can have very high resistance shorts on the order of
40,000 or more. The self discharge rate due to this higher
resistance is on the order of 0.1mA or 3% per month. Most
cells do not have this condition and can hold much of their
capacity for years. Some cells which meet specifications
when they leave the factory may sometimes exhibit this
condition later. This is strictly an electromechanical
condition. Used in a single cell pack, this cell can just be
recharged and shows no capacity loss. But, in a series pack,
a cell with soft sorts could lose 3% per month, while another
cell loses none at all. See Example 5.
Cell Balance Operation
When choosing components for the cell balancing circuit,
care is needed in the selection of the external current limiting
18
resistor to keep the currents within reasonable limits. If
balancing current is too high, power dissipation can be
considerable - both internal to the IC and externally in the
limiting resistor. The result can be battery pack heating or
component stress. If balancing current is too low, balancing
takes too long or requires too many charge/discharge cycles
to return a benefit. The result is ineffective or non-existent
cell balancing.
The microcontroller manages cell balancing by setting a bit
in the Cell Balance Register. Each bit in the register
corresponds to one cell’s balancing control. With the bit set,
an internal cell balancing FET turns on. This shorts an
external resistor across the specified cell. The maximum
current that can be drawn from (or bypassed around) the cell
is 200mA, based on the ISL9208 limits. This current is set by
selecting the value of the external resistor. Figure 30 shows
an example with a 200mA (maximum) balancing current.
AN1333.0
July 17, 2007
Application Note 1333
21
1W
ISL9208
CB7
MUST ASSUME ZERO rDS(ON)
FOR MAX CURRENT
CALCULATION
200mA
7 6 5 4 3 2 1
VCELL1
CELL2 (UNBALANCED)
100
CELL1 (UNBALANCED)
80
60
40
20
0
CB1
e
rg
ha
sc
Di
s
th
on
3M
ge
ar
Ch ge
r
ha
sc
Di
s
th
on
3m
ge
ar
Ch rge
ha
sc
Di hs
t
on
3M
ge
ar
Ch rge
ha
sc
Di
ge
ar
Ch hs
t
on
t
ar
3M
St
21
1W
CELL
BALANCE
REG
STATE OF CHARGE (%)
120
VC7/VCC
CONDITION
FIGURE 31. WITHOUT CELL BALANCING
VSS
Example 5: Cell balancing benefits.
Results without balancing:
At 3 months: Cell1=31% SOC, Cell2 = 40% SOC
After charge cycle: Cell1 = 91% SOC, Cell2 = 100%SOC
After discharge cycle: Cell1 = 0% SOC, Cell2 = 9% SOC
3 month pack capacity loss = 9%.
12 month pack capacity loss = 36%. A pack that had a 3
hour run time when new, lasts only 1.9 hours after one
year
Results with balancing:
At 3 months: Cell1 = 31% SOC, Cell2 = 40% SOC
After charge cycle: Cell1 = 100% SOC, Cell2 = 100%SOC
After discharge cycle: Cell1 = 0% SOC, Cell2 =0% SOC
3 month pack capacity loss = 0%.
12 month pack capacity loss = 0%, with only minor,
recoverable, loss if not used for a long period.
CELL2 (BALANCED)
CELL1 (BALANCED)
80
60
40
20
0
e
rg
ha
sc
Di h s
t
on
3M
ge
ar
Ch ge
r
ha
sc
Di
s
th
on
3m
ge
ar
Ch rge
ha
sc
Di h s
t
on
3M
ge
ar
Ch rge
ha
sc
Di
ge
ar
Ch h s
nt
Compare the pack performance with and without
balancing:
100
o
3M
t
ar
St
Assume a 2 cell pack.
Assume cell 1 discharges 3%/month.
Assume cell 2 has negligible discharge.
Assume the cells start at the same 40% state of charge
(SOC)
Assume the pack remains on the shelf for 3 months
between charging, then it is charged, discharged and
charged again before again being placed on the shelf.
STATE OF CHARGE (%)
120
FIGURE 30. CELL BALANCING CONTROL EXAMPLE WITH
100mA BALANCING CURRENT
CONDITION
FIGURE 32. WITH CELL BALANCING
To program a balancing current of 200mA, start with a cell
voltage of 4.2V and assume an internal resistance of 0.
This internal resistance is a ideal minimum rDS(ON). It will be
non-zero, but to keep the maximum current at 200mA per
cell, start by assuming this zero internal resistance. This
balancing condition calls for an external resistor of 21. With
this value resistor, the external resistor dissipates 0.84W and
the power dissipation inside the ISL9208 is zero. The
external resistor should be sized to handle this power
dissipation. (Ideally, to minimize heating, the goal is to use a
4W or greater resistor, but more realistically, because of
board space and cost, the choice would be the use of a 2W
resistor.)
Next, to make sure the device does not dissipate too much
power through the internal FET, assume an external resistor
of 21W and an internal FET resistance of 7. This gives a
balancing current of 150mA (4.2V/28). The external resistor
in this case dissipates 0.55W and the IC FET dissipates
158mW. The ISL9208 package has a power dissipation limit
of 400mW. So, because of the heat generated internally from
this aggressive balancing, there should be a software limit to
balance only one or two cells at a time.
With lower balancing current, more balancing FETs can be
turned on at once, without exceeding the device power
dissipation limits or generating excessive balancing current.
A reasonable compromise between aggressive balancing
19
AN1333.0
July 17, 2007
Application Note 1333
and power dissipation is a balancing current of about
100mA. A 42/2W cell balancing resistor sets this maximum
balancing current and has a maximum power dissipation of
420mW. The internal balancing FET has a maximum
dissipation of 70mW, allowing four to five cell balancing FETs
to be on at the same time.
The above calculations are for maximum cell voltages. But,
as the cell voltage drops, the overall power dissipation also
drops.
The ISL9208 supports battery packs with multiple cells in
parallel. With more than 2 cells in parallel, however, cell
balancing becomes more difficult due to the higher pack
capacities. At these higher capacities, the maximum 200mA
balancing current limits the rate of balancing. To deal with
this, an external P-Channel FET can be used to provide
higher currents. Figure 33 shows an example of such a
circuit. In this case it is even more important to separate the
voltage monitoring and cell balancing paths to get accurate
readings of the cell voltage while cell balancing is on. This
connection of cell balancing components completely isolates
the cell balancing from the cell monitoring, so in this case
monitoring and balancing can be performed simultaneously.
VCELL7
50k
10
CB7
VCELL6
50k
10
CB6
VCELL5
50k
CB5
VCELL4
10
50k
10
CB4
VCELL3
50k
10
CB3
VCELL2
50k
CB2
10
VCELL1
50k
CB1
10
VSS
FIGURE 33. HIGH CURRENT CELL BALANCING CIRCUIT
Another design consideration is to choose an external Pchannel FET with a gate turn on voltage below the minimum
cell voltage that balancing will take place. For example, if the
20
cells will be balanced down to 2.5V, then the FET turn on
voltage needs to be less than 2.5V. The circuit of Figure 33
provides up to 400mA of balancing current. This requires the
use of 5W balancing resistors and 1W cell balancing
transistors.
Cell Balance Control Algorithm
Designing the software for cell balancing can become quite
difficult as there are several limitations that should be
considered and several difficult obstacles to overcome.
Some of the design elements of a cell balancing algorithm
are listed below:
1. Maximum voltage differential between cells. If the
difference between the cells is too great, it could indicate
that there is a bad cell. In this case, the decision by the
microcontroller code might be to shut down the pack.
2. Minimum voltage differential between cells. If the cell
voltage differential is too small, then it could be said the
cells are already balanced. The decision about what
voltage differential is too small is primarily based on the
accuracy of the voltage measurement system. If the error
in the measurement system is greater than the minimum
cell balance differential, then a cell could be balanced
that did not need to be, and the cell imbalance can
increase.
3. Temperature limits on balancing. It is usually desirable
to refrain from balancing when the cells are too hot or too
cold. When cells are too hot, balancing them could
increase the temperature of the cells. When cells are too
cold charging should be restricted, limiting the
opportunities for balancing.
4. Maximum and minimum voltage on the individual
cells being balanced. This is not usually a problem and
cells can be balanced all the way from the under charge
level to the over charge level. However, if the balancing
operation affects the cell measurement, then operating
the cell balancing algorithm at the capacity extremes may
cause significant changes in the observed cell voltage,
leading to pack shut down or resulting in the attempted
balance of cells that do not need balancing. Also, as the
cell voltages near their maximum, it is necessary to keep
a close watch on the voltage, to avoid over charging the
cells. It may not be possible to balance at the same time
as closely monitor the cells near the over charge limit.
5. Balancing on time vs off time. Ideally, there would not
need to be a balancing on and off time. However, without
using external balancing FETs, any significant balancing
current will affect the voltage at the ISL9208 VCELLN pin
when the balancing is turned on. Adding a separate
“Kelvin” connection from the terminal of the cell to the
VCELLN pin (see Figure 2 and Figure 33), minimizing
resistance in the cell to board connection, and balancing
with less current all reduce the voltage measurement
error. But, in general, the cell balance circuit must turn off
periodically for the microcontroller to get a good reading
of the cell voltages for managing the over charge and
under charge condition of the cells as well as to
determine the continuing need for cell balancing.
AN1333.0
July 17, 2007
Application Note 1333
6. Maximum number of cells balanced at a time. As
mentioned earlier, the total number of cells balanced at
any one time may be limited by the package power
dissipation levels. This needs to be comprehended in the
algorithm.
7. Balancing order. The algorithm normally sorts the cell
voltages in order from high to low. Then, if the difference
between any higher voltage cell and the minimum voltage
cell exceeds the minimum balancing differential, then that
cell balance FET is turned on. The algorithm starts by
turning on the highest voltage cell, then the next highest,
and so on until the maximum number of balanced cells is
reached or no additional cells have a high enough voltage
differential.
8. Balance during charge or discharge or both.
Balancing cells during discharge conditions is not
common. In this case charge from the pack is “burned” in
the balancing resistors during a period where maximum
energy is required. Balancing during discharge reduces
the pack capacity in the short term. It could be that this
short term loss results in a long term gain, if the cells can
be balanced quickly, but it is not obvious that this is the
case.
Balancing cells during the charge condition is the more
common technique, since there is energy available from
the charger to replenish that lost through the cell
balance resistors. By balancing during charge, it is
necessary to increase the charge current slightly to keep
the overall charge time from increasing.
The best method of implementing cell balancing during
charge is to include a communication path between the
pack microcontroller and the charger. This
communication path allows the charger to monitor
individual cell voltages, but it also allows the charger to
let the pack know that a charger is present so balancing
can commence.
Without a charger communication path, in a two terminal
pack for example, the microcontroller code inside the
pack needs to detect the presence of a charging current
or use the pack voltage and cell voltages to determine if
a charger is connected or not. This is not a trivial
solution.
A modification of the FET desaturation current circuit in
Figure 17 could be used to provide the microcontroller
an indication of charge current. In this case, the
microcontroller would monitor the voltage at point A.
When this voltage drops significantly from the voltage
when there is no current, then the microcontroller
concludes that a charge is in progress.
Without this hardware indication, the pack can use an
instantaneous change in the pack voltage to detect that
a charger is connected. This instantaneous change can
be several hundred millivolts when the charger
connects. However, this change in pack voltage can be
indistinguishable from the change in pack voltage
caused by the instantaneous drop in the load current.
21
The pack can use an average dV/dt of the pack voltage
to determine if the pack is charging or discharging. A
pack being discharged generates a negative dV/dt; a
pack being charged creates a positive value. However,
in this case the pack voltage needs to be filtered to avoid
noise in the measurements and to smooth out short term
variations in the load. The dV/dt value also needs to be
averaged over a period of time, because in the middle of
the cell voltage range there can be a lot of capacity
change with very little corresponding voltage change. In
this case, cell balancing could automatically stop if the
dV/dt detection returns a zero charge rate.
Pack Communications
If it is important to communicate with the pack
microcontroller from the outside world, the easiest method is
with a two wire interface such as the SMBus or I2C bus.
Most microcontrollers have one of these interfaces
implemented in hardware. Alternatively, a one-wire interface
could be developed, using microcontroller code.
Another design consideration for communication is that the
microcontroller is ground referenced at the same point as
the ISL9208. When the power FETs are off, this ground
reference is different from the PACK-point. So,
communication between the pack and outside are only
possible in the following conditions:
1. The power FETs are on. In this case, the PACK- terminal
is roughly the same potential as the microcontroller
ground.
2. The 2-wire external communication connector also
provides the microcontroller ground voltage, so it is not
necessary that the power FETs be on. CAUTION: In this
case, the unit communicating with the pack cannot also
use the PACK- terminal as a ground connection. The
PACK- terminal should be floating. Otherwise, when the
power FETs turn off, either an unsafe voltage differential
occurs between the microcontroller ground and the
PACK- pin, potentially damaging the microcontroller, or
the monitoring device provides a discharge path around
the power FETs. Neither condition is desired.
Keep in mind also that a PC (for monitoring) and a power
supply (for charging) may have their grounds connected
together through their chassis and the AC power
connection. The same is true if a scope is connected to
the board. This may not be obvious. So using both of
these units in the second configuration may require extra
attention.
If monitoring of the pack is desired in production, then option
2 is normally sufficient. If a charger needs to communicate
with the pack, then option 1 is required and the pack
microcontroller needs to turn on the power FETs before
communication is possible. Then, if the pack shuts down
because of an over charge condition, the over charge
condition must be resolved before communication is reestablished.
AN1333.0
July 17, 2007
Application Note 1333
50k
VCELL7
10
0.1µ
10
50k
1k
CB7
VCELL6
0.1µ
10
50k
1k
0.1µ
CB5
VCELL4
10
50k
1k
50k
1k
ISL9208
CB6
VCELL5
0.1µ
10
CB4
VCELL3
0.1µ
10
50k
1k
CB3
VCELL2
0.1µ
CB2
10
50k
10
1k
0.1µ
VCELL1
4.7µ
CB1
VSS
FIGURE 34. SIMPLIFIED DIAGRAM OF INPUT FILTER/EXTERNAL BALANCING FETS
Other Hardware Design Ideas
The following design ideas are proposed implementations
and have not been thoroughly tested and will likely require
additional software control.
Input Filtering
In some applications it is required that the cell inputs be
filtered before being monitored by the ISL9208. As
mentioned earlier, this will add an offset error to the
monitored input voltage. However, if the microcontroller can
perform a calibration on initial assembly and can store this
value in non-volatile memory, then it is possible to add filters
to the inputs.
Adding a series resistance to each input, as part of the input
filter, has one other negative. It adds resistance to the cell
balance path. This both reduces the available cell balance
current and creates an even larger measurement error when
the cells are being balanced. As such, this design option
requires the addition of external P-Channel FETs for
balancing. These extra FETs add some cost to the system,
but will allow higher balancing current.
22
The combined input filter and external cell balancing input
are shown in Figure 34. In this case, the 1k resistors add
about 120mV error to the readings for cell2 through cell6
(depending on the input), about 60mV error on cell1 input,
and about 6mV error on cell7.
This error on the inputs is due to a current that flows when
sampling the cell voltage. The current varies cell to cell, but it
is consistent for any specific cell input.
The cell7 input poses a more difficult problem, because the
error varies according to the current consumption of the
ISL9208 device. However, if the series resistor is kept small,
then there will likely be very little variation in the current
consumption (for any specific device) at the time when a
measurement is being made.
There is one additional advantage to this input connection.
That is, the ISL9208 is protected against input surge
currents, so it is possible to connect the cells to the PCB in
any sequence.
AN1333.0
July 17, 2007
Application Note 1333
Positive Edge Wake-up Variations
When used in a power tool application, the positive edge
wake up might be used to power down the pack when it is
removed from the tool or the charger.
Positive edge wake up might also be used such that the
WKUP pin is connected directly to the power tool switch so
the pack is always asleep until the switch is pulled. In this
case, care should be taken with the microcontroller software
so the code wakes up quickly enough that there is no
perceived lag on the trigger pull. This connection will also
cause the FETs to turn on during a condition of maximum
current.
a mismatch between resistors R1 and R2 each translates to
a gain error at the microcontroller.
These 14-cell design ideas have not been implemented and
are presented here for purposes of discussion only.
Battery Pack Software
There are many things to consider when writing the software
for a battery pack controller. Please see the “ISL9208,
ISL9216 Microcode reference guide” for more detailed
information about battery pack code implementation.
In some other applications, the WKUP pin could be
connected to a system control signal. In this case, the pack
is powered down when not needed, for example when the
unit is taken off-line. Then, when the unit is again placed in
service, a signal can be sent to the battery pack to wake it
up. This provides maximum life of the battery when the
system does not require battery operation.
Packs With More Than 7-Series Connected Cells
For applications that require more than 7-series connected
cells, look at the ISL9216, ISL9217 chip set. These two
devices cascade and work together to support packs of 8- to
12-series connected cells. For more than 12-series
connected cells, it will be necessary to cascade autonomous
battery modules using level shifting or optical isolation.
Consider a pack with 14-series connected cells. There are
two possible approaches to this pack. In the first, two
ISL9208 devices are cascaded (See Figure 35). Each of
these support 7-cells and each has a microcontroller
managing the module operation. The microcontroller for the
lower ISL9208 also includes communication with the upper
module through level shifting circuitry. In this case, the level
shifter is implemented with several FETs. This technique
could be used with multiple cascaded ISL9208s, but there is
a limit due to voltage ratings of the FETs. The level shifter
could be replaced with an optical isolator for virtually
unlimited cascading.
In a second method of implementing a 14-cell series
connected pack, an ISL9208 is used with an ISL9217 and
only one microcontroller (See Figure 36). The ISL9217 was
selected in this case, because it has a “split” I2C interface
with an SDAOUT and an SDAIN. This is easier to handle
when level shifting than a bidirectional port. The ISL9217
also does not include the FET control functions which are
not needed on the upper cascaded devices. This circuit also
shows a mechanism for level shifting the analog output of
the ISL9217 to a ground reference so it can be monitored by
the ISL9208 microcontroller.
The AO level shifter has three main sources for error. The op
amp offset error translates to an offset error at the
microcontroller analog input. A current mirror mismatch and
23
AN1333.0
July 17, 2007
Application Note 1333
ISL9208
VCELL7
CB7
VCELL6
CB6
VCELL5
RGO
CB5
VCELL4
5k
CB4
VCELL3
CB3
VCELL2
CB2
VCELL1
5k
20k
20k
SDA IN
SDA
SCL
AO
CB1
VSS
µC
A0
SDA Out
SCL
50k
50k
ISL9208
VCELL7
CB7
VCELL6
GND
RGO
5k
CB6
VCELL5
PHILLIPS Tx Rx
P82B96
CB5
VCELL4
Sx
50k
20k
CB4
VCELL3
CB3
VCELL2
CB2
VCELL1
SDA
SCL
µC
SCL
SDA
AO
A0
CB1
VSS
Shown with two parallel cells.
GND
FIGURE 35. USING TWO ISL9208 DEVICES TO IMPLEMENT A 14-CELL SERIES CONNECTED PACK
24
AN1333.0
July 17, 2007
Application Note 1333
ISL9217
VCELL7
CB7
VCELL6
CURRENT MIRROR MISMATCH ERROR
TRANSLATES TO A1 GAIN ERROR
RGO
CB6
VCELL5
CB5
VCELL4
CB4
VCELL3
CB3
VCELL2
CB2
VCELL1
OP AMP
OFFSET ERROR
TRANSLATES TO
A1 OFFSET ERROR
5k
5k
20k
20k
SDA IN
SDA Out
SCL
AO
50k
CB1
VSS
50k
R1
ISL9208
VCELL7
GND
RGO
CB7
VCELL6
CB6
VCELL5
CB5
VCELL4
5k
PHILLIPS Tx Rx
P82B96
Sx
50k
20k
GND
CB4
VCELL3
SDA
CB3
VCELL2 SCL
µC
A1
A0
CB2
AO
VCELL1
CB1
VSS
R2
SCL
SDA
R1 = R2. ANY MISMATCH ERROR
TRANSLATES TO A1 GAIN ERROR
SHOWN WITH TWO PARALLEL CELLS
FIGURE 36. USING AN ISL9208 AND ISL9217 TO IMPLEMENT A 14-CELL SERIES CONNECTED PACK
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
25
AN1333.0
July 17, 2007
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