White LED Driver Circuits for Off-Line Applications using Standard PWM Controllers ® Application Note February 12, 2009 AN1387.0 Introduction The LED Ballast As high-efficiency ultra-bright white LEDs come down in cost, they are approaching cost parity with conventional mercury vapour, HID quartz metal halide and high/low pressure sodium lighting on a cost per lumen basis. They are becoming viable replacements in industrial and commercial lighting applications. However, there are significant differences between conventional lighting sources and LEDs in terms of voltage and current operating requirements. In particular, LEDs require a constant current source from a low DC voltage source, but they must also operate from the AC mains. Just as conventional lighting sources require a ballast, LED lighting sources have an analogous circuit. This Application Note discusses techniques for powering LEDs directly from the AC mains, not only to develop the requisite voltage and current, but also to deliver power from the AC mains with near unity power factor while using off-the-shelf constant frequency PWM controllers. The major difference in the control circuitry between a conventional DC/DC converter and the LED ballast is that the output current, rather than the output voltage, is the controlled parameter. Fortunately, there are many power supply topologies suitable for this application. Virtually any topology having a series inductor is suitable. This would include Boost, Buck-Boost, SEPIC, CUK, and Flyback converters, to name a few. The only requirements being that the inductor current must reduce to zero during a portion of the switching cycle, i.e., the converter must operate in either discontinuous conduction mode (DCM) or critical conduction mode (CrCM), and the converter must be operated with a constant On-Time control. The reason for the restrictions is to achieve unity power factor from the AC mains. When operated as described, the peak (and average) inductor current will track the input voltage waveform. The input current will be sinusoidal and in-phase with the AC input voltage. Requirements To achieve light intensity comparable to conventional commercial and industrial lighting, multiple LEDs must be used. The LEDs may be connected in parallel or series, or a combination of both. Depending on the light intensity required, the number of required LEDs could range from a few to hundreds. Each LED may require, depending on its characteristics, between 300mA and 1000mA of DC current at 3V to 4V to provide up to 175 lumens of light output1. A typical high pressure sodium street lamp bulb consumes 150W and produces about 15,000 lumens2. Using presently available LEDs, an equivalent intensity LED “bulb” would require up to 150 LEDs and consume somewhat more power. We desire a simple low cost power supply (LED ballast) that converts the AC mains input to a constant current DC source. Furthermore, the power must be delivered from the source with near unity power factor*. From Faraday’s Law and the definition of inductance, we have Equation 1: V =L di dt (EQ. 1) Since the switching period of the converter is very short compared to the AC line frequency, we can assume the voltage applied to the inductor is constant during a single switching cycle. If V and L are constant, then ΔI and ΔT may be substituted for di and dt, respectively. Furthermore, since this is a constant On-Time control law, TON may be substituted for ΔT. Rearranging and solving for ΔI yields Equation 2: ΔI = V • L T ON (EQ. 2) Since TON and L are constant, ΔI varies in proportion to the applied voltage, V. The AC input voltage is applied to the inductor, and as it varies, ΔI varies in proportion. Since the converter is operated in either DCM or CRCM, the inductor current always starts each switching cycle at zero current. Therefore, ΔI is the peak inductor current. Each switching cycle of the converter generates a triangular inductor current waveform that conforms to the envelope of the rectified AC input voltage waveform. *.Power factor is the ratio of real power to apparent power (W/VxA, where W = watts, V = RMS voltage, A = RMS current). Unity power factor implies that the load has no reactive (inductive or capacitive) component and appears purely resistive. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1387 FIGURE 1. RECTIFIED AC VOLTAGE AND INPUT CURRENT WAVEFORMS Figure 1 depicts the input voltage and current waveforms for a converter operating in DCM with constant On-Time control. The switching frequency of the converter has been reduced to 2kHz to illustrate the input current waveform on a time scale appropriate for viewing both waveforms simultaneously. One consequence to achieving near unity power factor is the energy delivered from the AC mains is not constant, but varies with the sinusoidal AC input voltage. The LED load, however, requires a constant DC current and voltage. Some LED driver solutions address this problem by using a second DC/DC converter to regulate the current. This is entirely unnecessary. A single stage converter is fully capable of meeting the requirements. The only penalty is a small amount of rectified line frequency ripple on the output voltage of the converter, the magnitude of which is inversely proportional to the value of output capacitance. This topic will be further discussed later. We have established that the converter must be operated using a constant On-Time control law, but how is the current through the LEDs regulated to achieve the desired intensity and/or color temperature? The answer is the On-time is not truly constant. If the On-time is modulated slowly, the On-time over an AC half-cycle will be virtually constant, but can still be slowly changed over time to regulate the current through the LEDs. This requires that the LED current control loop have a bandwidth significantly less than the frequency of the rectified AC input, or about 20Hz to 30Hz. Three of the many converter topologies suitable for LED driver applications will be discussed in detail. The methods discussed are easily adapted to other topologies as the actual control circuitry is not topology dependent. One control circuit can be used for all single stage LED driver topologies. 2 The Boost Converter The simplest LED ballast is based on a conventional boost converter, depicted in Figure 2. L AC CIN D Q COUT RS PWM CONTROLLER FIGURE 2. BOOST CONVERTER LED BALLAST The boost converter is useful for driving a large series string of LEDs. The only requirement being that the voltage applied to the LEDs must be higher than the peak of the AC input voltage. A boost converter cannot produce an output voltage lower than its input. For example, if the input voltage is the nominal 120VAC common in North America, it has an operating range of 90VAC to 140VAC and a maximum peak voltage of 198V (√2*140). The LED string must have a sufficient quantity of LEDs in series such that the voltage drop across the string is greater than the peak voltage of 198V. A typical forward voltage drop for a white LED is 3.5V, suggesting a minimum string of 58 LEDs. Once variation of forward voltage drop with temperature and other factors is taken into account, the actual quantity of LEDs required may be somewhat higher. If too few LEDs are used, the converter will not be able to regulate the LED current. The critical components of the boost converter are the inductor, L, the primary power switch, Q, the rectifier D, and AN1387.0 February 12, 2009 Application Note 1387 the output capacitor, COUT. Each of these components must be selected for the current and voltage stress experienced in the application. The inductor must be selected for both peak current and RMS current rating to avoid saturation and excessive power dissipation. The voltage and current waveforms for a boost converter operating in DCM are illustrated in Figure 3. TON = 0 VOLTAGE V IN 2TsI OUT L VOUT − V IN TOFF 1 = VIN VL VOUT - VIN TOFF1 TOFF2 L< Ts FIGURE 3. BOOST WAVEFORMS The switching period Ts is divided into three subintervals known as TON, TOFF1, and TOFF2. TON is the time period that switch Q is conducting, also known as the On-time. TOFF1 is the time period during which the inductor current ramps down to zero after switch Q is turned off, and TOFF2 is the remainder of the switching period where the inductor current is zero. VIN ⋅ TON VOUT − VIN 2 2(VOUT − VIN )TsI OUT L (EQ. 3) where VOUT is the output voltage, VIN is the peak input voltage, Ts is the switching period, IOUT is the output current, and L is the boost inductor value. Equation 3 assumes the inductor current remains discontinuous (DCM operation). The power switch, Q, and diode, D, are treated as ideal elements. The RMS current through the inductor can be calculated from Equations 4 through 6. Irms = 2 π Ipk (EQ. 7) Ts (VOUT − VIN ) VIN2 2 2 I OUT VOUT TON + TOFF 1 3Ts (EQ. 4) The RMS current through switch Q is shown in Equation 9: I Q ( RMS ) = 2 π Ipk TON 3Ts (EQ. 9) The factor of 2/π averages the RMS value over a complete AC half-cycle. The voltage ratings of the power switch, Q, diode D, and output capacitor, COUT, must be at least as high as the converter output voltage plus allowance for transients and design margin. The peak currents through Q and D are the same as was obtained for the inductor. The average current through diode D is the output current IOUT. The ripple current rating for COUT is an involved calculation. There is a high frequency component at the switching frequency, a low frequency component at the rectified AC frequency, and a DC component due to the load. An estimate may be calculated using Equation 10. I RMS ( COUT ) 3 (EQ. 8) The value of inductance determined by Equation 8 is the maximum allowed inductance and must be calculated using the minimum output voltage, the maximum instantaneous input voltage, and maximum output current over a complete AC half-cycle. The peak inductor current can be estimated from Equation 3. π (EQ. 6) The inductor value must be correctly sized so that the converter remains in DCM operation over all operating conditions. This criteria can be met provided the combined duration of TON and TOFF1 are less than the switching period, Ts. Summing Equations 5 and 6 and setting the result to be less than Ts yields Equation 8. 0 Ipk = (EQ. 5) and: TOFF 1' = TON 2TsI OUT L(VOUT − V IN ) where VIN is the average rectified input voltage. Equations 5 and 6 represent the average values of TON and TOFF1, respectively. While TON is essentially constant during an AC half-cycle, TOFF1 will vary considerably over the same time period. The instantaneous value of TOFF1, TOFF1’, may be calculated from Equation 7. IL CURRENT where: ⎞ 2 TOFF 1 ⎛ ΔI L2 ⎜⎜ ≈ − I OUT ΔI L ⎟⎟ + I OUT TS ⎝ 3 ⎠ (EQ. 10) AN1387.0 February 12, 2009 Application Note 1387 where: ΔI L = VIN V − VIN TON = OUT TOFF 1 L L Evaluating ΔIL at the maximum instantaneous input voltage will result in a conservative estimate of the ripple current. Evaluating ΔIL at the average or RMS input voltage will somewhat underestimate the ripple current. The input capacitor, CIN, must be sufficiently small so that it tracks the (unfiltered) rectified AC voltage. It must completely charged and discharged in-phase with the rectified AC input during each half-cycle. If this requirement is not met, the input current waveform will be distorted and power factor quality will be compromised. The boost topology provides better power factor performance when operated in critical conduction mode (CrCM) rather than discontinuous conduction mode. Since the inductor current ramps from Ipk to zero in proportion to the difference between the input voltage and the output voltage, the average inductor current does not track the input voltage as well. This behavior becomes obvious if the output voltage is nearly equal to the peak of the AC input voltage. The inductor current ramps down more slowly as the instantaneous difference between the input and output voltage decreases. As the output voltage is further increased above the peak input voltage, the distortion is reduced. Figure 4 shows this effect. Operating in CrCM eliminates the distortion because there is no TOFF2 period. NORMALIZED RECTIFIED INPUT CURRENT L1 (EQ. 11) 1.0 C1 D1 L2 AC CIN COUT Q1 RS PWM CONTROLLER FIGURE 5. SEPIC CONVERTER LED BALLAST The SEPIC converter is more complicated than the boost converter, and therefore requires some discussion of its operation. Referring to Figure 5, components L1 and L2 cannot have a steady state DC voltage impressed across them, or saturation would occur. Therefore, the average voltage across each inductor must be zero. This result implies the voltage across C1 must be equal to the rectified AC input, VIN. Likewise, the DC current through C1 must be zero for steady state operation. Since the DC current though C1 must be zero, the output current, IOUT, can only result from current flowing in L2. Therefore, the average current through L2 must be equal to the output current, IOUT. Therefore: V L1 = 0 VDC (EQ. 12) V L 2 = 0 VDC (EQ. 13) I C1 = 0 ADC (EQ. 14) V C1 = VIN VDC (EQ. 15) IDEAL 0.8 0.6 0.4 0.2 VOUT = 190VDC VOUT = 250VDC 0 0 1 2 3 4 5 6 7 TIME (RADIANS) FIGURE 4. RECTIFIED INPUT CURRENT vs VIN AND VOUT. VIN = 120VRMS The SEPIC Converter The SEPIC converter is a more general purpose LED driver than the boost converter, as it can produce output voltages lower, equal to, or greater than the input voltage. Figure 5 shows the SEPIC converter. It requires more components and has a higher material cost than the boost converter. The SEPIC converter is capable of driving LED loads from just a few to very many LEDs, limited only by the voltage rating of the components. 4 In DCM operation, there are three time periods in each switching cycle designated as TON, TOFF1, and TOFF2 corresponding to the state of the inductor currents. In the SEPIC topology, the inductors are considered to be discontinuous when the sum of their currents is zero rather than when either inductor has zero current. This occurs when the voltages across the inductors collapse to zero. During TON, the switch, Q1, is closed and the inductor currents ramp linearly to Ipk. (Ipk will be different for L1 and L2 unless they have equal inductance.) TOFF1 starts when switch Q1 opens and the inductor currents decrease in magnitude. TOFF2 begins when the inductor currents sum to zero and ends when the next switching cycle begins. AN1387.0 February 12, 2009 Application Note 1387 Since the VIN is applied across L1 and L2 for the same period of time, each inductor experiences the same flux-linkage (volt-second) change. CURRENT IL1 IL2 D1 C1 IL1+IL2 L1 t 0 IL1 VIN L2 VL1, VL2 CIN t 0 IOUT IL2 COUT Q1 LOAD VIN VOLTAGE + VIN - -VOUT TOFF1 TON TOFF2 FIGURE 8. SEPIC CONVERTER DURING TOFF1 Ts During TOFF1, the voltage across each inductor is: FIGURE 6. CURRENT WAVEFORMS FOR L1 AND L2 (L2 > L1) During TON, the main switch is closed. The input voltage, VIN, is applied across L1. Since C1 has a steady state voltage equal to VIN, L2 also has VIN applied across it during TON. Diode, D1, is reversed biased and blocking. The load current, IOUT, is entirely supplied by the output capacitor COUT. + VIN L1 C1 IL1 I L2 L2 CIN IOUT COUT Q1 LOAD VIN D1 VL1(TOFF 1 ) = VOUT − VIN + VC1 = VOUT (EQ. 18) V L 2 (TOFF 1 ) = VOUT (EQ. 19) VOUT appears across both inductors during TOFF1 so their flux-linkage (volt-second) change is again equal. Since the flux-linkage (volt-second) change for both inductors is identical during both TON and TOFF1, the inductor currents will ramp and decay at the same rate and become discontinuous at the same time. Although the inductor currents may not be zero during TOFF2, there is no inductor current flowing to the output. IOUT is supplied entirely by COUT. As noted earlier, the output current IOUT, is equal to the average current in inductor, L2. However, since current only flows to the output during TOFF1, the output current is also the sum of the average inductor currents during TOFF1. The output current, IOUT, can be expressed as Equation 20: FIGURE 7. SEPIC CONVERTER DURING TON It should be noted that C1 is sufficiently large that the AC currents through it produce a negligible voltage change and the voltage across it remains essentially equal to VIN. During TON, when Q1 is conducting, both inductors have VIN applied to them. ΔI L1 1 TON V L1(TON ) = L V L 2(TON ) = L2 ΔI L 2 TON = V IN (EQ. 16) = VIN (EQ. 17) I OUT = 2 ⎛1 VOUT TOFF 1 ⎞ 1 ⎜⎜ + ⎟⎟ 2TS ⎝ L1 L2 ⎠ (EQ. 20) Solving for TOFF1 yields Equation 21: TOFF 1 = 2TS I OUT ⎛1 1 ⎞ ⎜⎜ + ⎟⎟VOUT ⎝ L1 L 2 ⎠ (EQ. 21) It should be noted that the value of TOFF1 in Equation 21 is the average value during an AC half-cycle. Since the inductors are operating in steady state, ΔI during TON and TOFF1 must be equal and opposite in magnitude for 5 AN1387.0 February 12, 2009 Application Note 1387 each inductor. Equating ΔI during periods TON and TOFF1 yields Equation 22: TON = VOUT TOFF 1 VIN (EQ. 22) where VIN is the average input voltage since TON is virtually constant over an AC half-cycle (to achieve high power factor). Since the switching frequency, TS, is constant, TOFF2 can be calculated from Equations 21 and 22, yielding Equation 23. TOFF 2 = TS − TON − TOFF 1 (EQ. 23) When selecting the values of inductors L1 ad L2, it is important to realize that they must operate in the discontinuous mode to maintain high power factor. Discontinuous operation occurs when TON + TOFF1 ≤ TS. Using this information combined with Equations 21 and 22 shows that the parallel combination of L1 and L2 must be less than the value indicated in Equation 24 for discontinuous operation to occur. 2 ⎛ V IN ⎞ ⎜⎜ ⎟ TSVOUT VIN + VOUT ⎟⎠ L1L2 ⎝ ≤ L1 + L2 2 I OUT (EQ. 24) where VIN is the average minimum input voltage, VIN is the instantaneous maximum value of the minimum input voltage, and VOUT is the minimum output voltage. Referring to Figure 6, the DC offset current that flows is the result of maintaining charge balance on the series capacitor, C1. By summing the charge into the capacitor during the three intervals TON, TOFF1, and TOFF2, the value of the DC offset current, IDC can be calculated. The average current IC1 through the series capacitor, C1, must be zero. I C1 V T2 V T2 = 0 = OUT OFF 1 − IN ON + I DC 2 L1TS 2 L2TS (EQ. 25) Substituting for TON and TOFF1 using Equations 21 and 22, and solving for IDC yields Equation 26: I DC = L1I OUT ⎛ VINVOUT L2 ⎞ ⎜ − ⎟⎟ L1 + L2 ⎜⎝ V 2IN L1 ⎠ (EQ. 26) where VIN is the average minimum input voltage, VIN is the instantaneous maximum value of the minimum input voltage, and VOUT is the minimum output voltage. It should be noted that VIN is not the instantaneous input voltage, but the input voltage corresponding to the peak of the AC input. This equation was derived using values averaged over an AC half-cycle, not from an individual switching cycle. The average value of the inductor currents during TOFF1 does equal IOUT when averaged over an AC half-cycle, but this is generally not true for an individual switching cycle. 6 As can be seen from Equation 26, the magnitude and polarity of IDC is dependent on the ratio of L2 to L1 and the product of VOUT and VIN to VIN. Equation 26 becomes invalid when VIN falls below the voltage where maximum duty cycle would occur. As long as Equation 24 is satisfied, the inductors will operate in discontinuous mode. Within this limitation, the determination of inductance values for L1 and L2 is somewhat arbitrary. However, there is an advantage in keeping IDC positive over a complete AC half-cycle. Otherwise, if IDC is negative, current will flow into the input capacitor (CIN, Figures 5, 7 and 8). Since CIN is deliberately a low value to accurately track the rectified AC line voltage, its voltage can change significantly due to IDC. This behavior can impair power factor performance. Setting Equation 26 equal to zero and solving for the ratio of L2 to L1, and substituting the result into Equation 24 yields upper limit values for L1 and L2. Examining Equation 26 further, it is apparent that if L1 >> L2, IDC will be positive for most practical operating conditions. As previously determined, the average value of current in L2 is the output current, IOUT. The average current through L1 is shown in Equation 27: I L1 = VOUT I OUT VIN (EQ. 27) where VIN is the average input voltage during an AC half-cycle. The change in inductor currents is shown in Equations 27 and 28: ΔI L1 = V VIN TON = OUT TOFF 1 L1 L1 ΔI L 2 = VIN V TON = OUT TOFF 1 L2 L2 (EQ. 28) (EQ. 29) The peak value of inductor current is the change in inductor current, ΔILx plus the offset DC current, IDC. V VIN TON + I DC = OUT TOFF 1 + I DC L1 L1 V V = IN TON − I DC = OUT TOFF 1 − I DC L2 L2 I PK ( L1) = (EQ. 30) I PK ( L 2) (EQ. 31) where VIN is the maximum instantaneous input voltage, VOUT is the minimum output voltage, and IDC is determined AN1387.0 February 12, 2009 Application Note 1387 from Equation 26. The RMS currents for each inductor are shown in Equations 32 and 33: I RMS ( L1) = 2 ⎞ 2 TON + TOFF 1 ⎛ ΔI L1 2 ⎜ ⎟ + I DC + I Δ I + I DC L DC 1 ⎜ 3 ⎟ TS ⎝ ⎠ (EQ. 32) I RMS ( L 2 ) = 2 ⎞ 2 TON + TOFF 1 ⎛ ΔI L 2 2 ⎜ ⎟ + I DC − I Δ I + I DC L DC 2 ⎜ 3 ⎟ TS ⎝ ⎠ (EQ. 33) The ripple current through the series capacitor, C1, may be calculated from the RMS currents during each of the portion of the switching cycle, TON, TOFF1, and TOFF2. I RMS ( C1) = 2 I C21( RMS )TON + I C21( RMS )TOFF 1 + I C21( RMS )TOFF 2 π (EQ. 34) where: TON TS I C1( RMS )TON = ⎛ ΔI L22 2 ⎞ ⎜⎜ ⎟⎟ − I DC ΔI L 2 + I DC ⎝ 3 ⎠ TOFF 1 ⎛ ΔI L21 2 ⎞ ⎜⎜ ⎟⎟ = + I DC ΔI L1 + I DC TS ⎝ 3 ⎠ I C1( RMS )TOFF 1 I C1( RMS )TOFF 2 = TOFF 2 2 I DC TS The RMS current through switch, Q1, is shown in Equation 35: 2 π (ΔI L1 + ΔI L 2 ) TON 3TS The average current through diode D1 is the output current IOUT. Ignoring transients, the voltage stress on D1 is equal to VIN plus VOUT. The input capacitor, CIN, must be sufficiently small so that it tracks the (unfiltered) rectified AC voltage. It must completely charged and discharged in phase with the rectified AC input during each half-cycle. If this requirement is not met, the input current waveform will be distorted and power factor quality will be compromised. Additionally, the value of C1 must on the same order of magnitude as CIN. In general, the coupling capacitor, C1, needs to be large enough to handle the ripple current, but if it is too large in comparison to CIN, its voltage will not track the input voltage well, increasing harmonic distortion, and especially zerocrossing distortion. Zero-crossing distortion is evidenced by discontinuity in the input AC current waveform when the AC voltage crosses 0V. The Flyback Converter The individual RMS values must be evaluated using the maximum instantaneous input voltage, which occurs at the peak of the rectified input AC voltage. The factor of 2/π averages the RMS value over a complete AC half-cycle. I RMS ( Q1) = where ΔIL1 and ΔIL2 are evaluated at the maximum instantaneous input voltage. Evaluating ΔIL at the maximum instantaneous input voltage will result in a conservative estimate of the ripple current. Evaluating ΔIL at the average or RMS input voltage will somewhat underestimate the ripple current. (EQ. 35) If the difference between the average input voltage and the output voltage is large, the SEPIC topology discussed earlier may not be appropriate due to the extremely low duty cycle required for steady state operation. A transformer coupled topology may be required to step the voltage down to a more manageable level. Transformer coupled topologies can also provide isolation between the input and output as may be required in some applications. The simplest transformer coupled topology is the Flyback converter. Depending on the application requirements, the converter can be isolated or not. Figure 9 shows a non-isolated configuration where the primary and secondary grounds are common, and the control loop has no isolation component. where ΔIL1 and ΔIL2 are evaluated at the maximum instantaneous input voltage. Ignoring voltage transients, the voltage stress on Q1 is equal to VIN plus VOUT plus VD1. The ripple current rating for COUT is an involved calculation. There is a high frequency component at the switching frequency, a low frequency component at the rectified AC frequency, and a DC load current component. An estimate of the RMS ripple current rating for COUT can be approximated from Equation 36. I RMS ( C OUT ) ≈ 2 ⎞ 2 TOFF 1 ⎛ (ΔI L1 + ΔI L 2 ) ⎜ − (ΔI L1 + ΔI L 2 )I OUT ⎟⎟ + I OUT ⎜ 3 TS ⎝ ⎠ T AC D COUT CIN Q RS PWM CONTROLLER FIGURE 9. FLYBACK CONVERTER LED BALLAST (EQ. 36) 7 AN1387.0 February 12, 2009 Application Note 1387 The Flyback converter operates in a similar fashion as the Boost and SEPIC converters discussed earlier. Like those topologies, the main considerations are to operate at a nearly constant duty cycle and in Discontinuous Conduction Mode (DCM). this condition must occur when operating at maximum duty cycle (minimum VRMS) while the input AC voltage is at the peak of its sinusoidal waveform. Equation 39 defines the change in secondary current, ΔIS(min), that must occur to maintain DCM operation. DCM operation must be confirmed for peak minimum input voltage (VRMS(min) x √2), maximum output current, and minimum output voltage. Given a constant load and output voltage, the average input voltage will determine the duty cycle. The maximum duty cycle occurs at the minimum average input voltage. Since power transfer from the primary to the secondary tracks the magnitude of the instantaneous AC voltage, the power transferred to the secondary is less than required when the instantaneous voltage is less than the average value for an AC cycle, and more than is required when the instantaneous voltage is greater than the average voltage. The highest currents occur when the instantaneous voltage reaches its maximum (VRMS(min) x √2). It is at this operating condition that DCM operation must be maintained in order to achieve acceptable power factor. Even though the duty cycle is determined by the average input voltage, the designer must establish DCM operation at the instantaneous peak input voltage. ΔI S (min) = The transformer design is the critical component in achieving the desired performance. The primary inductance, the secondary inductance, and the energy storage capability of the core structure must all be considered in the design. These are the same considerations present in any DCM flyback design, except it is complicated by the time-varying nature of the rectified AC input voltage. The following discussion assumes that the output power, PO, the maximum desired operating flux density, Bmax, the maximum duty cycle, DMAX, and the switching frequency, f, are pre-established quantities. The first step is to determine the energy storage requirement of the transformer core. Δw = PO η⋅ f (EQ. 37) where Δw is the energy stored in the core structure in joules, PO is the output power, η is the expected conversion efficiency, and f is the switching frequency of the converter. The output current, IO, can be expressed using Equation 38: IO = PO η ⋅ VO (EQ. 38) where VO is the output voltage. The efficiency, η, is included in Equation 38 to approximate the equivalent output current the converter must process. IO is the (equivalent) average output current that must be delivered to the load under the worst case operating conditions while operating in DCM. It is also the average current flowing in the secondary of the transformer. The desired operating behavior is to have the switching cycle terminate just as the current in the secondary winding becomes discontinuous. Furthermore, 8 π ⋅ IO (EQ. 39) 1 − Dmax where Dmax is the duty cycle that occurs at the minimum input RMS input voltage, and IO is the average output current. ΔIS(min) is scaled by π/2 because the duty cycle is determined by the average input voltage, not the peak. The maximum secondary inductance, LS, that allows the current to completely decay during the off time for DCM operation is shown in Equation 40: V (1 − DMAX ) VO (1 − DMAX ) LS = O = f ⋅ ΔI S (min) f ⋅ π ⋅ IO 2 (EQ. 40) The transformer turns ratio, NS/NP = Ns/p, may be calculated as follows. Ns / p = VO (1 − DMAX ) VIN (min, pk ) DMAX (EQ. 41) where VIN(min,pk) is the peak value of the minimum AC voltage input. The primary inductance, LP, is easily calculated from the turns ratio and secondary inductance value. LS N s2/ p LP = (EQ. 42) The peak secondary current during a switching cycle is: I S , peak = VIN (min, pk ) ⋅ DMAX f ⋅ LP ⋅ N s / p = VO ⋅ (1 − DMAX ) f ⋅ LS (EQ. 43) Up to this point, the design procedure has been independent of the core geometry and material characteristics. To proceed, these parameters must be considered. For this discussion, a E-E core with an effective cross-sectional area Ae and having discrete air gap lg will be considered. Furthermore, the core has a residual flux density of Br, and a recommended maximum flux density of Bmax. The number of secondary turns, NS, is expressed in Equation 44: NS = I S , peak ⋅ LS Ae ⋅ (Bmax − Br ) = VO ⋅ (1 − DMAX ) f ⋅ Ae ⋅ (Bmax − Br ) (EQ. 44) The required air gap in the core, lg, can be found using Equation 45: lg = μ0 ⋅ Ae ⋅ N S2 (EQ. 45) LS AN1387.0 February 12, 2009 Application Note 1387 where μ0 is the permeability of free space (4π 10-7) and the result is in meters (mks units). The number of primary turns can be found using Equation 46. N NP = S Ns / p (EQ. 46) > μ0 2 ⋅ Δw (Bmax − Br )2 (EQ. 47) where Δw is defined in Equation 37. If the inequality of Equation 47 is not satisfied, the air gap must be increased, a core with a larger cross-sectional area must be used, or the maximum flux density, Bmax, must be increased. The worst case RMS winding currents are expressed in Equations 48 and 49: I P , rms 2 VIN (min, pk ) = π f ⋅ LP ⎞ 1 ⎛⎜ VO ⎟ 3 ⎜⎝ N s / p ⋅ VIN (min, pk ) + VO ⎟⎠ 3 (EQ. 48) I S , rms = 2 VIN (min, pk ) VO ⋅ π f ⋅ LP ⋅ N s / p (N s / p ⋅ VIN (min, pk ) + VO ) ⎞ VO 1 ⎛⎜ ⎟ 1− 3 ⎜⎝ (N s / p ⋅ VIN (min, pk ) + VO ) ⎟⎠ (EQ. 49) 2 VO ⋅ TOFF 1 2TS ⋅ LS (EQ. 50) Solving for TOFF1 yields: TOFF 1 = 2 I O ⋅ TS ⋅ LS VO (EQ. 51) The change in current, ΔI, during TON and TOFF1 scaled by the turns ratio must be equal. Equating the change in amp turns (ΔI*NP = ΔI*NS) during TON and TOFF1, respectively, and solving for TON yields: TON = N S VIN ' ⋅ TON N P VO (EQ. 53) VO ⋅ N P ⋅ TOFF 1 V IN ⋅ N S (EQ. 52) where VIN is the average input voltage. Equations 51 and 52 represent the average values of TOFF1 and TON, respectively. While TON is essentially constant during an AC half-cycle, the instantaneous value of TOFF1 will vary 9 The Output Capacitor Each of these converters operates from the AC mains with high power factor. Power delivery from the AC mains is sinusoidal and at a low frequency, so either the power to the load must be delivered as received from the source or there must be a provision to store the energy in the converter. The output capacitor performs this function. It not only filters the converter switching currents, but must also provide sufficient energy storage to maintain the output during the AC nodes with an acceptable level of ripple voltage. The allowed ripple voltage is determined by how much ripple current is acceptable in the LED load. Due to the non-linear behavior of the LED diode junction, the ripple current will be higher than might be expected from a given ripple voltage. Although higher ripple currents, even as much as 50-70%, do not produce observable flicker, some LED manufacturers suggest limiting the amount of ripple current to keep peak currents within ratings. Ultimately, the designer must evaluate the trade-offs between capacitance value and ripple current. The Control Loop The output current, IOUT, is equal to the average current in the secondary winding of the transformer. Since current only flows in the secondary winding during TOFF1, the output current can be expressed as: I OUT = TOFF 1' = where VIN’ is the instantaneous value of the input voltage. The capacity of the core to store sufficient energy needs to be verified. Since all of the stored energy occurs in the air gap, the volume of the air gap determines the energy storage capacity. Ae ⋅ l g considerably over the same time period. The instantaneous value of TOFF1, TOFF1’, may be calculated from Equation 53. Figures 12, 13, and 14 show detailed schematics for boost, SEPIC, and flyback converters, respectively. These converters are based on the Intersil ISL6745 double-ended PWM controller. The control loop is not topology dependent. The same loop configuration can be used in virtually all off-line AC LED applications. It consists of an operational amplifier in a low bandwidth integrator configuration. Referring to Figure 10, resistor RS converts the LED current into a voltage that is compared to VREF. The operational amplifier integrates the difference and creates an error voltage output used to control the PWM. The critical requirement for the control loop is that its bandwidth be limited to about 30Hz. The crossover frequency, fC of the control loop is shown in Equation 54: fC = 1 2πRCFB (EQ. 54) Setting fC equal to 30Hz and solving for the RC time constant τ yields Equation 55: τ = RCFB = 1 60π (EQ. 55) For example, selecting CFB = 0.1µF, yields a value of 53kΩ for R. AN1387.0 February 12, 2009 Application Note 1387 The LED current is set by VREF and RS, but the current may also be dynamically modulated using the IADJ input to vary the reference setpoint. IADJ is typically used to vary the intensity or color temperature. VOUT AC AC Power Stage AC PWM In Return PWM Controller CFB Error Voltage R - FB However, depending on the application, just paralleling LED strings may cause unacceptable color temperature and/or intensity variation among the LED strings. Additional circuitry to force current balancing may be required. Figure 11 shows a technique of paralleling LED strings with current balancing. The method consists of a master LED string and multiple slave strings in parallel. The LED driver control loop regulates the current in the master LED string, and the slave LED strings are individually regulated to match the current through the master LED string. Diode D is present only in the master LED string so that the linear pass elements, Q, in the slave LED strings have sufficient voltage across them to allow regulation. Alternatively, an extra LED in the master string accomplishes the same result. VOUT + VREF + - RS IADJ FIGURE 10. INTEGRATING CONTROL LOOP D Using Multiple Parallel LED Strings The previous discussion centered on a single string of LEDs in series for the sake of clarity. For many applications, a single string may be acceptable, but other applications may require more light intensity than can be practically delivered by a single string of LEDs. In these applications, additional LEDs strings may be added in parallel. Since the LED driver provides a single output, it cannot control the current through each LED string. Unless there is a mechanism to force equal currents through each LED string, the currents will not be balanced. The magnitude of the imbalance depends on the cumulative variation of forward voltage drop across each LED in the string. If the forward voltage distribution for each LED is random, then the differences in the cumulative variation among the LED strings tends to zero out as the number of LEDs in each string increases. The forward voltage drop across each LED may be represented as a temperature dependent voltage in series with a resistor. Fortunately, the resistance is rather large for the LEDs under consideration. CREE XLamp 7090 LEDs, for example, has an equivalent series resistance of approximately 1.9Ω. The resistance tends to linearize the V-I relationship of the LED so that variations in the voltage drop due to temperature and process variation have a reduced impact. Adding a discrete series resistor in each LED string will further enhance current balance, but at the expense of increased power dissipation. 10 RS Q Q RS RS + + Return FB FIGURE 11. PARALLEL LED STRINGS WITH CURRENT BALANCING In some applications the number or type of LEDs in each string may not be the same. In this case, having a common supply voltage for each string mar result in excessive dissipation in the linear pass elements. The solution is to provide different supply voltages to each string by providing winding taps on the transformer or inductor. Alternatively, each string can be controlled by a separate switching regulator. References 1. "CREE Achieves Highest Efficacy from a High-Power LED", CREE Press Release, September 13, 2007. 2. "Maximize Your Profit Potential with Sylvania HID Lamps. High Intensity Discharge Lighting", OSRAM Sylvania Product Information Bulletin CP103R3E, October 2007. AN1387.0 February 12, 2009 Application Circuits L L1 82 uH MSD1278-823MLB CoilCraft C2 0.1uF 275VAC PME271M610MR30 EvoxRifa F1 125VAC TBD/TD 35V L2 TBD mH Optional EMI Filter C1 0.22 uF 275VAC PME271M622KR30 EvoxRifa CR2 1A 400V ES1G 1,2 R1 499k 1206 11 Z1 MOV TMOV14R140E LITTELFUSE 90 –140 VAC - CR1 2A 600V 2W06G DIODES INC R3 2.61k 2512 R5 49.9k 1206 R4 2.61k 2512 R6 49.9k 1206 3,4 >60 LED STRING C5 220pF 630V 1206 DNP + + Q1 IRFR320 IR Q2 350V MJD47 R2 499k 1206 R15 100 2512 DNP VR1 11V RT1 TBD Ametherm C4 TBD Electrolytic R14 TBD 2512 R17 R17 = 1.225/Iout RETURN N ExtVdd U1 ISL6745 R19 90.9k 1 SS VDD 10 R8 100k R9 100k 2 RTD VDDP 9 3 VERR OUTB 8 NOTES: Unless otherwise specified 1) All components are 0805 2) All capacitors are ceramic 10%, 50V 3) All resistors are 1% 4) DNP= May not be required, depending on power level and layout 5) TBD component vlaues depend on quantity and type of LEDs used. 4 CS OUTA 7 5 CT GND 6 U2 LM358 R13 10.0 C8 220pF - 2 1 + 3 Q3 BSS138 - 6 + 5 7 4 C7 1.0uF C10 100.0uF 16V Electrolytic R7 30.1k C9 330 pF COG R18 10.0k R12 57.6k 8 R10 TBD + 1 C6 0.1uF U3 LM4041-1.2 C11 330pF 2 R11 100k Iadj FIGURE 12. DETAILED BOOST CONVERTER SCHEMATIC Application Note 1387 CR3 MMBD4148 R16 100 AN1387.0 February 12, 2009 Application Circuits (Continued) C2 0.1uF 275VAC ECQU2A104ML Panasonic F1 125VAC 2A/TD L L3 TBD mH Optional EMI Filter C1 0.22 uF 275VAC ECQU2A224ML Panasonic 1,2 R3 2.61K 2512 R5 49.9K 1206 R4 2.61K 2512 R6 49.9K 1206 CR2 1A 400V ES1G 35V Max 3,4 ≥ 4 LED STRING 1,2 R1 499K 1206 Z1 MOV TMOV14R140E LITTELFUSE 90 – 140 VAC C3 0.1uF 250V TDK C3225X7R2E104 1210 330 uH MSD1278-334KLB CoilCraft - CR1 2A 400V 2W04G DIODES INC + 12 Q1 IRFR320 IR Q2 350V MJD47 R2 499K 1206 L2 82 uH MSD1278-823MLB CoilCraft + 3,4 C4 TBD CR4 BAT54 R14 TBD 2512 VR1 11V RT1 TBD Ametherm R17 R17=1.225/Iout RETURN N ExtVdd Application Note 1387 CR3 MMBD4148 R16 100 U1 ISL6745 1 SS R8 100K VDD 10 R9 100K 2 RTD VDDP 9 3 VERR OUTB 8 4 CS OUTA 7 5 CT GND 6 U2 LM358 R13 10.0 1206 C8 220pF NOTES: Unless otherwise specified 1) All components are 0805 2) All capacitors are ceramic 10%, 50V 3) All resistors are 1% 4) DNP = May not be required, depending on power level and layout 5) TBD component vlaues depend on quantity and type of LEDs used. - 2 1 + 3 Q3 BSS138 - 6 + 5 7 4 R10 TBD + C7 1.0uF C10 100.0uF 16V R7 30.1K C9 330 pF COG R18 10.0K R12 34.0K 8 1 C6 0.1uF U3 LM4041-1.2 C11 330pF 2 R11 100K Iadj FIGURE 13. DETAILED SEPIC CONVERTER SCHEMATIC AN1387.0 February 12, 2009 Application Circuits (Continued) +Vout 13 85 –275 VAC C1 0.1μF 250VAC ECQU2A104ML Panasonic Z1 MOV TMOV14R275E LITTELFUSE R1A 499K 1206 - CR1 1.0A 800V DF08S Diodes, Inc C4 1nF 630V 1206 COG/NPO R3 38.0K 5% 2512 1W R13 2.61K 2512 L L1 330μH RFB0807-331L CoilCraft CR4 TBD T1 TBD F1 TBD 250VAC TD R15 49.9K 1206 R14 2.61K 2512 R16 49.9K 1206 + R12 10.0 2512 + CR3 MURS160 Diodes, Inc C14 TBDuF 100V Electrolytic C13 220pF 250V 0603 COG/NPO R1B 499K 1206 Return C2 0.1μF 250VAC ECQU2A104ML Panasonic R1C 499K 1206 Q2 400V MJD50 Fairchild C3 0.047μF 250VAC ECQU2A473ML Panasonic RT1 TBD Ametherm R6 R6=1.225/Iout Q1 IRF420A CR5 BAT54 VR1 11V BZX84-C11 N R17 100 VDD 10 1 SS ExtVdd CR3 MMSD4148 2 RTD VDDP 9 R8 100k 3 VERR OUTB 8 4 CS OUTA 7 5 CT GND 6 R8 3.01K U1 ISL6745 1) All Resistors are 1% 0805 unless otherwise specified 2) All capacitors are 10% 50V 0805 X7R ceramic unless otherwise specified 3) TBD values are dependent on the type and quantity of LEDs used R9 100k U2 LM358 R13 10.0 1206 - 1 2 + 3 Q2 BSS138 - 7 6 + 5 4 + C7 1.0uF 0805 R7 30.1K C8 220pF C9 330 pF COG C10 100.0uF 16V Electrolytic 3 VR3 4.7V BZX84-C4V7 1 R18 10.0k R12 34.0k 8 R10 TBD + 1 C6 0.1uF C6 0.1uF U3 LM4041DIM3-1.2 C11 330pF 2 R11 100k Iadj FIGURE 14. DETAILED FLYBACK CONVERTER SCHEMATIC AN1387.0 February 12, 2009 Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Application Note 1387 R4 0.430 2512 1W

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