AN1458: Extending the TID Capability of the ISL7457SRH

Extending the TID Capability of the ISL7457SRH
®
Application Note
March 17, 2009
AN1458.0
ISL7457SRH TID Rating
R1
The ISL7457SRH is specified for 10krads(Si) minimum TID
in SMD 5962-08230 when continuously biased as shown in
Figure 1.
In many cases a 10krad(Si) TID rating is not adequate to
meet mission requirements, so a method to extend the TID
capability is desired. Figure 2 shows a radiation exposure
circuit that biases the ISL7457SRH only 20% of the time. For
the other 80% of the time, the ISL7457SRH is unbiased.
Devices irradiated in this manner have demonstrated
acceptable post-rad parametric limits after 50krad(Si) TID,
as indicated in the Electrical Specification tables of this
application note. Please note, however, that the post-50krad
electrical specifications shown herein are not specified in or
guaranteed by SMD 5962-08230.
Imaging Applications
Some camera CCD driver applications do not require 100%
availability. In these situations, the ISL7457SRH can be left
unbiased until there is a need to image. When imaging is
required, the ISL7457SRH can be quickly biased by simply
closing a switch. As long as the duty-cycle of the application
does not exceed 20%, the TID capability can be extended up
to 50krad(Si).
R2
R1
U1
VS
INA
VS+
OE
OUTA
INB
OUTB
R1
R1
VL ISL7457SRH NC
GND
R1
VH
NC
OUTC
INC
OUTD
IND
VS-
R1
C1
C1 = 100n
R1 = 15k
R2 = 10k
VS = 15V
R1
R1
FIGURE 1. RAD EXPOSURE CIRCUIT (BIAS DUTY CYCLE =
100%)
DUTY CYCLE (SWITCH OPEN) = 80%
DUTY CYCLE (SWITCH CLOSED) = 20%
SW1
SPST
R1
R2
R1
U1
Conclusions
A simple method to extend the TID capability of the
ISL7457SRH to 50krad(Si) has been described. This
method can be applied to any space-based system that uses
the device as long as 20% availability is acceptable.
VS
INA
VS+
OUTA
OE
INB
OUTB
VL ISL7457SRH NC
GND
VH
NC
OUTC
OUTD
INC
IND
VSC1 = 100n
R1 = 15k
R2 = 10k
VS = 15V
R1
R1
R1
R1
C1
R1
R1
FIGURE 2. RAD EXPOSURE CIRCUIT (BIAS DUTY CYCLE =
20%)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Application Note 1458
Electrical Specifications
PARAMETER
VS+ = VH = 5V ±10%, VS- = VL= 0V, OE = VS+, TA = +25°C, Post 50krad(Si) unless otherwise specified. Refer
to Figure 2 for radiation exposure circuit biasing.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT
VIH
Logic “1” Input Voltage
IIH
Logic “1” Input Current
VIL
Logic “0” Input Voltage
IIL
Logic “0” Input Current
INx = 0V
ROH
ON Resistance VH to OUTx
ROL
2
INx = VS+
-10
V
10
µA
0.6
V
10
µA
INx = VS+, IOUTx = -100mA
12
Ω
ON Resistance VL to OUTx
INx = 0V, IOUTx = +100mA
7
Ω
ILEAK+
Positive Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS+
300
µA
ILEAK-
Negative Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS-
-10
OUTPUT
-50
µA
POWER SUPPLY
IS+
VS+ Supply Current
INx = 0V and VS+
IS-
VS- Supply Current
INx = 0V and VS+
IH
VH Supply Current
INx = 0V and VS+
IL
VL Supply Current
INx = 0V and VS+
5
-5
mA
mA
650
-650
µA
µA
SWITCHING CHARACTERISTICS
tR
Rise Time
INx = 0V to 4.5V step, CL = 1nF
40
ns
tF
Fall Time
INx = 4.5V to 0V step, CL = 1nF
26
ns
tRFΔ
tR, tF Mismatch
CL = 1nF
5
ns
tD+
Turn-On Delay Time
INx = 0V to 4.5V step, CL = 1nF
30
ns
tD-
Turn-Off Delay Time
INx = 4.5V to 0V step, CL = 1nF
40
ns
tDD
tD+, tD- Mismatch
CL = 1nF
12
ns
tENABLE
Enable Delay Time
INx = VS+, OE = 0V to 4.5V step, RL = 1kΩ
35
ns
tDISABLE
Disable Delay Time
INX = VS+, OE = 4.5V to 0V step, RL = 1kΩ
50
ns
2
AN1458.0
March 17, 2009
Application Note 1458
Electrical Specifications
PARAMETER
VS+ = VH = 15V ±10%, VS- = VL= 0V, OE = VS+, TA = +25°C, Post 50krad(Si) unless otherwise specified.
Refer to Figure 2 for radiation exposure circuit biasing.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT
VIH
Logic “1” Input Voltage
IIH
Logic “1” Input Current
VIL
Logic “0” Input Voltage
IIL
Logic “0” Input Current
INx = 0V
ROH
ON Resistance VH to OUTx
ROL
2
INx = VS+
-10
V
10
µA
0.6
V
10
µA
INx = VS+, IOUTx = -100mA
5
Ω
ON Resistance VL to OUTx
INx = 0V, IOUTx = +100mA
5
Ω
ILEAK+
Positive Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS+
300
µA
ILEAK-
Negative Output Leakage Current
INx = VS+, OE = 0V, OUTx = VS-
-10
OUTPUT
-50
µA
POWER SUPPLY
IS+
VS+ Supply Current
INx = 0V and VS+
IS-
VS- Supply Current
INx = 0V and VS+
IH
VH Supply Current
INx = 0V and VS+
IL
VL Supply Current
INx = 0V and VS+
5
-5
mA
mA
750
-750
µA
µA
SWITCHING CHARACTERISTICS
tR
Rise Time
INx = 0V to 5V step, CL = 1nF
20
ns
tF
Fall Time
INx = 5V to 0V step, CL = 1nF
20
ns
tRFΔ
tR, tF Mismatch
CL = 1nF
3
ns
tD+
Turn-On Delay Time
INx = 0V to 5V step, CL = 1nF
20
ns
tD-
Turn-Off Delay Time
INx = 5V to 0V step, CL = 1nF
20
ns
tDD
tD+, tD- Mismatch
CL = 1nF
5
ns
tENABLE
Enable Delay Time
INx = VS+, OE = 0V to 5V step, RL = 1kΩ
25
ns
tDISABLE
Disable Delay Time
INx = VS+, OE = 5V to 0V step, RL = 1kΩ
65
ns
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
AN1458.0
March 17, 2009
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