AN1673: Application Circuit to Generate Plus and Minus Supplies Using the ISL97701 Boost Regulator

Application Note 1673
Authors: Don LaFontaine, Dan Goodhew
Application Circuit to Generate Plus and Minus
Supplies Using the ISL97701 Boost Regulator
Introduction
This application note will discuss a method to combine the
operation of a boost regulator and a negative voltage
converter. The circuit described will generate both a positive
and a negative supply from a single low voltage supply. The
circuit in Figure 5 shows the standard ISL97701 application
circuit for a +20V supply along with two ISL28107 op amps,
two diodes and two capacitors to generate a well regulated
-20V supply.
Understanding the Boost Topology
Before we add the additional circuitry to generate the negative
supply, it is important to understand how the boost convertor
produces an output voltage that is always greater than the
input voltage. In order to do this, we analyze the boost circuits
in Figure 1 and the current waveforms in Figure 2. For this
analysis, we account for all the losses in the charging and
discharging loops in our equations. This should help to give a
complete understanding of the circuit.
However, the ISL97701’s output voltage is not dependent upon
any losses in the circuit. This is because all the losses are
inside the circuit’s feedback loop of the ISL97701, and are
automatically accounted for. The output voltage is defined
from the feedback resistor network shown in Figure 5 and
calculated in Equation 1, where VrefFB is the internal reference
voltage of the ISL97701.
forward biased. Since the dot end is at VIN, L1 delivers its
stored energy to C1 and charges it up to a higher voltage than
VIN. This energy supplies the load current and replenishes the
charge drained away from C1. During this time, energy is also
supplied to the load from VIN. The voltage applied to the dot
end of the inductor is (VIN - IL1 x RL1). The voltage applied to
the no-dot end of L1 is now the output voltage, VO, plus the
diode forward voltage VD. The voltage across the inductor
during the off-state is ((VO + VD1 + IL1 x RL1) - VIN). The inductor
current during the off-time of the switch (T-DT) is calculated in
Equation 4 and shown graphically in Figure 1C.
( V O + V D1 + I L1 × R L1 ) – V IN
ΔI L1 ( off ) = -------------------------------------------------------------------------- × ( T – DT )
L
In steady-state conditions, the current increases during the
on-time of the switch and decreases during the off-time of the
switch, reference Figure 2. Both on-time and off-time currents
are equal to prevent the inductor core from saturating. Setting
both currents equal to each other and solving for VO results in
the continuous conduction mode boost voltage shown in
Equation 5.
V IN – I L × R L
D
V O = -------------------------------- – V D1 – V DS × ------------1–D
1–D
RL1
Q1
C1
RL
FIGURE 1A.
Figure 1A shows the basic boost converter circuit. During one
switching cycle, the transistor Q1 turns on and turns off. During
the time Q1 is on, the inductor L1 is placed in series with the
VIN supply through the ISL97701’s integrated boost FET (Q1).
The diode D1 is reversed biased and the circuit reduces to that
shown in Figure 1B. The voltage across the boost inductor (L1)
is equal to VIN - (VDS + IL1 x RL1) and the current ramps up
linearly in inductor L1 to a peak value at time DT. The peak
inductor current (Δ IL1(on)) is calculated in Equation 3 and
shown graphically in Figure 1B. Any load requirements during
this phase are supplied by the output capacitor C1.
Δ IL1(on)= (VIN-(VDS + IL1xRL1))DT
RL1
VIN
+
∫ dt
When Q1 turns off, since the current in an inductor cannot
change instantaneously, the voltage in L1 reverses and the
circuit becomes that shown in Figure 1C. Now the no-dot end
of L1 is positive with respect to the dot end and D1 becomes
1
IQ1
Q1
VDS
IQ1
0T
DT
Δ IL1(off) = (VO+VD+IL1xRL)-VIN(T-DT)
RL1
VIN
+
(EQ. 3)
IL1
L
FIGURE 1B.
(EQ. 2)
V IN – ( V DS + I L1 × R L1 )
ΔI L1 ( on ) = ------------------------------------------------------------ × DT
L
L1
-
DT
T0
November 18, 2011
AN1673.0
VO
Io
-
(EQ. 1)
Positive Supply
di L
VL
V L = L × -------- ⇒ i Lpk = -----dt
L
(EQ. 5)
D1
L1
IL1
VIN
+
V OUT = V refFB • ( R 1 + R 2 ) ⁄ R 2
V OUT = 1.15V • ( R 1 + R 2 ) ⁄ R 2
(EQ. 4)
IL1
L1
D1
VO
L
ID
ID
C1
RL
-
DT
T
FIGURE 1C.
FIGURE 1. BASIC BOOST TOPOLOGY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved.
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1673
Q1 ON
IQ1
IL1
Q1 OFF
IL1(pk)
ΔIL1
IL1(ave)
O
OT
T
DT
DT
T
FIGURE 3. INDUCTOR AVERAGE AND PEAK CURRENTS
ID1
From Figure 3, it can be seen that the peak inductor current
IL1(PK) is equal to the average inductor current IL1(ave) plus one
half the Δ IL1 current, as shown in Equation 8.
1
I L1 ( PEAK ) = I L1 ( AVE ) + --- ΔI L1 ( on )
2
OT
IL1
T
DT
IL1(pk)
ΔIL1
IL1(ave)
(EQ. 8)
The average power IN is equal to the average power OUT divided
by the efficiency of the circuit, as shown in Equation 9.
VO × IO
V IN × I L1 ( AVE ) = -----------------Eff
(EQ. 9)
Where Eff is equal to the efficiency of the ISL97701 boost
regulator.
OT
T
DT
FIGURE 2. INDUCTOR, TRANSISTOR AND DIODE CURRENTS
The duty cycle “D” in Equation 5 is determined by setting the
losses in Equation 5 (IL1 x RL1, VD1, VDS) to zero because they
are within the feedback loop of the ISL97701. The ISL97701
varies the duty cycle continuously to keep VO constant,
regardless of the conduction losses as a function of load current.
With the losses set to zero, Equation 5 reduces to Equation 6.
This results in the value for the Duty Cycle as shown in
Equation 7.
VO
1 ------- = -----------V IN
1–D
(EQ. 6)
V IN
D = 1 – -------VO
(EQ. 7)
Therefore, the average inductor current is equal to the output
current times the gain of the boost regulator as shown in
Equation 10.
VO × IO
I L1 ( AVE ) = ---------------------V IN × E ff
(EQ. 10)
Δ IL1(on) was defined in Equation 3 and the duty cycle “D” in
Equation 7. Substituting Equation 7 into Equation 3 and adding it
to Equation 10 results in Equation 11. Equation 11 gives the
inductor’s peak current in terms of input voltage, output voltage,
switching frequency, and maximum output current (again, the
losses due to VDS and IL1 x RL1 are not included because they
are inside the feedback loop of the ISL97701).
VO × IO
V IN × ( V O – V IN )
I L ( PEAK ) = ---------------------- + 1 ⁄ 2 × ----------------------------------------V IN × E ff
L × V O × FREQ
(EQ. 11)
By rearranging the terms in Equations 11, we can solve for the
inductor value using Equation 12.
Inductor Selection
The inductor selection determines the output ripple voltage,
transient response, output current capability, and efficiency. Its
selection depends on the input voltage, peak inductor current,
output voltage, switching frequency, and maximum output
current. When choosing an inductor, make sure the saturation
current of the inductor is greater than the IPEAK of the circuit.
Likewise, the transistor should be able to handle peak current
greater than IPEAK. The peak inductor current is shown in
Figure 3 and can be calculated using Equation 11.
2
2 Eff ( V – V )
V IN
O
IN
L = -------------------------------------------------------------------------( I PK V IN Eff – I O V O )2V O FREQ
(EQ. 12)
Equation 12 is useful for determining the minimum value of L
the circuit can handle without exceeding the peak current
through the inductor, and therefore, the switch Q1. The
maximum peak current (IPEAK) allowed through Q1 for safe
operation is given in the Electrical Specification table of the
ISL97701 data sheet as 1.2A.
AN1673.0
November 18, 2011
Application Note 1673
Minimum Inductor Value Design Example
Negative Supply
Given: VIN = 5V, VO = 25V, IO = 35mA, IPK = 1.2A, freq = 1MHz,
Eff = 0.85 (Efficiency of 85% from Figure 3 in ISL97701 data
sheet).
The operation of the negative supply is best understood by
considering Figure 5. We will start our analysis under steady
state conditions (the inductor operating in continuous conduction
mode and C1 is equal to the voltage calculated in Equation 1).
Equation 12 gives us the boundary condition for the smallest
inductor we can have to ensure the peak current through Q1 is
less than the max limit of 1.2A. The minimum inductor value for
the given conditions is determined to be 2.0µH.
( 5V ) 2 ( 0.85 ) ( 25 – 5 )
L = ------------------------------------------------------------------------------------------------------------- = 2.0μH
( 1.2A ( 5 ) ( 0.85 ) – 35mA ( 25 ) )2 ( 25 )1MHz
(EQ. 13)
Maintaining CCM Design Example
For maximum efficiency, the boost converter needs to be
operated in continuous conduction mode (CCM). To maintain
continuous conduction mode operation of the boost regulator,
the value of IL1(ave) needs to be greater than or equal to ΔIL1/2,
reference Figure 3.
When Q1 turns off, the inductor voltage flies up turning on D1
and D3. Diode D2 is blocking current flow from C3. The inductor
current now charges both capacitors C1 and C2 with the polarity
as shown in Figure 5. The voltage on C2 is equal to the voltage on
C1, plus the forward voltage drop of D1.
When Q1 turns on, Diodes D1 and D3 are blocking and capacitor
C2 is now in parallel with capacitor C3 through D2 (which is now
on), reference Figure 4. This connection results in a negative
voltage being transferred on to C3. The voltage transferred to C3
is equal to the voltage on C1 as shown in Figure 4 and
Equation 18.
1
I L1 ( AVE ) ≥ --- ΔI L1
2
+
C2
VO × IO
V IN × ( V O – V IN )
---------------------≥ 1 ⁄ 2 × ----------------------------------------V IN × E ff
L × V O × FREQ
(EQ. 14)
D1
Rearranging terms and solving for L results in Equation 15.
V IN × ( V O – V IN )
L ≥ 1 ⁄ 2 × ---------------------------------------------------------VO × IO
---------------------× V O × FREQ
V IN × E ff
D2
VC1
+
C1
-
(EQ. 15)
+
VC3
C3
V = VC1+D1
Q1 turns on connecting
C2 to ground as shown.
FIGURE 4. CHARGING OF NEGATIVE SUPPLY CAPACITOR C3
To maintain continuous conduction mode operation, for the given
circuit design conditions above, the value of L has to be greater
than 9.71µH.
5V × ( 25V – 5V )
L ≥ 1 ⁄ 2 × ------------------------------------------------------------------------- ≥ 9.71μH
25V × 35mA
--------------------------------- × 25V × 1MHz
5V × ( 0.85 )
(EQ. 16)
It should be noted that when there is a light load, the circuit can
slip into discontinuous conduction mode, where the inductor
becomes fully discharged of its current each cycle. This operation
will reduce the overall efficiency of the supply. Using Equation 15
and making the value of the inductor large enough for a given
minimum output current will insure continuous conduction mode
operation.
Output Capacitor
Low ESR capacitors should be used to minimize the output voltage
ripple. Multilayer ceramic capacitors (X5R and X7R) are preferred
for the output capacitors because of their lower ESR and small
packages. Tantalum capacitors with higher ESR can also be used.
The output ripple can be calculated in Equation 17:
I OUT × D
ΔV O = ----------------------- + I OUT × ESR
f SW × C 1
(EQ. 17)
For noise sensitive applications, a 0.1µF placed in parallel with
the larger output capacitor is recommended to reduce the
switching noise.
3
( V C1 + D 1 ) – D 2 – V C3 = 0
V C1 = V C3
(EQ. 18)
The efficiency of the charge transfer between the two capacitors
is related to the energy lost during this process. ENERGY IS LOST
ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A
CHANGE IN VOLTAGE OCCURS. The energy lost is defined in
Equation 19:
2
2
1
E = --- C 2 ( V 1 – V 2 )
2
(EQ. 19)
Where V1 and V2 are the voltages on C2 during the charging and
transfer cycles. If the impedances of C2 and C3 are relatively high
at the 1MHz frequency compared to the value of RL, there will be
substantial difference in the voltages V1 and V2. Therefore, it is
not only desirable to make C3 as large as possible to eliminate
output voltage ripple, but also to employ a correspondingly large
value for C2 in order to achieve maximum efficiency of operation.
Output Voltage Regulation using Op Amps
The final output voltage regulation is accomplished using two
ISL28107 op amps (note: two separate op amps required
because of the different supply connections). The voltage
developed by the boost converter powers the amplifiers and the
output voltage is calculated using Equations 20 and 21.
V OUT ( positive ) = 5V • ( R 3 + R 4 ) ⁄ R 3
(EQ. 20)
V OUT ( negative ) = – V OUT ( positive ) • R 6 ⁄ R 5
(EQ. 21)
AN1673.0
November 18, 2011
Application Note 1673
Restriction on Design:
exceeded (Equation 12). The only drawback will be a
reduction in the efficiency of the circuit. The percent
efficiency could drop from the 80’s to the 60’s as the
operation goes from continuous conduction mode to
discontinuous conduction mode. Reference the ISL97701
data sheet for additional information on performance of the
Boost Regulator.
1. For reasonable voltage regulation of the negative supply
voltage, the negative supply current needs to be less than or
equal to the positive supply current. This is because the
control loop for output voltage regulation is around the
positive supply voltage only.
I OUT ( positive ) ≥ I OUT ( negative )
(EQ. 22)
4. To obtain output currents higher than 40mA, the user could:
2. The maximum output current of the circuit shown in Figure 5
is limited by the maximum output current of the ISL28107
op amps, which is 40mA.
• Operate the circuit without the op amps (at the cost of
output voltage regulation) by connecting directly to C1
and C3
3. The ISL97701 is optimized to work best for a small range of
inductors. The slope compensation ramp generator, inside
the ISL97701, is optimized for inductor values between the
range of 4.7µH to 15µH and output currents between 25mA
to 125mA. The circuit will work for inductor values outside
this range, as long as the maximum IPEAK current is not
• Or replace the op amps with ones with higher output
current drive capability
L1
+
10µH
C2
-
D2
- 25.35V
C3
4.7µF
4.7µF
D3
VDDOUT
VOUT(positive)
+
20V
LX
VDD
C0
5µF
NEN
OSCILLATOR
AND
CONTROL
5V
5. The accuracy of the output voltage is highly dependent on the
input voltage source. Using a well regulated voltage source is
recommended.
D1
VOUT
Q1
25.35V
V0
+
C1
4.7µF
-
R6
R1
383kΩ
ISL28107
R3
FB
ISL97701
R2
18.2kΩ
-20V
5V
NSYNC
GND
VOUT(negative)
100kΩ
+
V+
-
V-
R5
-
V-
+
V+
100kΩ
33.2kΩ
R4
5V
100kΩ
ISL28107
FIGURE 5. REFERENCE DESIGN TO GENERATE A POSITIVE AND NEGATIVE SUPPLY
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
4
AN1673.0
November 18, 2011
Similar pages