AN1825: Overcoming the Minimum VDD Ramp Rate Limitation of the ISL25700

Application Note 1825
Author: Paul Traynham
Overcoming the Minimum VDD Ramp Rate Limitation of
the ISL25700
Background
It features a programmable overcurrent protection of the
MOSFET that automatically adjusts the output voltage in order
to keep the MOSFET power under user defined limits.
The ISL25700 is a Temperature Controlled MOSFET Driver that
is an integral part of a temperature control loop to maintain a
constant pre-programmed temperature for many applications
but is primarily used in Oven Controlled Oscillators or OCXOs.
The protection settings always override the temperature
settings that cause violation of the current limit. These settings
are all programmed and stored in non-volatile memory.
Block Diagram/Application Circuit
3V TO 15V
VDD
VOLATILE & NONVOLATILE
REGISTERS
I2C BUS
CONTROL
SCL
SDA
K3
R
PROGRAMMABLE
OVERCURRENT
PROTECTION
K1
RSENSE
ISENSE
8-BIT FTC
DAC
K2
REFERENCE
GENERATOR &
POWER
CIRCUITRY
C
ADJUSTABLE SYSTEM
LOOP GAIN
VREF
RTH
VOUT
PMOS
VINT
THERMISTOR
RINT
VREF
8-BIT GP
DAC
VDAC
HEATER
GND
February 20, 2013
AN1825.0
1
CCOMP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Application Note 1825
VDD Ramp Rate Limitations
In normal OCXO applications, VDD ramp rates are not usually a
problem and fall somewhere between the minimum and
maximum; however, during evaluation, OCXOs are commonly
ramped up by hand on a bench supply. Doing so will almost
certainly result in memory loss. Exceeding the maximum VDD
ramp is usually not an issue, however, if it were to become an
issue, it can be easily solved by adding more decoupling
capacitance to slow down the ramp rate.
The ISL25700 datasheet specifies a parameter called “VDD
Ramp Rate” with a minimum of 0.2V/ms and a maximum of
50V/ms as its limits. Table 1 shows an excerpt of the Operating
Specifications table pertaining to this specification. The outcome
of violating the specification is data corruption of the non-volatile
memory. This corruption causes the memory to be reset to a
baseline state and can cause damage to the ISL25700 or the
MOSFET.
The Solution
Since the most critical voltage range for memory loss caused by
slow ramp rate is between 0V and 3V, the easiest solution is to
hold off VDD from being applied to the ISL25700 and the
P-channel MOSFET until VDD has reached the 3V threshold.
While the datasheet specifies that this ramp rate must be
adhered to from 0V to 15V, it has been shown in lab testing to be
only critical from 0V to the minimum operating voltage, 3V. Once
the ISL25700 VDD voltage reaches 3V, the ramp rate can violate
the spec and non-volatile memory will be retained. In fact, there
is some margin below 3V. Empirical testing has shown that once
VDD reaches approximately 2.5V, memory will be retained.
Figure 1 shows a circuit that achieves this desired outcome. The
ISL88001 is a Power On Reset/Voltage Monitor IC. It has an
active low reset output that powers up low (0V) and remains low
as long as VIN is <2.92V nominal. As soon as 2.92V is reached,
the reset of the output goes high (VIN). It will track VIN until the
zener diode D1, reaches its breakdown voltage of approximately
5.1V and then levels off at near to that voltage. The zener is
needed because the maximum operating supply voltage of the
ISL88001 is 5.5V. It draws very little quiescent current (400nA
max), so a zener diode is ideal. PLVA650A was chosen for its
small size, low reverse leakage and low cost.
TABLE 1. VDD RAMP RATE SPECIFICATION
SYMBOL
PARAMETER
VDD Ramp VDD Ramp
Rate
TEST
CONDITIONS
MIN TYP MAX UNITS
@ Any Level
From 0V to 15V
0.2
50
V/ms
LOGIC LEVEL MOSFETS
VIN = 0V TO 15V
10kΩ
PMOS
Q1
Q2
NMOS
NTCD4167C
COMPLIMENTARY
DUAL MOSFETS
VDD
VOLATILE & NONVOLATILE
REGISTERS
I2C BUS
CONTROL
SCL
SDA
K2
K3
REFERENCE
GENERATOR &
POWER
CIRCUITRY
R
PROGRAMMABLE
OVERCURRENT
PROTECTION
K1
D1
5.1V ZENER
PLVA650A
POR
± VREF
ISENSE
8-BIT FTC
DAC
1kΩ
C
ADJUSTABLE SYSTEM
LOOP GAIN
RST
VDD
VREF
RTH
GND
ISL88001
RSENSE
VOUT
PMOS
Q3
VINT
THERMISTOR
RINT
VREF
8-BIT GP
DAC
VDAC
HEATER
GND
CCOMP
ISL25700
FIGURE 1. V DD HOLD OFF CIRCUIT
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AN1825.0
February 20, 2013
Application Note 1825
Figure 2 is an oscilloscope shot of the resulting circuit's
waveforms. VIN (Blue) is allowed to ramp slowly to 15V at a rate
slower than the minimum 0.2V/ms. It is held off by the ISL88001
until VIN reaches ~2.92V. In this case, by the time VIN reaches the
threshold and the Gate of the N-channel FET (Purple) causes Q1
to turn on, VIN has already reached ~11.5V and is applied to the
ISL25700 and Q3 (Green). No non-volatile memory loss was
noted.
14
VOLTAGE (V)
2.5
VDD ISL25700 (Q3)
2.0
VDD ISL88001
1.5
1.0
0.5
Q1 GATE
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
FIGURE 3. SCOPE SHOT OF HOLD OFF CIRCUIT WAVEFORMS
(VIN RAMPS 0V TO 3.1V)
VDD ISL88001
Conclusions
VDD ISL25700 (Q3)
6
It has been confirmed in the lab that the ISL25700 will have
non-volatile memory loss issues if the min and max ramp rates
are violated which could result in circuit damage. The only time
memory loss was confirmed was from 0V to 3V.
4
2
0
-2
VIN
3.0
TIME (100ms PER/DIV)
VIN
12
8
3.5
-0.5
16
10
This experiment was also repeated for a third and final time but
this time VDD was very slowly ramped by hand to verify that
having a threshold of ~2.92V would not cause any memory loss
issues.
VOLTAGE (V)
Once VIN reaches ~2.92V, the reset output goes high and turns
on the N-channel MOSFET, Q1, which in turn turns on the
P-channel MOSFET, Q2, and allows VIN to be applied to both the
ISL25700 and the controlled P-channel MOSFET, Q3. A dual
complimentary MOSFET pair, NTGD4167C, was used for testing
the circuit due to the small size, low cost and good rDS(ON)
performance. Any heating in the MOSFET pair will be
compensated by the ISL25700.
Q1 GATE
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
TIME (100ms PER/DIV)
FIGURE 2. SCOPE SHOT OF HOLD OFF CIRCUIT WAVEFORMS
(VIN RAMPS 0V TO 15V)
In most OCXO applications, the actual ramp rate will fall between
the minimum and maximum limit, however, the minimum ramp
rate can often be violated in evaluation in the lab. It is
recommended that a VDD hold off circuit, similar to Figure 1, be
implemented to prevent memory loss and/or circuit damage.
In order to verify that VIN is being held off till it reaches ~2.92V,
the experiment was repeated but VIN was limited to a maximum
of 3.1V. Figure 3 shows the resulting waveforms. It is clear that
VIN is held off from being applied to the ISL25700 and Q3 until
after the threshold is reached. No non-volatile memory loss was
noted.
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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AN1825.0
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