AN2027: CompZL User Guide

CompZL™ User’s Guide
Application Note
Introduction
CompZL is a powerful, easy-to-use software tool
that enables optimization of Proportional - Integral
- Derivative (PID) compensation parameters for
any of Zilker Labs’ Digital-DC™ power
conversion products for a specific power stage
schematic design. Automatic optimization mode
predicts the optimal PID settings based on realworld performance criteria, and manual
optimization mode enables the user to adjust the
compensation performance based on actual
laboratory measurements using an intuitive
process.
M3
S3
A2
AN2027.0
May 01, 2009
This application note will discuss the methodology
for obtaining the required PID settings using
automatic optimization mode and manual mode
and will offer an example scenario for
comparison.
User Console
The CompZL tool is based on a simple yet
powerful user console (see Figure 1). This
console allows the designer to accurately model
their power stage schematic and enter desired
performance criteria relative to loop compensation
as well as to view the predicted results graphically
and with specific output data.
M2
A1
A4
S2
S1
M1
M3
S4
A3
A4
Figure 1. CompZL User Console
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Power Stage Model Setup
In order to predict the correct compensation
settings, the power stage schematic must first be
configured to include models of the components
used in the converter circuit.
4. Double-click the output capacitor and adjust its
capacitance value to match the value of the actual
capacitor selected. Double-click the inductive and
resistive elements of the capacitor and enter the
appropriate values individually. These values
should match the parameters provided by the
component supplier at the selected switching
frequency, DC Bias and temperature.
Upon start-up, CompZL will include an example
schematic from which the actual schematic model
can be derived. This initial schematic includes a
pair of synchronous MOSFETs, an output
inductor, and an output capacitor. The parasitic
resistance element of the inductor and
inductive/resistive elements of the capacitors are
also included for accuracy.
5. Click the Add Capacitor button to add additional
capacitors to the model. Enter the desired values
into the pop-up window and then click OK.
The value of any component may be modified by
either double-clicking on the component
(including the input voltage source and load) and
entering the desired value in the pop-up window
or by clicking once on the component and using
the slider bar (S4) to adjust the component value.
System Constraints and Output
Results
6. Click the Add External Capacitor button to add a
transmission line model and additional capacitors
external to the transmission line. Click OK when
done.
CompZL will accept several system constraints as
the basis for calculation of the PID compensation
settings.
The following steps may be followed to configure
the power stage schematic:
•
Switching Frequency in Hz (S2)
•
Desired phase margin in Degrees (S3)
1. Set the input source. Use the slider bar (S4) or
double-click the input source to select the
appropriate input voltage if different from the
default.
•
Desired gain margin in dB (S3)
•
Desired crossover frequency in Hz (S3)
2. Double-click the upper MOSFET and enter the
equivalent RDSON value of the MOSFETs selected
for the actual circuit. Repeat for the lower
MOSFET.
3. Double-click the output inductor and enter the
value of the inductance to match the selected
component’s inductance at the selected load
current and switching frequency. Best results are
generally achieved using the average of the
minimum and nominal inductance values. Doubleclick the inductor resistive element and adjust the
value to match the ESR of the inductor at the
selected load current and switching frequency.
2
Given these system constraints, the optimization
engine will attempt to match the desired phase
margin, gain margin, and crossover frequency.
The predicted values are displayed individually
(A2) and a graphical representation of the closedloop Bode plot (A3) is created.
The
corresponding PID compensation values A, B, and
C (A4) are also displayed on screen so they can be
loaded into the appropriate Digital-DC device.
Additionally, the power stage schematic screen
will display text related to the status of the power
stage and the status of the PID taps. If any of the
input constraints are varied sufficiently to cause a
new optimization process, the screen will display
the message “Taps are not optimal.”
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Automatic Optimization Mode
Once the power train schematic model is correctly
configured and the input constraints have been
entered, clicking the Optimize button (A1) will
initialize the internal automatic optimization
mode. This mode uses an internal optimization
routine to produce the best fit of phase margin,
gain margin, and crossover frequency for the
selected power train and switching frequency. The
optimization algorithm adjusts the complex
compensation zeroes to produce a phase response
that is as flat as possible while achieving the gain
required to meet all three conditions.
Once the best fit compensation settings have been
calculated, the PID taps will be displayed in green
text and the Power Train Schematic screen will
reflect optimal tap settings.
The PID
compensation values (A4) will be presented in red
text if they have not yet been optimized; once the
optimization routine has been run they will be
displayed in green text. The Actual Crossover
frequency field will also be displayed in green
text.
It should be noted that the automatic optimization
mode will attempt to optimize the compensator
response based on the power stage circuit model
entered by the user. Components often change
their characteristic behavior as the switching
frequency is varied; accordingly, the parasitic
characteristics of each device should be modified
when the switching frequency is modified. Most
component data sheets provide the device
characteristics versus frequency.
It is also
possible to measure the component characteristics
using a precision impedance analyzer.
Manual Cursor Adjust Mode
If a slightly different response characteristic is
desired after using the automatic optimization
mode, it is possible to adjust the compensator
zeros by moving the cursor on the Bode plot
manually until the desired response is observed
graphically. Clicking the check box (M1) just
above the Bode plot enables this mode. Dragging
the cursor (M3) enables changes in Q and
crossover frequency but does not adjust the gain of
the compensator. Gain adjustments can be made
by entering a new value in the Gc field (M2).
Manual Parametric Entry Mode
Manual parametric entry mode can be used to
tweak the compensator response slightly from the
output of automatic optimization mode or to
manually adjust the compensator gain, damping,
and frequency response based on actual Bode plot
measurements of the circuit.
This mode utilizes values entered into the input
fields (M2) for Gain (Gc), Q (damping), and
natural frequency to modify the compensator
response in an intuitive manner such that the user
can quickly determine the optimal compensation
values to achieve the desired Bode plot response.
Saving Your Work
It is possible to save the circuit configuration and
resultant compensation settings to a file for later
review. Clicking the Save button (A4) will open a
new window prompting the user to save the file in
.CZL format. Select a name and an appropriate
location for this file. The file may also be saved
by clicking the File menu (M3) and selecting Save
Project from the drop-down menu.
Manual Optimization Mode
The CompZL tool offers several methods of
manually adjusting the compensation settings to
optimize the circuit response.
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Loading Previously Saved Files
Any file that has been saved in the .CZL format
can also be loaded into CompZL at a later time by
clicking the Load button (A4) or by clicking the
File menu (M3) and selecting Load Project from
the drop-down menu.
Exporting PID Taps
Once the PID compensation settings have been
calculated, they may be saved to a file for loading
into the appropriate Digital-DC devices. Click the
File menu (M4), select Export PID Taps from the
drop-down menu, and input the desired file name
and location for the file. This file is saved in
.TXT format and can be loaded into a Digital-DC
device using the PowerNavigatorTM Evaluation
Software.
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Application Note 2027
Design Example
This section walks the designer through a typical
design procedure using CompZL. Refer also to
AN2011 (Component Selection Guide), AN2016
(Digital-DC Control Loop Compensation),
AN2035 (Compensation of DDC Products) and
AN2032 (NLR Configuration of DDC Products).
The following design constraints are given:
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage:
VIN = 12 V ± 2 V
Output Voltage:
VOUT = 1.5 V ± 5 %
Maximum Output Current:
IOmax = 30 A
Inductor Ripple Current:
ΔIL = 30%·IOmax = 9 A
Switching Frequency:
fsw = 300 kHz
Output Voltage Ripple:
ΔVOstatic = ±1%·VOUT = ±15 mV
Output Voltage Transient Response, pk-pk:
ΔVOtran-pp = ±5%·VOUT-nom = ±75mV
ΔIOtran = 50%-100%-50% = 15 A
dIO/dt = 2.5 A/μs
Target Phase Margin:
PMmin = 53°
Target Gain Margin:
GMmin = 6 dB
Target Crossover Frequency:
fxo = 15kHz
Target Efficiency:
η ≥ 88% @ 50%·IOmax
η ≥ 85%, 15%·IOmax ≤ IO ≤ IOmax
Ambient and PCB Temperatures:
TAMB = 45 °C
TPCB = 65 °C
Controller:
ZL2006
Step 1 – Choose an inductor, considering the
effects on inductance of the initial tolerance, DC
bias and switching frequency. The maximum
current rating of the inductor should also be
greater than the maximum output current plus half
the ripple current.
The minimum desired
inductance is given by:
5
Lmin −des
Lmin −des
Lmin −des
⎛
⎞
V
⎜⎜1 − OUT ⎟⎟ ⋅VOUT
V
IN max ⎠
=⎝
ΔI L ⋅ f sw
⎛ 1.5V ⎞
⎟ ⋅1.5V
⎜⎜1 −
14V ⎟⎠
⎝
=
9 A ⋅ 300 kHz
= 0.496μH
The IHLP5050FDERR68M01 seems a good choice.
•
•
•
•
•
•
•
Nominal Inductance:
Lnom = 0.68 μH
Inductor Resistance:
DCR = 1.4 mΩ,
ESR @ 300kHz ≈ 14 mΩ
Inductor Current Rating:
ISAT = 60 A,
ITHERM = 35 A
Initial Tolerance:
δLtol = 20 %
DC Bias:
δLbias ≈ 10.3 %
Frequency:
δLfreq ≈ 5 %
Root-Sum-of-Squares of all deviations:
δLRSS = δLtol 2 + δLbias 2 + δL freq 2
δLRSS = (20% )2 + (10.3% )2 + (5% )2
δLRSS = 23.05%
•
Minimum Probable Inductance:
L min = L nom ⋅ (1 − δ L RSS )
L min = 0 . 5233 μ H
•
Maximum Probable Ripple / Peak Currents:
ΔI L max
ΔI L max
ΔI L max
1
2
⎛
⎞
V
⎜⎜1 − OUT ⎟⎟ ⋅ VOUT
V
IN max ⎠
=⎝
Lmin ⋅ f sw
⎛ 1.5V ⎞
⎜⎜1 −
⎟ ⋅ 1.5V
14V ⎟⎠
⎝
=
0.5233 μH ⋅ 300 kHz
= 8.531 A
ΔI L max = 4.266 A
I Lpeak = I O max + 12 ΔI L max
I Lpeak = 30 A + 4.266 A = 34.266 A
•
Inductance Value for CompZL:
Lcalc = ½ ( Lnom + Lmin ) = 0.6016 μH
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Step 2 – Choose an output capacitor solution
that satisfies the Output Voltage Ripple and
Transient specs and that has ripple current
capacity greater than the worst-case Inductor
Ripple Current. Since the Output Voltage
Transient Response was specified as peak-to-peak,
we first need to subtract the Output Voltage
Ripple budget and the controller’s regulation error
over line, load and temperature to determine our
actual budget for the transient response alone.
ΔVOtran-max = ΔVOtran-pp – ΔVOstatic – εreg
ΔVOtran-max = 5% – 1% – 1% = 3%
AN2011 outlines a method for selecting output
capacitors when a single type of output
capacitance is used. However, in this example,
the designer chooses to absorb some of the
inductor ripple current with ceramic capacitors
and provide additional bulk capacitance using
Aluminum Conductive Polymer technology. The
designer selects a 47 μF ceramic capacitor in a
1206 package and a 6.3 V, 820 μF Al-Poly
capacitor in a 10.3 mm x 10.3 mm x 12.2 mm SMT
can package. From electrical characteristics data
obtained from the ceramic capacitor supplier, the
designer learns the following parameters and deratings:
•
•
•
•
•
•
•
Equivalent Series Resistance
@ 300 kHz, 85 °C, 1.5 VDC :
ESRcer ≈ 1.56 mΩ
Equivalent Series Inductance:
ESLcer ≈ 1.13 nH
Ripple Current Rating for 20 °C rise:
Iac-cer ≈ 3.2 A
Initial Tolerance:
δCtol-cer = 20 %
DC Bias of 1.5 V:
δCbias-cer ≈ 10 %
AC Voltage of 30 mV:
δCac-cer ≈ 15 %
Temperature of 65 °C:
δCtemp-cer ≈ 20 %
6
•
Root-Sum-of-Squares of all deviations:
δC cer = δCtol −cer 2 + δCbias −cer 2 + δC ac −cer 2 + δCtemp−cer 2
δC cer = (20% )2 + (10% )2 + (15% )2 + (20% )2
δC cer = 33.54%
•
Minimum Probable Ceramic Capacitance:
Cmin − cer = Cnom − cer ⋅ (1 − δCcer )
Cmin − cer = 31.24 μF
From electrical characteristics data obtained from the
Al-Poly capacitor supplier, the designer learns the
following parameters and de-ratings:
•
•
•
•
•
•
Equivalent Series Resistance at 300 kHz:
ESRAl-Poly ≈ 10 mΩ
Equivalent Series Inductance at 300 kHz:
ESLAl-Poly ≈ 5 nH
Ripple Current Rating for 20 °C rise:
Iac-Al-Poly ≈ 5.5 A
Initial Tolerance:
δCtol-Al-Poly = 20 %
Temperature of 65 °C:
δCtemp-Al-Poly ≈ 15 %
Root-Sum-of-Squares of all deviations:
δC Al − Poly = δC tol − Al − Poly 2 + δC temp − Al − Poly 2
δC Al − Poly =
(20% )2 + (15% )2
δC Al − Poly = 25.00%
•
Minimum Probable Al-Poly Capacitance:
Cmin − Al − Poly = Cnom − Al − Poly ⋅ (1 − δC Al − Poly )
Cmin − Al − Poly = 615 μF
For multiple-type output capacitors, the simplest
and most accurate way to determine how many of
each type of capacitor to use is by simulation.
From simulation results, the designer determines
to use four ceramics and four Al-Polys to meet
ripple and transient specs. This equates to the
following:
•
•
Effective Ceramic Capacitance
Ceff-min-cer = 124.96 μF
ESReff-cer ≈ 0.39 mΩ
ESLeff-cer ≈ 0.2825 nH
Effective Al-Poly Capacitance
Ceff-min-Al-Poly = 2460 μF
ESReff- Al-Poly ≈ 2.5 mΩ
ESLeff- Al-Poly ≈ 1.25 nH
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Step 3 – Select MOSFETs that satisfy efficiency,
cost and availability requirements.
In this
example, the designer selects the Infineon
BSC030N03LS (x1 high-side) and BSC016N03LS
(x2 low-side).
Typical Drain-Source On-State Resistance,
BSC030N03LS: 3.8 mΩ @ VGS = 4.5V
BSC016N03LS: 1.8 mΩ @ VGS = 4.5V
Predicted efficiency is shown in Figure 2.
Figure 2. Predicted Efficiency
Step 4 – Enter Component Parameters and
Design Constraints into CompZL. It is very
important that these entries accurately reflect
actual component values under target bias
conditions to achieve good correlation between
predicted and measured results.
•
•
•
•
•
•
•
•
Vin = 12V
RDSon-HS = 3.8 mΩ
RDSon-LS = 1.8 mΩ / 2 = 0.9 mΩ
Lcalc = 0.6016 μH
RL = 14 mΩ
Capacitor Type 1:
C1 = 31.24 μF
ESRC1 = 1.56 mΩ
ESLC1 = 1.13 nH
QtyC1 = 4
Capacitor Type 2:
C2 = 615 μF
ESRC2 = 10 mΩ
ESLC2 = 5 nH
QtyC2 = 4
Vout = 1.5 V
7
•
•
•
•
Iout = ½ΔILmax = 4.266 A
fsw = 300 kHz
PMmin = 53°
GMmin = 6 dB
Step 5 – Compare Compensation Options and
make your selection.
Figure 3 and Figure 4 show results of CompZL’s
optimizer using both the under-damped and overdamped switch settings. These have the advantage
of extra gain in the mid-band while still meeting
phase margin requirements. The results of Figure
3 yield complex zeroes that more perfectly cancel
the complex poles of the output filter itself, but the
real zeroes of Figure 4 result in more mid-band
gain which may in practice yield better transient
response.
In Figure 5 and Figure 6, the compensator zeroes
have been manually adjusted to yield a straightline magnitude response and flat phase response
below crossover at load currents of one-half the
inductor ripple current and Imax, respectively, with
a significant increase in phase margin and a slight
reduction in gain margin (relative to Figure 3 and
Figure 4). These results might be used in an
adaptive compensation scenario.
Figure 7 uses the natural frequency of Figure 3
with a lower Q and compensator gain to yield
even more mid-band loop gain without sacrificing
bandwidth. This approach generally yields very
good transient response across the entire load
range.
The Next Step – Compensation Verification
and Optimization. CompZL uses a simplified
model and relies on accurate component
parameters provided by the designer to make
predictions of system performance. The actual
circuit will have higher-order effects, parasitic
impedances and complex component behaviors
that will cause differences between predicted and
measured results that increase with switching
frequency. Therefore, CompZL should be used
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Application Note 2027
for preliminary selection of compensation settings
and the designer should next verify and optimize
the compensation according to the procedure
outlined in AN2035 (Compensation of DDC
Products). Finally, the designer should follow the
procedure
outlined
in
AN2032
(NLR
Configuration of DDC Products) to select NLR
settings, if NLR is required for the application.
Figure 3. CompZL Under-Damped Optimizer Results
Figure 4. CompZL Over-Damped Optimizer Results
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Figure 5. CompZL Manual Results, Straight-Line Magnitude, Flat Phase, ½ΔILmax
Figure 6. CompZL Manual Results, Straight-Line Magnitude, Flat Phase, Imax
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Figure 7. CompZL Manual Results, with Mid-Band Gain Boost
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References
[1]
[2]
Revision History
AN2011 – Component Selection Guide, Zilker
Labs, 2007.
AN2016
–
Digital-DC
Control
Compensation, Zilker Labs, 2007.
Loop
[3]
AN2032 – NLR Configuration of DDC Products,
Zilker Labs, 2008.
[4]
AN2035 – Compensation of DDC Products,
Zilker Labs, 2008.
11
Date
Rev. #
June 2007
0.6
Initial Release
March 2008
1.0
Added Design Example
May 2009
AN2027.0
Assigned file number AN2027
to app note as this will be the
first release with an Intersil file
number. Replaced header and
footer with Intersil header and
footer. Updated disclaimer
information to read “Intersil and
it’s subsidiaries including Zilker
Labs, Inc.” No changes to
datasheet content.
Application Note Revision 5/01/2009
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Application Note 2027
Zilker Labs, Inc.
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Building A-100
Austin, TX 78746
Tel: 512-382-8300
Fax: 512-382-8329
www.zilkerlabs.com
© 2008, Zilker Labs, Inc. All rights reserved. Zilker Labs, Digital-DC, and the Zilker Labs Logo are trademarks
of Zilker Labs, Inc. All other products or brand names mentioned herein are trademarks of their respective holders.
Specifications are subject to change without notice. Please see www.zilkerlabs.com for updated information.
This product is not intended for use in connection with any high-risk activity, including without limitation, air
travel, life critical medical operations, nuclear facilities or equipment, or the like.
The reference designs contained in this document are for reference and example purposes only. THE REFERENCE DESIGNS ARE PROVIDED "AS IS" AND "WITH ALL FAULTS" AND INTERSIL AND IT’S
SUBSIDIARIES INCLUDING ZILKER LABS, INC. DISCLAIMS ALL WARRANTIES, WHETHER
EXPRESS OR IMPLIED. ZILKER LABS SHALL NOT BE LIABLE FOR ANY DAMAGES, WHETHER
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designs is at your own risk and you agree to indemnify Intersil and it’s subsidiaries including Zilker Labs, Inc.
for any damages resulting from such use.
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