Applications of the CA3080 High-Performance Operational Transconductance Amplifiers Application Note November 1996 AN6668.1 Introduction The CA3080 and CA3080A are similar in generic form to conventional operational amplifiers, but differ sufficiently to justify an explanation of their unique characteristics. This new class of operational amplifier not only includes the usual differential input terminals, but also contains an additional control terminal which enhances the device's flexibility for use in a broad spectrum of applications. The amplifier incorporated in these devices is referred to as an Operational Transconductance Amplifier (OTA), because its output signal is best described in terms of the output-current that it can supply: Circuit Description A simplified block diagram of the OTA is shown in Figure 2. Transistors Q1 and Q2 comprise the differential input amplifier found in most operational amplifiers, while the lettered-circles (with arrows leading either into or out of the circles) denote “current-mirrors”. Figure 3A shows the basic type of currentmirror which is comprised of two transistors, one of which is diode-connected. In a current-mirror with similar geometries for QA and QB, the current I’ establishes a second current I whose value is essentially equal to that of I’. ∆i OUT Transconductance g M = ----------------∆e IN V+ The amplifier's output-current is proportional to the voltage difference at its differential input terminals. This Application Note describes the operation of the OTA and features various circuits using the OTA. For example, communications and industrial applications including modulators, multiplexers, sample-and-hold-circuits, gain control circuits and micropower comparators are shown and discussed. In addition, circuits have been included to show the operation of the OTA being used in conjunction with CMOS devices as post-amplifiers. Figure 1 shows the equivalent circuit for the OTA. The output signal is a current which is proportional to the transconductance (gM) of the OTA established by the amplifier bias current (IABC) and the differential input voltage (eIN). The OTA can either source or sink current at the output terminal, depending on the polarity of the input signal. V+ 7 2 OTA RIN eIN 2RO 6 gM x eIN IOUT = gM(±eIN) 2RO 3 7 Y INVERTING INPUT 2 AMPLIFIER BIAS CURRENT 5 IABC Z Q1 Q2 3 OUTPUT NON-INVERTING INPUT 6 W X 4 V- FIGURE 2. SIMPLIFIED DIAGRAM OF THE OTA This basic current-mirror configuration is sensitive to the transistor beta (β). The addition of another active transistor, shown in Figure 3B, greatly diminishes the circuit sensitivity to transistor beta and increases the current-source output impedance in direct proportion to the transistor beta. Current-mirror W (Figure 2) uses the configuration shown in Figure 3A, while mirrors X, Y, and Z are basically the version shown in Figure 3B. Mirrors Y and Z employ PNP transistors, as depicted by the arrows pointing outward from the mirrors. Appendix 1 describes current-mirrors in more detail. + gM (mS) = 19.2 IABC (mA) RO (MΩ) ≈ 7.5/IABC (mA) 4 5 VIABC FIGURE 1. BASIC EQUIVALENT CIRCUIT OF THE OTA The availability of the amplifier bias current (IABC) terminal significantly increases the flexibility of the OTA and permits the circuit designer to exercise his creativity in the utilization of this device in many unique applications not possible with the conventional operational amplifier. 1 I’ I QA I’ I QB QB QA V- V- FIGURE 3A. DIODE-CONNECTED TRANSISTOR PAIRED WITH TRANSISTOR 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 Application Note 6668 I’ I I’ Transistors Q10, Q11, and diode D6 of Figure 4 comprise the current-mirror “X” of Figure 2. Diodes D2 and D4 are connected across the base-emitter junctions of Q5 and Q8, respectively, to improve the circuit speed. The amplifier output signal is derived from the collectors of the “Z” and “X” current-mirror of Figure 2, providing a push-pull Class A output stage that produces full differential gM. This circuit description applies to both the CA3080 and CA3080A. The CA3080A offers tighter control of gM and input offset voltage, less variation of input offset voltage with variation of IABC and controlled cut-off leakage current. In the CA3080A, both the output and the input cut-off leakage resistances are greater than 1,000MΩ. I I I V- V- FIGURE 3B. IMPROVED VERSION: EMPLOYS AN EXTRA TRANSISTOR FIGURE 3. BASIC TYPES OF CURRENT MIRRORS 10kΩ Figure 4 is the complete schematic diagram of the OTA. The OTA employs only active devices (transistors and diodes). Current applied to the amplifier-bias-current terminal, IABC, establishes the emitter current of the input differential amplifier Q1 and Q2 . Hence, effective control of the differential transconductance (gM) is achieved. V+ 2 10kΩ CHANNEL #1 INPUT V+ 7 D3 3 - OTA AMP 1 CA3080 + 4 5 V- D5 150pF Q6 INVERTING INPUT 2 Q1 D4 Q9 10kΩ CHANNEL #2 INPUT 3 Q2 OUTPUT 6 NONINVERTING INPUT 3 TO TERM 5 AMP 1 Q10 AMPLIFIER BIAS-CURRENT - 7 OTA AMP 2 CA3080 + 4 5 V- 6 V+ = 5V V- = -5V (NO SUPPLY BYPASSING SHOWN) IABC V+ Q3 5 VABC 620Ω V+ 2 Q8 MULTIPLEXED OUTPUT IABC Q7 Q5 6 10kΩ Q4 D2 7 Q11 D1 D6 V4 FIGURE 4. SCHEMATIC DIAGRAM OF OTA TYPES CA3080 AND CA3080A The gM of a differential amplifier is equal to: qαI C ------------2KT (see Reference 2 for derivation) where q is the charge on an electron, α is the ratio of collector current to emitter current of the differential amplifier transistors, (assumed to be 0.99 in this case), IC is the collector current of the constantcurrent source (IABC in this case), K is Boltzman's constant, and T is the ambient temperature in degrees Kelvin. At room temperature, gM = 19.2 x IABC, where gM is in mS and IABC is in milliamperes. The temperature coefficient of gM is approximately -0.33%/oC (at room temperature). Transistor Q3 and diode D1 (shown in Figure 4) comprise the current mirror “W” of Figure 2. Similarly, transistors Q7, Q8 and Q9 and diode D5 of Figure 4 comprise the generic current mirror “Z” of Figure 2. Darlington-connected transistors are employed in mirrors “Y” and “Z” to reduce the voltage sensitivity of the mirror, by the increase of the mirror output impedance. 2 CLOCK INPUT Q 36kΩ DTL OR T2L FLIP-FLOP 2N4037 Q 36kΩ FIGURE 5. SCHEMATIC DIAGRAM OF OTAs IN A TWOCHANNEL LINEAR TIME-SHARED MULTIPLEXER CIRCUIT Applications Multiplexing The availability of the bias current terminal, IABC, allows the device to be gated for multiplexer applications. Figure 5 shows a simple two-channel multiplexer system using two CA3080 OTA devices. The maximum level-shift from input to output is low (approximately 2mV for the CA3080A and 5mV for the CA3080). This shift is determined by the amplifier input offset voltage of the particular device used, because the open-loop gain of the system is typically 100dB when the loading on the output of the CA3080A is low. To further increase the gain and reduce the effects of loading, an additional buffer and/or gainstage may be added. Methods will be shown to successfully perform these functions. Application Note 6668 In this example ±5V power-supplies were used, with the IC flipflop powered by the positive supply. The negative supply-voltage may be increased to -15V, with the positive-supply at 5V to satisfy the logic supply voltage requirements. Outputs from the clocked flip-flop are applied through PNP transistors to gate the CA3080 amplifier-bias-current terminals. The grounded-base configuration is used to minimize capacitive feed-through coupling via the base-collector junction of the PNP transistor. Another multiplexer system using the OTAs clocked by a CMOS flip-flop is shown in Figure 6. The high output voltage capability of the CMOS flip-flop permits the circuit to be driven directly without the need for PNP level-shifting transistors. V+ 10kΩ 7 2 10kΩ 3 10kΩ OTA AMP 1 + 4 5 V- 6 MULTIPLEXED OUTPUT 150pF 7 V+ 2 10kΩ 3 V+ = 10V, V- = -10V (NO SUPPLY BYPASSING SHOWN) 14 0V CLOCK INPUT -10V 2kΩ 7 6 6 TO TERM 5 AMP 1 4 VDD VSS CL Q 1/2 CD4013A 5 D Q 3 620Ω FIGURE 7. VOLTAGE WAVEFORMS FOR CIRCUIT OF FIGURE 6 OTA AMP 2 + 4 5 V- V- Top Trace: Multiplexed Output; 1V/Div., 100µs/Div. Bottom Trace: Time Expansion of Switching Between Inputs; 2V/Div., 5µs/Div. 1 IABC 82kΩ TO TERM 5 AMP 2 IABC 82kΩ 2 FIGURE 6. SCHEMATIC DIAGRAM OF A TWO-CHANNEL LINEAR MULTIPLEXER SYSTEM USING A CMOS FLIP-FLOP TO GATE TWO OTAs A simple RC phase-compensation network is used on the output of the OTA in the circuits shown in Figures 5 and 6. The values of the RC-network are chosen so that: Top Trace: Output; 1V/Div., 100µs/Div. Bottom Trace: Voltage Expansion of Output; 1mV/Div., 100µs/Div. FIGURE 8. VOLTAGE WAVEFORMS FOR CIRCUIT OF FIGURE 6 1 ---------------- ≅ 2MHz. 2πRC Sample-and-Hold Circuits This RC network is connected to the point shown because the lowest-frequency pole for the system is usually found at this point. Figure 7 shows an oscilloscope photograph of the multiplexer circuit functioning with two input signals. Figure 8 shows an oscilloscope photograph of the output of the multiplexer with a 6VP-P, sine wave signal (22kHz) applied to one amplifier and the input to the other amplifier grounded. This photograph demonstrates an isolation of at least 80dB between channels. 3 An extension of the multiplex system application is a sampleand-hold circuit (Figure 9), using the strobing characteristics of the OTA amplifier bias-current (ABC) terminal as a means of control. Figure 9 shows the basic system using the CA3080A as an OTA in a simple voltage-follower configuration with the phase-compensation capacitor serving the additional function of sampled-signal storage. The major consideration for the use of this method to “hold” charge is that neither the charging amplifier nor the signal readout device significantly alter the charge stored on the capacitor. The CA3080A is a particularly suitable capacitor-charging amplifier because its output resistance is more than 1000MΩ under cut-off conditions, and the loading on the storage capacitor during the Application Note 6668 hold-mode is minimized. An effective solution to the read-out requirement involves the use of a 3N138 insulated-gate fieldeffect transistor (MOSFET) in the feedback loop. This transistor has a maximum gate-leakage current of 10pA; its loading on the charge “holding” capacitor is negligible. The open-loop voltage-gain of the system (Figure 9) is approximately 100dB if the MOSFET is used in the source-follower mode with the CA3080A as the input amplifier. The open-loop output impedance (1/gM) of the 3N138 is approximately 220Ω because its transconductance is about 4,600µS at an operating current of 5mA. When the CA3080A drives the 3N138, the closed loop operational-amplifier output impedance characteristic is: Z O ( OPEN-LOOP ) Z OUT ≅ ------------------------------------------------------------------------------------------A ( OPEN-LOOP VOLTAGE-GAIN ) 220Ω 220Ω ≅ ----------------- ≅ --------------- ≅ 0.0022Ω 5 100dB 10 Top Trace: Sampled Signal 1V/Div., 20µs/Div. Center Trace: Top Portion of Upper Signal; 1V/Div., 2µs/Div. Bottom Trace: Sampling Signal; 20V/Div., 20µs/Div. 2.0kΩ 2 OTA CA3080 INPUT 2.0kΩ 0.01µF 7 - 3 + 4 30kΩ -15V HOLD 3N138 OUTPUT 6 R 5 SAMPLE 0V FIGURE 10. WAVEFORMS FOR CIRCUIT OF FIGURE 9 V+ =15V 120pF 0.01µF 220Ω 300pF C 3kΩ IABC 480µA STORAGE AND PHASE COMPENSATION NETWORK V- = -15V Figure 12 shows a dual-trace photograph of a triangular signal being “sampled-and-held” for approximately 14ms with a 300pF storage capacitor. The center trace (expanded to 20mV/Div.) shows the worst-case “tilt” for all the steps shown in the upper trace. The total equivalent leakage current in this case is only 170pA (I = C dv/dt). Figure 13 is an oscilloscope photograph of a ramp voltage being sampled by the “sample-and-hold” circuit of Figure 9. The input signal and sampled-output signal are superimposed. The lower trace shows the sampling signal. Data shown in Figure 13 were recorded with supply voltages of ±10V and the series input resistor at terminal 5 was 22kΩ. FIGURE 9. SCHEMATIC DIAGRAM OF OTA IN A SAMPLEAND-HOLD CIRCUIT Once the signal is acquired, variation in the stored-signal level during the hold-period is of concern. This variation is primarily a function of the cutoff leakage current of the CA3080A (a maximum limit of 5nA), the leakage of the storage element, and other extraneous paths. These leakage currents may be either “positive” or “negative” and, consequently, the stored-signal may rise or fall during the “hold” interval. The term “tilt” is used to describe this condition. Figure 11 shows the expected pulse “tilt” in microvolts versus time for various values of the compensation/storage capacitor. The horizontal axis shows three scales representing leakage currents of 50nA, 5nA, 500pA. 4 100K HOLD PERIOD (µs) Figure 10 shows a “sampled” triangular signal. The lower trace in the photograph is the sampling signal. When this signal goes negative, the CA3080A is cutoff and the signal is “held” on the storage capacitor, as shown by the plateaus on the triangular waveform. The center trace is a time expansion of the top-most transition (in the upper trace) with a time scale of 2µs/Div. 1000K 10K 1K 100 10 1 1 10 100 C= µF 10 F 3µ F 1µ F µ 0.3 F µ 0.1 F 3µ . 0 0 µF 1 0 0. pF 00 30 0pF 0 10 F 0p 30 pF 0 0 1 pF 30 F p 10 10 100 1K 100 1K 10K 1K 10K 100K THIS SCALE FOR 500pA 5nA 50nA LEAKAGE 10K 100K 1000K PULSE TILT (µV) FIGURE 11. “TILT” IN “HELD” VOLTAGE vs HOLD TIME Application Note 6668 Top Trace: Input and Sampled Output Superimposed; 100mV/Div., 100ns/Div. Bottom Trace: Sampling Signal; 20V/Div., 100ns/Div. Top Trace: Sampled Signal; 1V/Div., 20ms/Div. Center Trace: Worse Case Tilt; 20mV/Div., 20ms/Div. FIGURE 12. “TRIANGULAR-VOLTAGE” BEING SAMPLED BY CIRCUIT OF FIGURE 9 FIGURE 14. “TRIANGULAR-VOLTAGE” BEING SAMPLED BY CIRCUIT OF FIGURE 9 Figure 15 shows the basic circuit of Figure 9 implemented with a 2N4037 PNP transistor to minimize capacitive feedthrough. Figure 16 shows oscilloscope photographs taken with the circuit of Figure 15 operating in the sampling mode at supply voltage of ±15V. The 9.1kΩ resistor in series with the PNP transistor emitter establishes amplifier-bias-current (IABC) conditions similar to those used in the circuit of Figure 9. 2.0kΩ V+ = 15V 120pF 2 OTA CA3080 INPUT 2.0kΩ 7 - 3 + Top Trace: Input and Output Superimposed; 1V/Div., 2µs/Div. Bottom Trace: Sampling Signal; 20V/Div., 2µs/Div. FIGURE 13. “RAMP-VOLTAGE” BEING SAMPLED BY CIRCUIT OF FIGURE 9 DTL/TTL CONTROL LOGIC 5V 2N4037 OUTPUT 6 4 C 0.01µF 5 3N138 0.01µF 68Ω 300pF 3kΩ IABC STORAGE AND PHASE COMPENSATION NETWORK 0V 9.1kΩ V- = -15V In Figure 14, the trace of Figure 13 has been expanded (100mV/Div. and 100ns/Div.) to show the response of the sample-and-hold circuit with respect to the sampling signal. After the sampling interval, the amplifier overshoots the signal level and settles (within the amplifier offset voltage) in approximately 1µs. The resistor in series with the 300pF phase-compensation capacitor was adjusted to 68Ω for minimum recovery time. 5 FIGURE 15. SCHEMATIC DIAGRAM OF THE OTA IN A SAMPLEAND-HOLD CONFIGURATION (DTL/TTL CONTROL LOGIC) Application Note 6668 Top Trace: Input and Sampled Output Superimposed; 100mV/Div., 100ns/Div. Bottom Trace: Sampling Signal; 5V/Div., 100ns/Div. Top Trace: Output; 5V/Div., 2µs/Div. Center Trace: Differential Comparsion of Input and Output; 2mV/Div., 0V thru Center; 2µs/Div. Bottom Trace: Input; 5V/Div., 2µs/Div. FIGURE 16. CIRCUIT OF FIGURE 15 OPERATING IN SAMPLING MODE Figure 17 shows a multi-trace oscilloscope photograph of input and output signals for the circuit of Figure 9, operating in the linear mode. The lower portion of the photograph shows the input signal, and the upper portion shows the output signal. The amplifier slew-rate is determined by the output current and the capacitive loading: in this case the slew rate (dv/dt) = 1.8V/µs. The center trace in Figure 17 shows the difference between the input and output signals as displayed on a Tektronix 7A13 differential amplifier at 2mV/Div. The output of the amplifier system settles to within 2mV (the offset voltage specification for the CA3080A) of the input level in 1µs after slewing. Figure 18 is a curve of slew-rate versus amplifier-bias-current (IABC) for various storage/compensation capacitors. The magnitude of the current being supplied to the storage/compensation capacitor is equal to the amplifier-bias-current (IABC) when the OTA is supplying its maximum output current. Gain Control - Amplitude Modulation Effective gain control of a signal may be obtained by controlled variation of the amplifier-bias-current (IABC) in the OTA because its gM is directly proportional to the amplifierbias-current (IABC). For a specified value of amplifier-bias-current, the output current (IO) is equal to the product of gM and the input signal magnitude. The output voltage swing is the product of output current (IO) and the load resistance (RL). 6 FIGURE 17. CIRCUIT OF FIGURE 9 OPERATING IN THE LINEAR SAMPLE MODE Figure 19 shows the configuration for this form of basic gain control (a modulation system). The output signal current (IO) is equal to -gM x VX; the sign of the output signal is negative because the input signal is applied to the inverting input terminal of the OTA. The transconductance of the OTA is controlled by adjustment of the amplifier bias current, IABC. In this circuit the level of the unmodulated carrier output is established by a particular amplifier-bias-current (IABC) through resistor RM. Amplitude modulation of the carrier frequency occurs because variation of the voltage VM forces a change in the amplifier-bias-current (IABC) supplied via resistor RM. When VM goes positive, the bias current increases which causes a corresponding increase in the gM of the OTA. When the VM goes in the negative direction (toward the amplifierbias-current terminal potential), the amplifier-bias-current decreases, and reduces the gM of the OTA. 100 10 SLEW RATE (V/µs) Considerations of circuit stability and signal retention require the use of the largest possible phase-compensation capacitor, compatible with the required slew rate. In most systems the capacitor is chosen for the maximum allowable “tilt” in the storage mode and the resistor is chosen so that 1/2πRC ≅ 2MHz, corresponding to the first pole in the amplifier at an output current level of 500µA. It is frequently desirable to optimize the system response by the placement of a small variable resistor in series with the capacitor, as is shown in Figures 9 and 15. The 120pF capacitor shunting the 2kΩ resistor improves the amplifier transient response. 1.0 C 0.1 0.01 0.001 0.1 F 0p =1 F p 30 pF 0 10 0pF 30 0pF 0 pF 10 00 F 30 1µ 0.0 03µF 0. µF 0.1 1 10 100 AMPLIFIER BIAS CURRENT (IABC µA) 1000 FIGURE 18. SLEW RATE vs AMPLIFIER-BIAS-CURRENT (IABC) Application Note 6668 CARRIER FREQUENCY VX +6V 2 51Ω 7 OTA CA3080A 51Ω 3 47kΩ MODULATING VFREQUENCY VM + 4 5 IABC -6V IO IO = gM VX RL AMPLITUDE MODULATED OUTPUT NPN transistor-array as an input emitter-follower, with the three remaining transistors of the transistor-array connected as a current-source for the emitter followers. VX +6V 6 3 47kΩ RM 7 - AM OUTPUT OTA CA3080A 51Ω V+ 100kΩ 2 51Ω 5.1kΩ + 6 5.1kΩ 4 5 -6V -6V +6V IABC 100kΩ VM 2N4037 FIGURE 19. AMPLITUDE MODULATOR CIRCUIT USING THE OTA 5.1kΩ 24kΩ As discussed earlier, gM = 19.2 x IABC, where gM is in millisiemens when IABC is in milliamperes. In this case, IABC is approximately equal to: +6V FIGURE 20. AMPLITUDE MODULATOR USING OTA CONTROLLED BY PNP TRANSISTOR V M – ( V- ) ------------------------- = I ABC RM VX IO = –gM VX +15V 2 51Ω g M V X = ( 19.2 ) ( I ABC ) ( V X ) – 19.2 [ V M – ( V- ) ]V X I O = -----------------------------------------------------RM 100kΩ 19.2 ( V X ) ( V- ) 19.2 ( V X ) ( V M ) I O = ------------------------------------ – -------------------------------------RM RM There are two terms in the modulation equation: the first term represents the fixed carrier input, independent of VM and the second term represents the modulation, which either adds to or subtracts from the first term. When VM is equal to the V- term, the output is reduced to zero. 3 + 4 6 5.1kΩ 5 47kΩ -15V +15V IABC +15V VM AM OUTPUT OTA CA3080A 51Ω -15V 7 - CA3018A 10kΩ 2N4037 +15V 75kΩ 1.3MΩ +6V In the preceding modulation equations the term, -15V V ABC ( 19.2 ) ( V X ) --------------RM FIGURE 21. AMPLITUDE MODULATOR USING OTA CONTROLLED BY PNP AND NPN TRANSISTORS involving the amplifier-bias-current terminal voltage (VABC) (see Figure 4 for VABC) was neglected. This term was assumed to be small because VABC is small compared with Vin the equation. If the amplifier-bias-current terminal is driven by a current-source (such as from the collector of a PNP transistor), the effect of VABC variation is eliminated and transferred to the involvement of the PNP transistor base-emitter junction characteristics. Figure 20 shows a method of driving the amplifier-bias-current terminal to effectively remove this latter variation. The 100kΩ potentiometer shown in these schematics is used to null the effects of amplifier input offset voltage. This potentiometer is adjusted to set the output voltage symmetrically about zero. Figures 22A and 22B show oscilloscope photographs of the output voltages obtained when the circuit of Figure 19 is used as a modulator for both sinusoidal and triangular modulating signals. This method of modulation permits a range exceeding 1000:1 in the gain, and thus provides modulation of the carrier input in excess of 99%. The photo in Figure 22C shows the excellent isolation (>80dB at f = 100kHz) achieved in this modulator during the “gated-off” condition. If an NPN transistor is added to the circuit of Figure 20 as an emitter-follower to drive the PNP transistor, variations due to base-emitter characteristics are considerably reduced due to the complementary nature of the NPN base-emitter junctions. Moreover, the temperature coefficients of the two base-emitter junctions tend to cancel one another. Figure 21 shows a configuration using one transistor in the CA3018A 7 Four-Quadrant Multipliers A single CA3080A is especially suited for many lowfrequency, low-power four-quadrant multiplier applications. The basic multiplier circuit of Figure 23 is particularly useful for waveform generation, doubly balanced modulation, and other signal processing applications, in portable equipment, Application Note 6668 where low-power consumption is essential and accuracy requirements are moderate. The multiplier configuration is basically an extension of the previously discussed gaincontrolled configuration (Figure 19). To obtain a four-quadrant multiplier, the first term of the modulation equation (which represents the fixed carrier) must be reduced to zero. This term is reduced to zero by the placement of a feedback resistor (R) between the output and the inverting input terminal of the CA3080A, with the value of the feedback resistor (R) equal to 1/gM. The output current is IO = gM (-VX) because the input is applied to the inverting terminal of the OTA. The output current due to the resistor (R) is VX/R. Hence, the two signals cancel when R = 1/gM. The current for this configuration is: -19.2 V X V M I O = --------------------------------, and V M = V Y RM The output signal for these configurations is a current which is best terminated by a short-circuit. This condition can be satisfied by making the load resistance for the multiplier output very small. Alternatively, the output can be applied to a current-to-voltage converter as shown in Figure 24. TIME (50µs/DIV.) Top Trace: Modulation Input (20V) Bottom Trace: Amplitude Modulated Output; 500mV/Div. FIGURE 22B. RESPONSE FOR TRIANGLE WAVE MODULATION In Figure 23, the current “cancellation” in the resistor R is a direct function of the OTA differential amplifier linearity. In the following example, the signal excursion is limited to ±10mV to preserve this linearity. Greater signal-excursions on the input terminal will result in a significant departure from linear operation (which may be entirely satisfactory in many applications). TIME (50µs/DIV.) Top Trace: Gated Output; 1V/Div. Bottom Trace: Voltage Expansion Of Above Signal Showing No Residual; 1mv/Div. FIGURE 22C. RESPONSE FOR SQUARE WAVE MODULATION FIGURE 22. AMPLITUDE MODULATOR CIRCUIT OF FIGURE 19 WITH RM = 40kΩ, VS = ±10V TIME (50µs/DIV.) Top Trace: Modulation Input (≅ 20VP-P) Center Trace: Amplitude Modulated Output; 500mV/Div. Bottom Trace: Expanded Output to Show Depth of Modulation; 20mV/Div. 2 VX R = 1/gM OTA CA3080A FIGURE 22A. RESPONSE FOR SINE WAVE MODULATION 3 RM 6 IO ≅ -K VX VY + 5 IABC VY FIGURE 23. BASIC FOUR QUADRANT ANALOG MULTIPLIER USING AN OTA 8 Application Note 6668 ANALOG MULTIPLIER CA3080A RF IO X Y VX OP AMP CA3741CT OTA EOUT = - IO RF 2 5.1Ω 7 - OUTPUT OTA CA3080A 5.1Ω 3 24kΩ 100Ω 150kΩ +15V 250kΩ 5.1kΩ + 6 4.7MΩ 4 5 -15V V+ -15V V- VY 200kΩ FIGURE 24. OTA ANALOG MULTIPLIER DRIVING A CURRENTTO-VOLTAGE CONVERTER Figure 25 shows a schematic diagram of the basic multiplier with the adjustments set-up to give the multiplier an accuracy of approximately ±7 percent full-scale. There are only three adjustments: 1) one is on the output, to compensate for slight variations in the current-transfer ratio of the current-mirrors (which would otherwise result in a symmetrical output about some current level other than zero); 2) the adjustment of the 20kΩ potentiometer establishes the gM of the system equal to the value of the fixed resistor shunting the system when the Y-input is zero; 3) compensates for error due to input offset voltage. Procedure for adjustment of the circuit: 1. a) Set the 1MΩ output-current balancing potentiometer to the center of its range b) Ground the X- and Y- inputs c) Adjust the 100kΩ potentiometer until a 0V reading is obtained at the output. 2. a) Ground the Y-input and apply a signal to the Xinput through a low source-impedance generator (it is essential that a low impedance source be used; this minimizes any change in the gM balance or zero-point due to the 50µA Y-input bias current). b) Adjust the 20kΩ potentiometer in series with Y-input until a reading of 0V is obtained at the output. This adjustment establishes the gM of the CA3080A at the proper level to cancel the output signal. The output current is diverted through the 510kΩ resistor. 3. a) Ground the X-input and apply a signal to the Y-input through a low source-impedance generator. b) Adjust the 1MΩ resistor for an output voltage of 0V. -15V +15V 100kΩ +15V 1MΩ 2N4037 2.2kΩ 62kΩ 20kΩ +15V FIGURE 26. SCHEMATIC DIAGRAM OF ANALOG MULTIPLIER USING OTA CONTROLLED BY A PNP TRANSISTOR Figure 26 shows the schematic of an analog multiplier circuit with a 2N4037 PNP transistor replacing the Y-input “current” resistor. The advantage of this system is the higher input resistance resulting from the current-gain of the PNP transistor. The addition of another emitter-follower preceeding the PNP transistor (shown in Figure 21) will further increase the current gain while markedly reducing the effect of the Vbe temperature-dependent characteristic and the offset voltage of the two base-emitter junctions. Figures 27A and 27B show oscilloscope photographs of the output signals delivered by the circuit of Figure 26 which is connected as a suppressed-carrier generator. Figures 28A and 28B contain photos of the outputs obtained in signal “squaring” circuits, i.e. “squaring” sine-wave and triangular- wave inputs. If ±15V power supplies are used (shown in Figure 26), both inputs can accept ±10V input signals. Adjustment of this multiplier circuit is similar to that already described above. There will be some interaction among the adjustments and the procedure should be repeated to optimize the circuit performance. VX +6V 510kΩ 5.1kΩ 10Ω 2 7 - OTA CA3080A 10Ω 3 24kΩ + OUTPUT 6 3.3MΩ 4 5 -6V -6V VY +6V -6V 100kΩ 20kΩ IABC +6V 1MΩ 91kΩ FIGURE 25. SCHEMATIC DIAGRAM OF ANALOG MULTIPLIER USING OTA 9 500mV/Div., 200µs/Div., Triangular Input: 700Hz; 5VP-P to VY Input Carrier Input: 30kHz; 13.5VP-P to VX Input FIGURE 27A. Application Note 6668 0V 0V 500mV/Div., 200µs/Div., Modulating Frequency: 700Hz; 5VP-P to VY Input Carrier Input: 21kHz; 13.5VP-P to VX Input Top Trace: Input to X And Y; 2V/Div., 1ms/Div. (200Hz) Bottom Trace: Output; 500mV/Div., 1ms/Div. (400Hz) FIGURE 27B. FIGURE 28A. FIGURE 27. WAVEFORMS OBSERVED WITH OTA ANALOG MULTIPLIER USED AS A SUPPRESSED CARRIER GENERATOR The accuracy and stability of these multipliers are a direct function of the power supply-voltage stability because the Yinput is referred to the negative supply-voltage. Tracking of the positive and negative supply is also important because the balance adjustments for both the offset voltage and output current are also referenced to these supplies. 0V Linear Multiplexer - Decoder A simple, but effective system for multiplexing and decoding can be assembled with the CA3080 shown in Figure 29. Only two channels are shown in this schematic, but the number of channels may be extended as desired. Figure 30 shows oscilloscope photos taken during operation of the multiplexer and decoder. A CA3080 is used as a 10µs delay“one-shot” multivibrator in the decoder to insure that the sample-and-hold circuit can sample only after the input signal has settled. Thus, the trailing edge of the “one-shot” output-signal is used to sample the input at the sample-andhold circuit for approximately 1µs. Figure 31 shows oscilloscope photos of various waveforms observed during operation of the multiplexer/decoder circuit. Either the Q or Q output from the flip-flop may be used to trigger the 10µs “one-shot” to decode a signal. 10 0V Top Trace: Input to X And Y; 2V/Div., 1ms/Div. (200Hz) Bottom Trace: Output; 500mV/Div., 1ms/Div. (400Hz) FIGURE 28B. FIGURE 28. WAVEFORMS OBSERVED WITH OTA ANALOG MULTIPLIER USED IN SIGNAL-SQUARING CIRCUITS Application Note 6668 MULTIPLEXER 3 CHANNEL #1 INPUT 10kΩ 2 +5V DECODER 7 + OTA CA3080A - 6 TRANSMISSION MEDIA 7 3 OTA CA3080 2kΩ 4 2 5 -5V 10kΩ - CL Q 1/2 CD4013A FLIP FLOP 2 D Q -5V 7 6 3kΩ 1 DECODED OUTPUT -5V 5 620Ω +5V 150pF 4 2N4037 Q1 500kΩ -5V IABC 62kΩ 82kΩ 82kΩ 20pF 18pF 2 10kΩ 3 1N914 68kΩ +5V +5V 5 10kΩ CHANNEL #2 INPUT 300pF IABC 14 3 3N138 270Ω 0.01µF 5 82kΩ 0V 6 4 2kΩ IABC 2.2kΩ 0.01µF + +5V 7 3 7 - OTA CA3080A 1N914 6 + 4 -5V 51pF FROM Q OR Q 2 1kΩ 10ms ONE - SHOT 5 OTA CA3080A + 6 4 10µs -5V FIGURE 29. TWO-CHANNEL MULTIPLEXER AND DECODER USING OTAs Top Trace: Input Signal; 1V/Div., 20ms/Div. Center Trace: Recovered Output; 1V/Div., 20ms/Div. Bottom Trace: Multiplexed Signals; 2V/Div., 20ms/Div. Top Trace: Input Signal; 1V/Div., 20ms/Div. Center Trace: Recovered Output; 1V/Div., 20ms/Div. Bottom Trace: Multiplexed Signals; 1V/Div., 20ms/Div. FIGURE 30. WAVEFORMS SHOWING OPERATION OF LINEAR MULTIPLEXER/SAMPLE-AND-HOLD DECODE CIRCUITRY (FIGURE 29) 11 Application Note 6668 Top Trace: Flip-flop Output; 5V/Div., 20µs/Div. Center Trace: “One-shot” Output; 5V/Div., 20µs/Div. Bottom Trace: Strobe Pulse At The Collector of Q1; 0.1V/Div., 20µs/Div. FIGURE 31A. WAVEFORMS CONTROLLING DECODER ENABLE 500µs/Div. FIGURE 31C. SAME AS FIGURE 31B BUT WITH EXPANDED TIME SCALE FIGURE 31. VARIOUS WAVEFORMS SHOWING THE OPERATION OF LINEAR MULTIPLEXER High-Gain, High-Current Output Stages Top Trace: Strobe Pulse at Q1; 0.5V/Div., 5ms/Div. Center Trace: Multiplexed Output With One Input at GND; 0.5V/Div., 5ms/Div. Bottom Trace: Decoded Output; 0.5V/Div., 5ms/Div. FIGURE 31B. WAVEFORMS SHOWING DECODER OPERATION 12 In the previously discussed examples, the OTA has been buffered by a single insulated-gate field-effect-transistor (MOSFET) shown in Figure 9. This configuration yields a voltage gain equal to the (gM) (RO) product of the CA3080, which is typically 142,000 (103dB). The output voltage and current-swing of the operational amplifier formed by this configuration (Figure 9) are limited by the 3N138 MOSFET performance and its source-terminal load. In the positive direction, the MOSFET may be driven into saturation; the source-load resistance and the MOSFET characteristics become the factors limiting the output-voltage swing in the negative direction. The available negative-going load current may be kept constant by the return of the source-terminal to a constant-current transistor. Phase compensation is applied at the interface of the CA3080 and the 3N138 MOSFET shown in Figure 9. Another variation of this generic form of amplifier utilizes the CD4007A (CMOS) inverter as an amplifier driven by the CA3080. Each of the three inverter/amplifiers in the CD4007A has a typical voltage gain of 30dB. The gain of a single CMOS inverter/amplifier coupled with the 100dB gain of the CA3080 yields a total forward-gain of about 130dB. Use of a two-stage CMOS amplifier configuration will increase the total open-loop gain of the system to about 160dB (100,000,000). Figures 32 through 35 show examples of these configurations. Each CMOS inverter/amplifier can sink or source a current of 6mA (Typ). In Figures 34 and 35, two CMOS inverter/amplifiers have been connected in parallel to provide additional output current. Application Note 6668 +6V +6V 14 5 INVERTING INPUT 2 7 - 13 OUTPUT CA3080 NON-INVERTING INPUT 3 6 4 + 6 8 7 -6V CD4007A. For greater output current capability, the remaining amplifiers in the CD4007A may be connected in parallel with the single stage shown. Precise timing and thresholds are assured by the stable characteristics of the input differential amplifier in the CA3080. Moreover, speed vs power consumption trade-offs may be made by adjustment of the IABC current to the CA3080. The quiescent power consumption of the circuits shown in Figure 37 is typically 6mW, but can be made to operate in the micropower region by suitable circuit modifications. V+ -6V V+ 1/3 CD4007A 14 FIGURE 32. OTA DRIVING CMOS INVERTER/AMPLIFIER IN OPEN-LOOP MODE The open-loop slew-rate of the circuit in Figure 32 is approximately 65V/µs. When compensated for the unity-gain voltage-follower mode, the slew-rate is about 1V/µs (shown in Figure 33). Even when the three inverter/amplifiers in the CD4007A are connected as shown in Figure 34, the openloop slew-rate remains at 65V/µs. A slew-rate of about 1V/µs is maintained with this circuit connected in the unity-gain voltage-follower mode, as shown in Figure 35. Figure 36 contains oscilloscope photos of input-output waveforms under small-signal and large-signal conditions for the circuits of Figures 33 and 35. These photos illustrate the inherent stability of the OTA and CMOS circuits operating in concert. INVERTING INPUT 2 3 NONINVERTING INPUT 13 - 5 2kΩ +6V OTA CA3080 + 6 6 VIN 2kΩ 2 OTA CA3080 - V- 7 50Ω 2.7Ω 0.1µF + 8 0.25µF OUTPUT 9 4 +6V 14 50µF 6 4 2kΩ +6V 13 6 OUTPUT FIGURE 34. OTA DRIVING TWO-STAGE CMOS INVERTER/AMPLIFIER IN OPEN-LOOP MODE 7 + N 8 V- 2 3 12 10 N 5 N 4 7 14 5 1 3 +6V 24kΩ 11 P P P 7 2 2kΩ - 11 P P P 24kΩ 2 13 5 OTA CA3080 3 + 0.1µF 4 1 3 6 6 N 5 N 12 10 N 8 OUTPUT 0.33Ω 7 INPUT 50µF 0.1µF 7 4 9 -6V 40µF -6V 1/3 CD4007A FIGURE 33. OTA DRIVING CMOS INVERTER/AMPLIFIER IN UNITY-GAIN CLOSED-LOOP MODE Precision Multistable Circuits The micropower capabilities of the CA3080, when combined with the characteristics of the CD4007A CMOS inverter/amplifiers, are ideally suited for use in connection with precision multistable circuits. In the circuits of Figures 32, 33, 34, and 35, for example, power-supply current drawn by the CMOS inverter/amplifier approaches zero as the output voltage swings either positive or negative, while the CA3080 current-drain remains constant. Figure 37 shows a variety of circuits that can be assembled using the CA3080 to drive one inverter/amplifier in the 13 -6V -6V FIGURE 35. OTA DRIVING TWO-STAGE CMOS INVERTER/AMPLIFIER IN UNITY GAIN CLOSEDLOOP MODE Application Note 6668 Top Trace: Input; 5V/Div., 100µs/Div. Bottom Trace: Output; 5V/Div., 100µs/Div. FIGURE 36A. LARGE SIGNAL RESPONSE FOR CIRCUIT IN FIGURE 33 Top Trace: Input; 5V/Div., 100µs/Div. Bottom Trace: Output; 5V/Div., 100µs/Div. FIGURE 36C. LARGE SIGNAL RESPONSE FOR CIRCUIT IN FIGURE 35 Top Trace: Input; 50mV/Div., 1µs/Div. Bottom Trace: Output; 50mV/Div., 1µs/Div. FIGURE 36B. SMALL SIGNAL RESPONSE FOR CIRCUIT IN FIGURE 33 Top Trace: Input; 50mV/Div., 1µs/Div. Bottom Trace: Output; 50mV/Div., 1µs/Div. FIGURE 36D. SMALL SIGNAL RESPONSE FOR CIRCUIT IN FIGURE 35 FIGURE 36. PERFORMANCE OF OTA DRIVING CMOS INVERTER/AMPLIFIER 14 Application Note 6668 1 f ≈ ------------------------------------------- 2R 1 2RCln ----------- + 1 R 2 R V+ 5kΩ V+ 100kΩ 14 7 3 C 0.01µF 13 OTA CA3080 2 V+ V- 5 + 6 6 - 8 1/3 CD4007A 7 V- 10kΩ R1 V- The schematic diagram of a micropower comparator is shown in Figure 38. Quiescent power consumption of this circuit is about 10µW (Typ). When the comparator is strobed “ON”, the CA3080A becomes active and consumes 420µW. Under these conditions, the circuit responds to a differential input signal in about 8µs. By suitably biasing the CA3080A, the circuit response time can be decreased to about 150ns, but the power consumption rises to 21mW. The differential amplifier input common-mode range for the circuit of Figure 38 is -1V to +10.5V. Voltage gain of the micropower comparator is typically 130dB. For example, a 5µV input signal will switch the output. 4 R2 Micropower Comparator V+ 10kΩ V+ FIGURE 37A. ASTABLE MULTIVIBRATOR 2 R1 --------------------- (V+ - V-) + V+ - V D R1 + R2 = RCln ------------------------------------------------------------------------V+ 10MΩ R V+ R1 V+ 100kΩ 100kΩ R2 T 7 2 56pF V- 13 OTA CA3080 + 3 4 VD 1N914 6 6 FIGURE 37B. MONOSTABLE MULTIVIBRATOR R1 Threshold = ± V S --------------------- R 1 + R 2 V+ V+ 100kΩ 5.1kΩ 1/3 CD4007A 2 + - 14 7 OTA CA3080 V- OUTPUT 14 V+ P 13 9 VSTROBE FIGURE 38. SCHEMATIC DIAGRAM OF MICROPOWER COMPARATOR USING THE CA3080A AND CMOS CD4007A Current Mirrors 7 V- 3 12 Appendix I V- R = R1||R2 N 8 8 1/3 CD4007A 5 7 6 V+ 5 - CD4007A 6 V+ = 12V V- = -2V 10kΩ 14 5 V- 1.3MΩ 10kΩ 1000pF OTA CA3080 3 + 4 IABC 10µA V+ C 10 7 - 11 13 6 6 8 7 R2 V- 10kΩ The basic current-mirror, described in the beginning of this note, in its rudimentary form, is a transistor with a second transistor connected as a diode. Figure A shows this basic configuration of the current-mirror. Q2 is a diode connected transistor. Because this diode-connected transistor is not in saturation and is “active”, the “diode” formed by this connection may be considered as a transistor with 100% feedback. Therefore, the base current still controls the collector current as is the case in normal transistor action, i.e., IC = β IB. If a current I1 is forced into the diode-connected transistor, the base-to-emitter voltage will rise until equilibrium is reached and the total current being supplied is divided between the collector and base regions. Thus, a base-to-emitter voltage is established in Q2 such that Q2 “sinks” the applied current I1. I1 I2 R1 10kΩ Q2 Q1 FIGURE 37C. THRESHOLD DETECTOR FIGURE 37D. MULTISTABLE CIRCUITS USING THE OTA AND CMOS INVERTER/AMPLIFIERS 15 FIGURE 39A. DIODE - TRANSISTOR CURRENT SOURCE Application Note 6668 If the base of a second transistor (Q1) is connected to the baseto-collector junction of Q2, shown in Figure 39A, Q1 will also be able to “sink” a current approximately equal to that flowing in the collector lead of the diode-connected transistor Q2. This assumes that both transistors have identical characteristics, a prerequisite established by the IC fabrication technique. The difference in current between the input current (I1) and the collector current (I2) of transistor Q1 , is due to the fact that the base-current for both transistors is supplied from I1. Figure 39B shows this current division, using a “unit” of base current (1) to each transistor base. This base current causes a collector current to flow in direct proportion to the β of each transistor. The ratio of the “sinking” current I2 to the input current I1 is therefore: Figure 39D shows a curve-tracer photograph of characteristics for the circuit of Figure 39B. No consideration in this discussion is given to the variation of the transistor (Q1) collector current as a function of its collector-to-emitter voltage. The output resistance characteristic of Q1 retains its similarity to that of a single transistor operating under similar conditions. An improvement in its output resistance characteristic can be made by the insertion of a diode-connected transistor in series with the emitter of Q1. I2 ---- = β/ ( β +˙ 2 ) . I1 Thus, as β increases, the output current (I2) approaches the input current (I1). The curves in Figure 39C show this ratio as a function of the transistor β. When the transistor β is equal to 100, for example, the difference between the two currents is only two percent. I1 I2 β+2 I2 β ----- = ------------I1 β+2 β β 2 Q2 Scale: Horizontal = 2V/Div. Vertical = 1mA/Div. Steps = 1mA/STEP Q1 1 1 FIGURE 39D. PHOTO SHOWING RESULTS OF FIGURE 39B CURRENT TRANSFER RATIO I2/I1 FIGURE 39B. DIODE - TRANSISTOR CURRENT SOURCE. ANALYSIS OF CURRENT FLOW 1.5 1.4 1.3 1.2 1.1 1.0 0.9 This diode-connected transistor (Q3 in Figure 39E) may be considered as a current-sampling diode that senses the emitter-current of Q1 and adjusts the base current Q1 (via Q2) to maintain a constant-current in I2. Because all controlling transistors are operated at relatively fixed voltages, the previously discussed effects due to voltage coefficients do not exist. The curve-tracer photograph of Figure 39F shows the improved output resistance characteristics of the circuit of Figure 39E. (Compare Figure 39D and 39F). 2 I2 β + 2β ---- = ----------------------------2 I1 β + 2β + 2 0.8 0.7 0.6 0.5 0.4 I2 β ---- = ------------I1 β+2 I1 I2 Q1 0.3 0.2 0.1 0 1 10 100 1000 Q2 Q3 TRANSISTOR BETA FIGURE 39C. CURRENT TRANSFER RATIO I2/I1 vs TRANSISTOR BETA 16 FIGURE 39E. DIODE - 2 TRANSISTOR CURRENT SOURCE Application Note 6668 Conclusions The Operational Transconductance Amplifier (OTA) is a unique device with characteristics particularly suited to applications in multiplexing, amplitude modulation, analog multiplication, gain control, switching circuitry, multivibrators, comparators, and a broad spectrum of micropower circuitry. The CA3080 is ideal for use in conjunction with CMOS ICs being operated in the linear mode. Acknowledgments The author is indebted to C. F. Wheatly for many helpful discussions. Valued contributions in circuit evaluation were made by A. J. Visioli Jr. and J. H. Klinger. Scale: Horizontal = 2V/Div. Vertical = 1mA/Div. Steps = 1mA/STEP FIGURE 39F. PHOTO SHOWING RESULTS OF FIGURE 39E Figure 39G shows the current-division within the mirror assuming a “unit” (1) of current in transistors (Q2 and Q3). The resulting current transfer ratio 2 β + 2β I 2 /I 1 = -----------------------------. 2 β + 2β + 2 Figure 39C shows this equation plotted as a function of beta. It is significant that the current transfer ratio (I2/I1) is improved by the β2 term, and reduces the significance of the 2β + 2 term in the denominator. I1 β+2 ------------β+1 β+2 β + ------------β+1 I2 β+2 β ------------- β + 1 Q1 β+2 β 2 Q2 β Q3 1 1 β+2 β ------------- 2 I2 β + 1 β + 2β ---- = ---------------------------- = ----------------------------2 I1 β+2 β + ------------- β + 2β + 2 β + 1 FIGURE 39G. CURRENT FLOW ANALYSIS OF FIGURE 39E All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. 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