AN9011: Synchronous Operation of Intersil Rad Hard SOS 64K Asynchronous SRAMs

Synchronous Operation of Intersil Rad Hard SOS
64K Asynchronous SRAMs
Application Note
June 1992
The HCS373 and HCTS373 are both fabricated with SOS
technology; each circuit is available hardened to 200K RADs
or 1M RADs, and has excellent single event immunity. The
addition of the latches will delay the address inputs to the
SRAMs by a maximum of 39ns (over temperature, VDD, and
1M RAD total dose), so system timing should be analyzed
accordingly. Even with the additional delay of the latches,
address access time is a maximum of 89ns (for a 50ns
SRAM access time).
E OR E1
E OR E1
LE
A0-A7
HCS373
The Intersil SOS 64K SRAMs provide excellent single event
and total dose hardness, and fast access and cycle times.
The HS-65643RH and HS-65647RH were designed as standard pinout asysnchronous circuits; they can, however, be
used in systems that require their speed and radiation resistance, but have been designed for synchronous memories.
The addition of two HCS373 or HCTS373 to latch the
address location on the falling edge of the chip enable signal
will make the HS-65643RH and HS-65647RH appear as
synchronous memories to the system. The only difference in
signal wiring need to use the asynchronous circuits it to
route the address lines through the 373’s and connect the E
or E1 signal to the 373’s LE pin as shown in Figure 1.
AN9011
D
A0-A7
Q
OE
HS-65643RH
OR
HS-65647RH
LE
A8-A15
OR
A8-A12
D
HCS373
TM
A8-A15
OR
A8-A12
Q
OE
FIGURE 1.
HS-65643RH, HS-65647RH Asynchronous Read Cycles
READ CYCLE I: W HIGH; G, E1 LOW
READ CYCLE II: W HIGH
TAVAX
TAVAX
TAVQV
A
ADDRESS 2
ADDRESS 1
TAXQX
TAVQV
E1
DATA 1
DATA 2
TELQV
TEHQZ
TELQX
Q
HS-65643RH, HS-6547RH Asynchronous Write Cycles
WRITE CYCLE I: LATE WRITE
WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E, E1
TAVAX
TAVAX
A
W
A
TWLWH
TAVWL
TWHAX
TAVEL
TELEH
TEHAX
W
E, E1
TDVWH
TWHQX
E1
TWHDX
TDVEH
TEHDX
D
D
TWLQZ
Q
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Application Note 9011
HS-65643RH, HS-65647RH Synchronous Operation
READ CYCLE
TAVQV
TELAX
TAVEL
TAVEL
A
VALID ADD
NEXT
TELEL
TELEH
TEHEL
E
ADD
TEHEL
HIGH
W
TEHQZ
TELQV
The address information is latched in the HSC373’s on the
falling edge of E or E1; minimum address setup and hold
time requirements at the SRAM must be met. After the required hold time, the addresses may change state without
affecting device operation. W must remain high throughout
the read cycle. After the data has been read, E or E1 may return high. This will force the output buffers into a high impedance mode after TEHQZ elapses.
TEHQZ
VALID DATA
OUT
DQ
TELQX
WRITE CYCLE
TELAX
TAVEL
TAVEL
A
VALID ADD
NEXT ADD
TELEL
TEHEL
TELEH
TEHEL
E
TWLEH
TWLWH
W
TELWH
TDVWH
DQ
The write cycle is initiated on the falling edge of E or E1
which latches the address information in the HCS373’s.
TDVWH and TWHDX at the SRAM inputs must be met for
proper device operation. If E or E1 rises before W rises, reference data setup and hold times to the E or E1 rising edge.
The write operation is terminated by the first rising edge of
W, E, or E1. After the minimum E high time (TEHEL), the
next cycle may begin. If a series of consecutive write cycles
are to be performed, the W line may be held low until all desired locations have been written. In this case, data setup
and hold times must be referenced to the rising edge of E or
E1.
TWHDX
VALID DATA IN
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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