A Spice-2 Subcircuit Representation For Power MOSFETs Using Empirical Methods Application Note October 1999 AN9209.2 Abstract Discussion An accurate power-MOSFET model is not widely available for CAD circuit simulation. This work provides a subcircuit model which is compatible with SPICE-2 software and MOSFET terminal measurements. SPICE-2 is the circuit simulation package of choice for this work because of its universal availability, despite its inherent limitations. These limitations are circumvented through circuit means. The subcircuit shown in Figure 1 is described in Table 1. All passive circuit elements are constants. The very-high-gain JFET is used to simulate the dual-slope drain voltage vs time switching curve common to the power MOSFET.1,2 This effort models power-MOSFET terminal behavior consistent with SPICE-2 limitations; hence it will differ from the physical model as suggested by Wheatley, et al1, Ronan et al2 and others. We feel we have advanced prior efforts3 particularly in areas of third-quadrant operations, avalanchemode simulation, switching waveforms and diode recovery waveforms. C3 TABLE 1. EMPIRICAL INPUTS I(V meas.) RDRAIN D D1 G E1 DBODY - - JFET Depletion mode; areas factor = 1; B = 100KP (Figure 2); VTO = VPINCH (Figure 5); C’s = diode lifetime = RSERIES = 0; diode ideality factor = 1.0, IDSO = IE -20 BODY DIODE IS from Figure 4; Ideality Factor = 1.0; R from Figure 4 (must be very much greater than RD); C (from COSS); lifetime = best fit to TRR D1 IS = arbitrary; C = lifetime = 0; ideality factor = best low-current fit; R = best high-current fit D2 IS = 1E -8; C = lifetime = R = 0; ideality factor = 0.03 RS Figure 2. RDRAIN Figure 3. LS Approximately (5L) ln (4 L/d) nH; L and d are source wire inches. VPINCH VTO of JFET. VBRK Avalanche voltage. C1 From Figure 5. C2 Maximum from Figure 5. C3 Minimum from Figure 5. LSOURCE + - Enhancement mode; W = L = 1µm; KP (Figure 2); VTO (Figure 2); C’s = 0; IDSO = IE -12 VBREAK Vpinch D2 + MOSFET + C1 E1 The body diode cannot be properly modeled by the JFET gate-drain diode, hence DBODY. Conditions of Table 1 assure that most third-quadrant current flow is via DBODY. Avalanche breakdown is more accurately modeled by the clamp circuit containing D1. Table 1 in combination with Figures 2, 3, 4 and 5 provides the required empirical inputs. Table 2 lists the preferred algorithm for parameter extraction. C2 + If E1 exceeds VPINCH, errors will exist in the turn-on waveforms. The C2 discharge current-controlled current source remedies this situation in conjunction with the subcircuit containing D2. The D2 ideality factor was set at 0.03 to assure that E1 minus VPINCH does not exceed several millivolts. RSOURCE Vmeas. S FIGURE 1. SPICE-2 SUBCIRCUIT FOR POWER MOSFET SIMULATION NOTE: If the JFET source voltage, E1, is very low relative to its VPINCH voltage, the JFET is in a highly conductive state, tightly coupling C2 to the JFET drain. However, as the voltage E1 approaches VPINCH, the JFET operates in a constant-current mode, thereby permitting a much faster drain slew rate, which is determined primarily by C3. 1 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999. Application Note 9209 IDS RS RFP15N15 25 SLOPE ≈ RD + RS 20 SLOPE AT KP VDS > VGS (SATURATED REGIME) VDS (VOLTS) √IDS (AMPERES1/2) RFP15N15 15 10 5 4.0 VTHRESHOLD 5.0 6.0 VGS (VOLTS) 7.0 FIGURE 2. SQUARE ROOT OF DRAIN CURRENT vs GATE VOLTAGE DEFINES VTHRESHOLD, KP, AND RS 0 2 4 IDS (AMPERES) 6 FIGURE 3. DRAIN CURRENT vs DRAIN VOLTAGE WITH CONSTANT GATE VOLTAGE DEFINES “ON” RESISTANCE RFP15N15 RDRAIN = 10Ω IG = 1mA TEST CIRCUIT (SEE REF. 1) IMAX R RFP15N15 135 VGS = 0 9.0 q = 60mV/DECADE 6.0 90 VDS (VOLTS) SLOPE = KT VGS (VOLTS) LOG ID (AMPERES) SLOPE = IG/(C1 + C2 + C3) GATE PLATEAU VOLTAGE SLOPE ≈ IG/C2 45 3.0 SLOPE ≈ IG/C1 TRIAL Vpinch IDRDS ON IS 0 0 VDS (VOLTS) FIGURE 4. THIRD-QUADRANT OPERATION DEFINES IS AND R OF DIODE DBODY TABLE 2. PREFERRED ALGORITHM FOR PARAMETER EXTRACTION 1. Determine KP of lateral MOS 2. Determine VTH of lateral MOS 3. Determine C1 4. Determine C1 + C2 + C3 5. Determine RDS 6. Assign B of JFET = 100 x KP of lateral MOS 7. Use trial VPINCH 8. Use C2 (Maximum), C3 (Minimum) are curve-fit C’s 9. Adjust VPINCH to fix gate voltage plateau 2 20 40 TIME (µs) FIGURE 5. DRAIN AND GATE VOLTAGE vs TIME DETERMINE C1, C2, C3 AND VPINCH. Results Figure 6 and Figure 7 compare measured static data to calculated transfer curves and output curves. Calculated static-output curves are shown in Figure 8 and Figure 9 for third-quadrant range, including avalanche. Calculated switching data is compared to measured switching curves1,2 in Figure 10 and Figure 11. Calculated body-diode recovery curves are shown in Figure 12. Application Note 9209 30 MEASURED CALCULATED 20 RFP15N15 MEASURED 25 CALCULATED RFP15N15 IDS (AMPERES) IDS (AMPERES) 20 10 15 10 5 1.0 0.1 0 3.0 5.0 VGS (VOLTS) 0 7.0 FIGURE 6. DRAIN CURRENT vs GATE VOLTAGE (NOTE SQUARE ROOT SCALE) - MEASURED CURVE vs CALCULATED POINTS -1 VDS (VOLTS) -0.6 -0.4 -0.8 2 4 VDS (VOLTS) 6 8 FIGURE 7. DRAIN CURRENT vs DRAIN VOLTAGE FOR CONSTANT VALUES OF GATE VOLTAGE MEASURED CURVES vs CALCULATED POINTS 40 -0.2 RFP15N15 0 0 RFP15N15 IDS (AMPERES) -5 -10 IDS (AMPERES) 30 20 10 -15 0 0 -20 FIGURE 8. THIRD-QUADRANT DRAIN CURRENT vs DRAIN VOLTAGE WITH CONSTANT POSITIVE GATE VOLTAGE (CALCULATED) 40 80 120 VDS (VOLTS) 160 200 FIGURE 9. FIRST-QUADRANT DRAIN CURRENT vs DRAIN VOLTAGE, VGS = CONSTANT. NOTE AVALANCHE BREAKDOWN (CALCULATED) 150 10 75 120 8 60 10 4 60 RDRAIN = 10Ω VSUPPLY = 37.5V, 75V, 112.5V, 150V 30 0 TEST CKT. (SEE REF. 1) 0 20 40 60 TIME (µs) 80 FIGURE 10. DRAIN AND GATE VOLTAGE vs TIME FOR CONSTANT GATE CIRCUIT - MEASURED CURVES vs CALCULATED POINTS 3 2 0 100 8 MEASURED CALCULATED 10Ω 45 30 20V 0V 6 + - 50Ω 4 50Ω VGS (VOLTS) 6 MEASURED CALCULATED VDS (VOLTS) RFP15N15 90 VGS (VOLTS) VDS (VOLTS) RFP15N15 2 15 0 200 400 600 TIME (ns) 800 1000 FIGURE 11. DRAIN AND GATE VOLTAGE vs TIME FOR STANDARD SWITCHING CIRCUIT - MEASURED CURVES vs CALCULATED POINTS Application Note 9209 Conclusion 4A ID (AMPERES) RFP15N15 VGS = 0 0.0 An equivalent-circuit model for power-MOSFETs, that is suitable for use with the SPICE CAD program, has been demonstrated. The model is compatible with all versions of SPICE presently available without modification to the program’s internal code. The model addresses static and dynamic behavior of first and third-quadrant operation, including avalanche breakdown, and is empirical in nature. All necessary input parameters may be inferred from data sheets or simple terminal measurements. Excellent agreement has been obtained between measured and simulated results. -4A References 0 100 200 300 400 TIME (ns) FIGURE 12. THIRD-QUADRANT DIODE - RECOVERY vs TIME CURVE (CALCULATED) [1] Wheatley Jr., C. F. and Ronan Jr., H. R., “Switching Waveforms of the L2FET: A 5-Volt Gate-Drive Power MOSFET,” Power Electronic Specialists Conference Record, June 1984, p. 238 [2] Ronan Jr., H. R. and Wheatley Jr., C. F., “Power MOSFET Switching Waveforms: A New Insight,” Proceedings of Powercon II, April 1984, p. C-3 [3] Nienhaus, H. A., Bowers, J. C., and Herren Jr., P. C., “A High Power MOSFET Computer Model,” Power Conversion International, January 1982, p 65 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 4