AN9326: A Complete Analog-to-Digital Converter Operating from a Single 3V Power Supply

A Complete Analog-to-Digital Converter
Operating From a Single 3.3V Power Supply
Application Note
Introduction
The current data acquisition marketplace has an ever
increasing demand for integrated circuits capable of
operating with a single 3.3V power supply. The Intersil
HI-5812 12-bit sampling analog-to-digital converter has
proven capable of meeting this market demand and can
assist system designers with their 3.3V requirements. The
Intersil HI-5813, which will be our 3.3V, 12-bit ADC with
guaranteed 3.3V parameters, is scheduled to be introduced
in the fall of 1993.
Features
The Intersil HI-5812 is a fast, low power, 12-bit successive
approximation analog-to-digital converter capable of operating from a single 3.3V to 6V supply. Typical supply current is
1.9mA (when operating with a 5V supply), and the device
can operate from either an external clock or from its own
internal clock. It is offered over the full industrial temperature
range in 24 lead narrow body Plastic DIP, narrow body
Ceramic DIP, and wide body Plastic SOIC packages.
Theory of Operation
The HI-5812 uses capacitor charge balancing to approximate the analog input. The heart of the converter is a
capacitor network with a common node connected to a
comparator and the second terminal of each capacitor is
individually switchable to the analog input, VREF+, or VREF-.
A complete conversion takes 15 clock cycles. The first three
clock cycles are used to auto-balance the comparator at the
capacitor common node. The switchable terminal of every
capacitor in the network is connected to the analog input
during this time.
During the fourth clock period, all capacitors are
disconnected from the input. The capacitor representing the
MSB is then connected to the VREF+ terminal and the
remaining capacitors to VREF-. After the charge balances
out, the capacitor common node will indicate whether the
input was above 1/2 of ((VREF+) - (VREF-)). At the end of the
fourth clock period the comparator output is stored and the
MSB capacitor is either connected to VREF+ (if the
comparator output is high) or connected to VREF-. This
allows the next comparison to be at either 3/4 or 1/4 of
((VREF+) - (VREF-)). A similar procedure is used during
clock periods five through fifteen to test the capacitors
representing the remaining bits. At the end of each clock
cycle the comparator result is stored and each capacitor
either connected to VREF+ or VREF-.
Typical 3.3V Performance
At room temperature, the HI-5812 will typically exhibit eleven
bit linearity under the following operating conditions: (1) VDD
= VREF + = 3.3V and (2) maximum clock frequency fCLKMAX
= 600kHz (which equates to a conversion time of tC = 25µs).
1
August 1993
AN9326
Refer to Figure 1 through Figure 10 for typical performance
curves. Note that all data shown was taken at room temperature (+25oC).
Power supply current, at reduced supply voltage (3.3V), is
typically 500µA and remains relatively independent of the
applied external clock frequency (Figure 1.) Offset and Gain
errors remain below ±2LSBs up to fCLK = 600kHz (Figure 2
and Figure 3). Both Differential and Integral Linearity also
remain below ±2LSBs with fCLK up to 600kHz or 25µs
conversion time (Figure 4 and Figure 5). Typical overall
12-bit performance is achievable with fCLK up to 500kHz or
30µs conversion time.
Figure 6 and Figure 7 are spectral plots of the HI-5812
output with a 1kHz sine wave input and clock frequencies of
500kHz and 600kHz respectively. The plots show that the
noise floor is between -90dB and -100dB and all harmonics
are below -80dB for both clock frequencies. Figure 8, Figure
9 and Figure 10 illustrate signal-to-noise + distortion
(SINAD) vs frequency, total harmonic distortion (THD) vs
frequency, and effective number of bits (ENOB) vs frequency
respectively. As expected, each of these parameters
degrades with increasing clock frequency. In particular,
ENOB decreases from 11.1 bits at fCLK = 500kHz to 10.2
bits at fCLK = 750kHz. Figure 11 shows the test circuit used
for this 3.3V characterization. conversion time (Figure 4 and
Figure 5). Typical overall 12-bit performance is achievable
with fCLK up to 500kHz or 30µs conversion time.
Figure 6 and Figure 7 are spectral plots of the HI-5812
output with a 1kHz sine wave input and clock frequencies of
500kHz and 600kHz respectively. The plots show that the
noise floor is between -90dB and -100dB and all harmonics
are below -80dB for both clock frequencies. Figure 8, Figure
9 and Figure 10 illustrate signal-to-noise + distortion
(SINAD) vs frequency, total harmonic distortion (THD) vs
frequency, and effective number of bits (ENOB) vs frequency
respectively. As expected, each of these parameters
degrades with increasing clock frequency. In particular,
ENOB decreases from 11.1 bits at fCLK = 500kHz to 10.2
bits at fCLK = 750kHz. Figure 11 shows the test circuit used
for this 3.3V characterization.
Conclusions
The capacitor charge balancing technique used by the
HI-5812 lends itself well to operation at reduced supply
voltages. Optimal performance is determined by the clock
frequencies applied.
Slower clocks allow for additional conversion time and allows
the comparator to meet the higher accuracy requirements
imposed by both the reduced headroom and the reduced
LSB size. Eleven bit performance can typically be obtained
with clock frequencies less than 600kHz (equating to tC =
25µs) and twelve bit performance can typically be achieved
with fCLK = 500kHz (tC = 30µs).
1-888-INTERSIL or 321-724-7143 | Copyright
© Intersil Corporation 1999
0.60
2.0
0.55
1.5
LSB
mA
Application Note 9326
0.50
1.0
0.5
0.45
0.40
100
200
250
500
0.0
100
600
200
fCLK (kHz)
250
500
600
fCLK (kHz)
FIGURE 1. DYNAMIC POWER SUPPLY CURRENT vs CLOCK
FREQUENCY
VREF = VDD = 3.3V
FIGURE 2. OFFSET ERROR (IN LSB) vs CLOCK FREQUENCY
VDD = VREF = 3.3V
2.0
0.5
LSB
LSB
0.0
-0.5
1.0
-1.0
-1.5
100
0.0
200
250
500
100
600
200
250
500
fCLK (kHz)
fCLK (kHz)
FIGURE 3. GAIN ERROR (IN LSB) vs CLOCK FREQUENCY
VREF = VDD = 3.3V
FIGURE 4. WORST CASE DIFFERENTIAL LINEARITY ERROR
vs CLOCK FREQUENCY
VREF = VDD = 3.3V
3.0
0
-10
ENOB = 11.27
SINAD = 69.4dB
THD = -81.4dBc
-20
2.0
dB
LSB
-30
-40
-50
-60
1.0
-70
-80
-90
-100
0.0
100
200
250
500
600
fCLK (kHz)
FIGURE 5. INTEGRAL INEARITY ERROR vs CLOCK FREQUENCY
VREF = VDD = 3.3V
2
600
FIGURE 6. SPECTRAL PLOT
(fCLK = 500kHz)
Application Note 9326
72
0
ENOB = 10.84
SINAD = 67.2dB
THD = 77.3dB
-10
-20
70
68
-40
-50
dB
dB
-30
-60
-70
66
64
-80
-90
62
-100
60
FIGURE 7. SPECTRAL PLOT
(fCLK = 600kHz)
750
11.8
11.4
-70
11.0
BITS
-72
dBc
600
fCLK
FIGURE 8. TYPICAL SIGNAL TO NOISE + DISTORTION
(SINAD)
VREF = VDD = 3.3V, fIN = 1kHz
-68
-74
-76
10.6
10.2
9.8
-78
-80
500
9.4
9.0
500
600
fCLK
750
FIGURE 9. TOTAL HARMONIC DISTORTION
VREF = VDD = 3.3V, fIN = 1kHz
3
500
600
fCLK
750
FIGURE 10. EFFECTIVE NUMBER OF BITS
VREF = VDD = 3.3V, fIN = 1kHz
Application Note 9326
+3.3V
4.7µF
0.1µF
10µF
0.1µF
0.01µF
VAA+
VDD
D11
.
.
.
D0
VREF+
4.7µF
0.1µF
0.001µF
OUTPUT
DATA
DRDY
OEM
ANALOG
INPUT
OEL
VIN
STRT
CLK
VREF-
VAA-
750kHz CLOCK
VSS
FIGURE 11.
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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