No. AN9506 Intersil Intelligent Power April 1995 A 50W, 500kHz, Full-Bridge, Phase-Shift, ZVS Isolated DC to DC Converter Using the HIP4081A Author: David J. Hamo Introduction ability to vary the turn-on delays of both upper and lower MOSFET switches. This is an essential feature for realizing zero voltage switching (ZVS). The net result is flexibility and capacity to derive the control logic drive signals necessary for phase-shift ZVS switching. The voltage rating of the HIP4081A is 80V, which is ideal for telecom DC to DC converters. With the added overvoltage protection circuit which turns on the lower MOSFETS and turns off the upper MOSFETS, further protection is supplied to the system. The block diagram of the full-bridge phase-shift power supply described in this application note is shown in Figure 1. The circuit discussed here has an output power capability of 50W, but operation can be scaled upwards to the 500W range with the appropriate power component changes. Many articles and papers have been published recently promoting the performance and benefits of the Phase-Shift, Full-Bridge Topology and rightly so. This topology productively utilizes the same elements that have been plaguing power supply designers for decades, those infamous parasitic components. The topology enables designers to advantageously employ transformer leakage inductance, MOSFET output capacitance and the MOSFET body diode, enabling designers to easily move their designs upwards in frequency. The topology offers additional advantages like zerovoltage-switching at a constant switching frequency, which substantially reduces switching losses. This can be significant enough to eliminate heatsinking of power MOSFETS and/or enabling the use of less expensive power devices. Reduced EMI and RFI are additional benefits, since the voltage and current switching waveforms are much “cleaner” and waveform edges switch softly compared to conventional pulse width modulation (PWM) techniques. The ability to move upwards in frequency will ultimately reduce the overall size and lower the cost of the supply. One megahertz operation and beyond is possible with this topology. This is truly a major advancement in topological architecture. The requirements for this design are a full bridge configuration, an additional inductor to aid resonant operation and output structure consisting of a dual diode rectifier and an LC filter. Special thermal substrates may not be required. As a result, cost savings can be realized by utilizing inexpensive FR4 printed circuit board material in place of elaborate thermal designs. What’s more, EMI/RFI filtering requirements and heatsinking are less rigorous further reducing costs. Therefore, focusing on the overall system cost, it can be demonstrated that employing this topology does have merit. HIP4081A Features The HIP4081A is a member of the HIP408X family of high frequency H-Bridge driver ICs. The HIP4081A H-Bridge driver has the ability to operate from 8 to 80VDC for driving N-channel MOSFET H-Bridges. The HIP4081A is packaged in both 20 Lead DIP and 20 Lead SOIC, provide peak gate current drive of 2.5A and can switch up to 1MHz. A combination of bootstrap and charge-pumping techniques is used to power the circuitry which drives the upper halves of the HBridge. The bootstrap technique supplies high instantaneous current needed for turning on the power devices, while the charge pump provides enough current to “maintain” bias voltage on the upper driver sections and MOSFETs. Since voltages on the upper bias supply pin “float” along with the source terminals of the upper power switches, the design of this family provides voltage capability for the upper bias supply terminals of 95VDC. Two resistors tied to pins HDEL and LDEL can provide precise delay matching of upper and lower propagation delays. The programmable delay range for this device is 10ns to 100ns. This variable delay capability is imperative for zero voltage switching and will be described shortly. Presently, there are limited phase-shift controllers on the market, and those that are available are still expensive. Having faced this problem, an investigation of designing a discrete solution was performed. What was discovered proved to be encouraging. With any low cost single ended controller and two low cost logic ICs, one can generate all the gating and delay functions necessary to derive the phase-shift control waveforms. What makes this all possible is the Intersil HIP4081A MOSFET driver. The HIP4081A is capable of independently driving four MOSFETs directly, eliminating the need for traditional drive transformers. The HIP4081A also allows additional drive and control capabilities unavailable with conventional gate drive transformers. This includes the 1-888-INTERSIL or 321-724-7143 | Copyright Phase-Shift Control Overview Due to the number of well written papers on the theory and concepts of phase-shift ZVS conversion, we will limit the discussion to the implementation of the technology. Several papers are listed in the reference section that address phase-shift ZVS conversion topics further. The full bridge drive control logic required for this topology is not conceptually complex. Figure 2 shows the full bridge with © Intersil Corporation 1999 1 Application Note 9506 CURRENT SENSOR EMI FILTER A VIN -36VDC TO -72VDC C +5V START-UP CIRCUITRY D B VCC PWM CONTROLLER PWM TO PHASE SHIFT CONVERTER LOGIC REFERENCE AND ISOLATION HIP4081A FIGURE 1. FULL-BRIDGE, PHASE-SHIFT POWER SUPPLY BLOCK DIAGRAM POWER DELIVERY INTERVAL LEFT LEG TRANSITION INTERVAL VIN FREE WHEEL INTERVAL iPRI RIGHT LEG TRANSITION INTERVAL C A 0 NS LIK VPRI VPRI LO SLEW INTERVAL VO NP CO iPRI DRIVE SIGNALS NS A B B D C D t0 t1 t3 t4 t2 t5 FIGURE 2. FIGURE 3. associated parasitic components essential for ZVS operation. Figure 3 shows the waveforms associated with the circuit of Figure 2. During phase-shift ZVS operation there are five states or intervals of time, that take place per half cycle of operation. These states will be briefly discussed and only one half cycle of the bridge will be described due to the circuits symmetric operation. Refer to Figure 3 during the following descriptions and time interval identifications. and to provide realistic transition delay times. The term resonant inductance will refer to the combination of transformer leakage inductance and any additional inductance in the primary path. Power Delivery Interval (t2-t4) The gate drive signals and timing diagram associated with the full bridge are shown in Figure 4. The power delivery interval of the phase shift topology is similar to the traditional full bridge converter, in that two diagonal switches are on (A&D or B&C). This applies the full input voltage across the primary and results in power transfer to the load. The amount of time these switches are on is directly proportional to the phase shift between the two sets of waveforms AB and CD. The phase between these sets of waveforms will change as required, to regulate the output voltage. A 100% phase shift will result in 100% duty cycle. Conversely, a 0% phase shift will result in 0% duty cycle. Slew Interval (t0-t2) The slew interval is the time it takes for the primary current to reverse directions. This time is established by the level of input voltage across the primary, load current and the total inductance in the primary path, referred to as the resonant inductance. This inductance includes the leakage inductance of the transformer and any additional inductance in the primary path. Additional inductance may be required to store enough energy to displace the capacitive charge on COSS 2 Application Note 9506 The MOSFET output capacitance COSS is multiplied by 4/3 to approximate the average capacitance value during a varying drain-to-source voltage. The derivation of this equation is listed in appendix A. A B C Right Leg Transition Interval(t3- t4) D The second ZVS delay is called the right leg (C&D) transition time which terminates the power delivery interval. This is the time required to displace the charge on the output capacitance of the C&D leg. The converters output inductor current is reflected to the primary and therefore is the source of energy which will displace this charge. The displacement of this charge forces the voltage across MOSFET C to zero (MOSFET D ZVS occurs during the cycles second half), enabling zero voltage switching to take place. In this case however, the mechanism for displacement of charge is not resonant, but linear since this transition is modelled by a current source of reflected output current driving the output capacitance. The time is given by: A&D ON TIME B&C ON TIME FIGURE 4 Freewheel Interval (t4-t5) Notice the following from Figure 3. There is a time when A&C switches will conduct simultaneously and B&D switches will conduct simultaneously. This state is called the “freewheel” interval. This is how the phase-shift controller can perform control without changing the frequency, unlike other quasi-resonant topologies. As the load requirements change, the freewheel time changes accordingly. The freewheel time increases with light loads and decreases with heavy loads. In other words, the freewheel time is a way for the controller to idle until the next appropriate state comes along. During the freewheel time, reflected load current is circulated through the FET switches A&C or B&D and the voltage across the primary is zero. Figure 3 shows the droop in primary current during this time. This is caused by conduction losses in the circulation path and output inductor ripple current. C R × V IN t RL = -----------------------IP VIN = Voltage applied to full bridge IP = Peak primary current CR = Resonant capacitance tRL = Transition time for the right leg interval Both energy sources required to displace the charge on the drain-to-source capacitances of the MOSFETs are load dependant. This makes it difficult to maintain zero-voltageswitching at light loads. However, this fact does not pose a serious problem as described later in the section titled ZVS Design Considerations. Transition Intervals (ZVS Delay) Left Leg Transition Interval (t0- t1) The method for ZVS involves the displacement of charge in the drain-to-source capacitances of the MOSFETs and occurs differently for the two legs of the bridge. The left leg (A&B) transition interval begins after the freewheel state to initiate the power delivery interval. This is the time required to displace the charge on the output capacitance of the A&B leg. For the left leg, the source of energy that displaces this charge is stored in the transformer’s leakage inductance plus any additional inductance in the primary path (the total being the resonant inductance). The displacement of this charge forces the voltage across MOSFET A to zero (MOSFET B ZVS occurs during the cycles second half), enabling zero voltage switching to take place. Here the MOSFETs output capacitances form a resonant circuit with the resonant inductance. The charge is displaced in a time equal to one-fourth the resonant period. As a result, the left leg transition time is given by: π t LL = --- × L R C R 2 Phase-Shift Drive Derivation Deriving the phase-shift drive control logic from a standard off-the-shelf PWM controller is straight forward. The controller chosen is the Unitrode UC3823A. This was chosen for its high speed operation and low start-up current. However, any low-cost, high-speed controller could be used. Figure 5 shows the logic circuit used to derive the phase-shift control logic. The timing diagram for this circuit is shown in Figure 6. Notice that the clock output from the UC3823A is shown only for reference purposes. The clock signal is not used in the circuit, however, many of the following equations will include the clock period tCLK in their composition. The clock period tCLK is 2µs. The PWM output from the controller clocks the flip-flop which outputs waveforms at its Q and Q outputs, which become a&b. At the same time the PWM logic signal is exclusive ORed with the Q and Q outputs of the flip-flop. This generates the c&d waveforms as shown in the timing diagram. Normally “slivers” are developed on the c&d waveforms. They come about from the time delay caused by the PWM clock signal propagation time through the flip-flop. Using advanced CMOS logic the maximum sliver width will be approximately 15ns. While it is possible to generate sliverless waveforms with additional circuitry, this does not present a problem since small capacitors filter the slivers as (EQ. 1) tLL = Transition time for the left leg interval LR = Transformer leakage inductance + additional inductance CR = Resonant capacitance The resonant capacitance is given by: 4 C R = --- × C OSS + C XFMR 3 (EQ. 3) (EQ. 2) COSS = MOSFET output capacitance CXFMR = Transformer capacitance 3 Application Note 9506 shown in Figure 5. The Q and Q signals are passed through an XOR gate which is configured as a non-inverting buffer and become a&b. This is to match the timing of the a&b drive outputs with the c&d drive outputs. These signals are then input into the HIP4081A which in turn drives the MOSFET H-Bridge. The A&B drive signals drive the Left-Leg of the bridge while the C&D drive signals drive the Right-Leg of the bridge. The ZVS timing delays are determined by Equation 1 and Equation 3. Once the requirements are known the HIP4081A turn on delay times can be set accordingly by the resistor values on the HDEL and LDEL pins. Normally, the left leg and right leg would like to be controlled independently. With the HIP4081A the upper and lower device delay times are controlled independently. This causes a requirement that both delay times be identical. Typically the left leg delay is slightly longer than the right leg delay. In this case the HDEL and LDEL are set to the longer of the two. This concept will be explained further in the section titled ZVS Design Considerations. 74ACT86 a VREF 74ACT86 PR D FROM PWM CONTROLLER Q 74ACT74 b TO HIP4081A 74ACT86 INPUT The Design Process Now that the proper control signals for the phase-shift topology have been realized its time to begin working through the design of the power supply of Figures 7A and 7B. c Q CL 74ACT86 VREF d To begin, the overall power supply requirements have been defined by: Input Voltage = -36V to -72V FIGURE 5. Output Voltage = +5V The flip-flop and XOR gates receive their power from the controllers VREF terminal of the UC3823A, which outputs +5V. The power requirements for the logic devices are well within the reference output current capabilities. However, the reference should be properly by-passed. Output Current = 10A Switching Frequency = 500kHz tCLK CONTROLLER CLOCK PWM OUTPUT 74ACT74 OUTPUT Q a Q b PWM + Q=c PWM + Q=d ZVS DELAY (EQ. 1) ZVS DELAY (EQ. 1) HIP4081A OUTPUT A B ZVS DELAY (EQ. 3) ZVS DELAY (EQ. 3) C D FIGURE 6. PHASE SHIFT TIMING DIAGRAM 4 POWERRTN R33 33K R34 10 Q5 BF720T1 R38 47K T2 T37-8 C15 0.1µF 100V + BOOT D2 75V BZX84C75LT1 ILIM R42 20K D18 1N4148 C11 4µF 100V VREF U4 VREF 15 13 R23 10K D15 BZX84C12LT1 12V 2 1 3 8 5 R22 10K 10 C20 0.1µF VC OUTA VREF OUTB ILIM NI INV CT EAO RAMP RT SS GND PGND 4 11 14 9 6 1 2 7 5 4 5 C32 470pF VREF 4 C17 0.1µF 2 C22 0.22µF C34 1µF 3 R24 6.49K C21 47µF 10K 6 B U5C 8 C 13 74ACT74 U5D 11 D 74ACT86 C26 2200pF R45 4.7K C25 2200pF VREF POWERAIL R21 R5 619K 12 R43 1K Q7 MMBT3904LT1 -36V TO -72V 6 CLK Q 1 U5B 74ACT86 CL C18 1µF + 9 10 U6A D PR Q 5 + + A 74ACT86 _ C19 470pF R39 2.2K 3 74ACT86 12 UC3823A U5A R7 10K C29 0.1µF FDBK FIGURE 7A. Application Note 9506 C14 0.1µF 100V 16 CLK VCC -36V to -72V +5.0V J2 ILIM Q6 MMBT5401LT1 0.470Ω 2W POWERRTN R44 BOOT D3 MBRS1100T3 IRFR120 Q1 R11 D4 U1 1 10 6 B 2 C 5 D 3 6 8 9 4 AHO AHB BHO AHI AHS ALI BHS BHI VDD BLI VCC DIS BLO HDEL ALO LDEL BLS VSS ALS C7 0.1µF IRFR120 Q3 R12 10 20 C4 4µF 100V 2.0µH 12 10T 19 16 R13 IRFR120 Q4 10 13 R14 17 14 C23 0.1µF + 2T 2T R35 100 1W +5V/10A 4µH + IRFR120 Q2 D1 BAV70LT1 C5 0.47µF C3 100µF C30 2200pF 5T 5T 15 18 L1 T50-8 T1 EPC-19 L2 T44-6 D8 MBRB2535CTL R4 4.99K R2 C8 15K 0.1µF U2 UC39432 2 10 C28 10µF CMP HIP4081A 5 4 6 R40 100K MOLEX 22-59-1310 R41 100K 3 VCC REF EA+ COLL SEN GND ISET R3 5.11K POWERAIL L3 + C16 33µF 470µH DT1608-474 VREF FDBK FIGURE 7B. ISO1 PS2701-1 7 8 R1 39 1 Application Note 9506 7 A BHB 11 MBRS1100T3 1 2 3 4 5 6 7 8 9 10 MOLEX 22-59-1310 10 C6 0.1µF J1 1 2 3 4 5 6 7 8 9 10 Application Note 9506 For an EPC-19 transformer operating at 250kHz, a 25oC rise will occur operating with a peak flux density of 1200G. If we let the maximum primary duty cycle reach 80% the maximum on time will be 0.8t, then the maximum flux density change within the time span of 0.8t/2 will be ∆B = 2400G. The voltage across the transformer has been reduced by 2V due to an anticipated voltage drop caused by the two MOSFET switches rDS(ON). The minimum primary turns from Equation 5 is: Power Semiconductor Selection One of the overall goals of this supply is to maintain the lowest profile and size possible. This is important to module manufacturers, as well as board level OEMs. We selected a form factor close to the standard 3” x 3”, along with a minimum profile. The voltage and current requirements along with size constraints has lead to the choice of four Intersil IRFR120s for the full-bridge switches. They have a rDSON of 0.27Ω, a breakdown voltage of 100V and are available in the surface mount TO-261(D-PAK)™ package. The output rectifier diode chosen is the Motorola MBRB2535CTL available in a (D2-PAK)™. This rectifier was chosen because of its very low forward voltage drop, slightly over 0.3V at 10A. This is a important consideration since most of the power loss is in the output rectifier. 0.8 × 4 × 10 – 6 36 – 2 × ------------------------------------- × 10 8 2 N P = ---------------------------------------------------------------------------------- ≥ 10Turns 0.227 × 2400 Now in the most ideal case: NS V O = V IN × -------- × D N Transformer Design P Maintaining the form factor requirements mentioned earlier has lead to the choice of an EPC-19 ferrite core from TDK. In this application the transformer size is limited by core loss. The transformer will be designed for a temperature rise of 50oC. That coupled with a maximum ambient temperature of 50oC, the transformer can reach a maximum temperature of 100oC. PC40 material was chosen since it has a curie temperature in excess of 215oC, and low core loss at the switching frequency. Design curves given with the core material (TDK catalog #BAE-030D) show temperature rise for a given core loss. The design curves indicate that the core temperature will rise 50oC with the core dissipating 800mW. This value is for core loss only and excludes any copper losses. If the core losses and copper losses were equally distributed in the transformer the core loss will be 400mW. Therefore, we can determine the maximum core loss limitation for this design: P CORE P CLOSS = -------------------Ve For the non-ideal case: NS V O = ( V IN – V MOSDROP ) × -------- – V RECT × D NP Rearranging and solving for the secondary turns ratio: VO -------- + V RECT D N S = ------------------------------------------------- × N P V IN – V MOSDROP 5 ------- + 0.3 0.8 N S = ----------------------- × 10 = 2Turns 36 – 2 The transformer turns ratio has been designed to yield a given flux density excursion, thereby maintaining the limits of temperature range. Next, the wire size must be determined and the copper losses must not exceed 400mW to limit the rise in core temperature to 50oC. For the primary windings a current density of 500 circular mils per RMS ampere was used. For the secondary a current density of approximately 200 circular mils per RMS ampere was used because of the higher current and the fact that there are only two windings per side required for the secondary. Using these current densities, wire size requirements become 20AWG for the primary and 19AWG for the secondary. For the secondary, eight strands of 28AWG magnet wire will be used, yielding an equivalent circular mil area of 19AWG. With wire selected, the copper loss including skin effects and increased wire resistance at 100oC, approach 300mW. Therefore we can expect a maximum temperature rise of slightly less than 50oC. The transformer was wound by interleaving the secondary halves between the primary. The first half of the secondary will be wound first and the primary will be wound next. The remaining secondary half will be wound and finally, the auxiliary will be wound. (EQ. 4) mW 400mW P CLOSS = --------------------------- = 382 ----------cm 3 1.047cm 3 Using the curves once again for the PC40 material, the core loss vs flux density curves indicate that the peak flux density for a core loss of 382 mW/cm3 is approximately 1200 gauss. The switching frequency is 500kHz but with the full-bridge topology the core flux swings at half the switching frequency. Therefore the transformer switching frequency will be 250kHz while operating in the first and third quadrants of its hysteresis curve. The remaining transformer design procedure is now straight forward. From Faraday’s Law: E × ∆t × 10 8 N P = -------------------------------Ae × ∆B (EQ. 6) (EQ. 5) Where E = voltage across the transformer windings (Volts) NP = number of primary turns ZVS Design Considerations Ae = Iron area of the core (cm2) Now that the transformer has been designed it is a good time to determine the ZVS transition times. This will allow the turn on delays to be set properly for zero-voltage-switch- ∆B = Core flux density (Gauss) ∆t = time in which the flux is changed D-PAK™ and D2-PAK™ is a registered trademark of Motorola 7 Application Note 9506 ing to take place. However, choosing the left leg transition time requires much thought because this time is a function of many variables. Therefore, before going any further some concepts need to be clarified and an equation will be derived that will allow this value to be chosen quickly and correctly. From Figure 8: ∆D × t CLK = t 2 – t 1 Performing the substitution and multiplying by two since there are two such transitions per period, the loss of duty cycle on the secondary is then equal to: In Figure 8, primary bridge voltage, primary current and secondary voltage waveforms are shown. Notice that the primary and secondary duty cycles are different. From these waveforms the following relationship can be determined: ∆D = D – D 2 × N S × L R × I LOAD ∆D = ------------------------------------------------------t CLK × N P × V i Solving for LR: (EQ. 7) e ∆D × t CLK × V i × N P L R = ----------------------------------------------------2 × I LOAD × N S ∆D = Loss of duty cycle on the secondary side. D = Primary voltage duty cycle. We now have an expression for the total resonant inductance in terms of loss of duty cycle so that its value can be easily determined. From the beginning of the design the maximum secondary duty cycle has been chosen to be 80%. Using this value and selecting a duty cycle loss of 15%, will yield a maximum primary duty cycle of 95%. The leakage inductance of the transformer is approximately 500nH and the total resonant inductance calculation becomes: De = Secondary voltage duty cycle or effective duty cycle. The loss of duty cycle on the secondary side is a key concept. This loss is caused by the time it takes to change the direction of the primary current (t2-t1). Therefore it is imperative that the resonant inductance value not be excessive. Otherwise, this might require a larger turns ratio, since the primary duty cycle could reach its maximum value while the secondary duty cycle is incapable of sustaining the appropriate output voltage. This concept could be a stumbling block for the unsuspecting. This leads to the importance of deriving an equation for LR in terms of this loss of duty cycle ∆D which enables LR to be bounded properly. This in turn, will lead to the correct value chosen for the left leg transition tLL. 0.15 × 2 × 10 – 6 × ( 36 – 2 ) × 10 L R = ---------------------------------------------------------------------------------- = 2.55µH 2 × 10 × 2 L RINDUCTOR = 2.05 µH – 0.5µH = 2.05µH Before determining the left leg transition time the resonant capacitance must be calculated. The IRFR120 MOSFET switches have a COSS capacitance equal to 130pF and the transformer primary capacitance is approximately equal to 10pF. Using Equation 2 the resonant capacitance is calculated: Deriving an equation for ∆D: Let t2-t1 equal the time it takes for the primary current to slew. Since we know the slope of the sluing primary current, the following equation can be determined from Figure 8. 4 C R = --- × 130 × 10 – 12 + 10 – 12 = 183pF 3 NS -------- × I LOAD NP = ------------------------------t2 – t1 Vi ------LR The left leg transition is then calculated using Equation1: π t LL = --- × 2.55 × 10 – 6 × 183 × 10 – 12 2 i 0 (EQ. 8) PRI I LOAD = ----------------n t LL = 34ns In the previous calculation an alternative expression for tLL could have been used: DtCLK VPRI ∆D × t CLK × V i × C R × N P π t LL = --- × -------------------------------------------------------------------2 2 × I LOAD × N S V i SLOPE = -------L R tCLK So making the left leg transition 34ns will cause the maximum primary duty cycle to be approximately 95% at full load with the minimum input voltage applied. This allows 5% margin for variations in CR and LR, assuming nearly 100% duty cycle is possible. These numbers can be adjusted easily by the previous equations for your particular needs. DetCLK VSEC Vi n ∆DtCLK 0 t0 t1 t2 (EQ. 9) t3 t4 Now that the resonant inductor and left leg transition time have been selected, the right leg transition time needs to be determined. It turns out that the maximum right leg transition time occurs during the maximum input voltage and at a load boundary called the ZVS operational limit. The ZVS operational limit is the point at which the power supply no longer maintains zero-voltage-switching. This is a normal function of this topology. As mentioned earlier, the two energy sources (resonant inductance and output inductance) required to dis- t5 FIGURE 8. Rearranging: N S × L R × I LOAD t2 – t1 = --------------------------------------------NP × Vi 8 Application Note 9506 place the charge on the drain-to-source capacitances of the MOSFETs are load dependant. Therefore at some load value less than maximum, the energy stored in these sources will be less than adequate to displace this charge. This is the point at which the converter will no longer operate in the ZVS mode. This is best exemplified by Figure 9. Figures 9 A, B and C show how the left leg transition is formed. Figure 9A shows that the energy in LR is larger than the energy required to displace the capacitance charge. Figure 9B shows the ZVS operational limit where the energy in LR is equal to the energy required to displace the capacitance charge. Figure 9C shows the energy in LR is not capable of fully displacing the capacitance charge. The same scenario is true for the right leg transitions but they will ramp at a linear rate and their energy source is the output inductance as stated earlier. VIN VIN tLL A So the power at which the supply stops zero-voltage-switching is 16.6W, well below 1/2 Po(max), which is within the design goal requirements. The right leg transition can now be determined using Equation 3: 183 × 10 – 12 × 72 t RL = -------------------------------------------- = 20ns 0.662 The left-leg transition takes 34ns and the right-leg transition takes 20ns. These values can now be programmed as turn on delays via the HDEL and LDEL resistor values on the HIP4081A. As previously mentioned, since the HIP4081A controls the upper and lower delay times, both HDEL and LDEL should be set equal to the longest delay time. This time will be 34ns. Resonant Component Selection VIN The core material selected for the resonant inductor was chosen for its high Q and low core loss characteristics. Micrometals powdered iron RF core T44-6 has a Q of 200 at the resonant frequency of interest, 7MHz (FRES=1/(4xtLL)). tLL tLL The output filter inductor was another Micrometals powdered iron RF core, T50-8 chosen for its low core loss at 500kHz. This material has the lowest core loss of any other material they offer. As a result, it is also the most expensive. Another core which may be used is the T50-52. The 52 material has slightly higher core loss and is less expensive. C B FIGURE 9. It is more important to maintain ZVS at higher loads for two reasons. The first and more obvious is that the switching losses are greatly reduced. The second reason is because the free-wheel time is at a minimum during full load. Therefore the circulation of the reflected load current during the free-wheel time is shortened thereby reducing the I2R losses in the free-wheel circulation path. During lighter loads the power dissipation in the MOSFET switches should not be significant if switching losses begin to manifest due to the smaller primary currents during lighter load values. For this reason, the design goal was to maintain ZVS operation down to half the maximum output power (25W). It should be noted that at higher converter power levels (>200W) it may be necessary to place saturable inductors in series with the anode leads of the output rectifier. This extends the range of zero-voltage-switching to very low power levels further improving efficiency. This concept is discussed in great detail in several of the listed references. Effects of Variations in MOSFET Parasitic Output Capacitance The MOSFETs parasitic output capacitance, COSS can vary from part to part, and from manufacturer to manufacturer. However, this variability does not cause any severe aberration in the operation of the converter. The only noticeable effect can be a slight decrease in efficiency. This loss in efficiency is due to two factors. The first and most significant is capacitive turn-on losses. This is caused by the energy required to displace the charge on the output capacitance when there is insufficient energy in the resonant inductor to perform this task. This is indicated by the first term in Equation 11. The other losses are simply turn-on and turn-off losses which normally occur if zero voltage switching is not in effect. These turn-on and turn-off switching losses are caused by the slight movement of the resonant peak with respect to the programmed ZVS delay time as COSS varies from its nominal value. This may cause drain-to-source voltage to occur simultaneously with drain current during a portion of the switching time, thereby decreasing efficiency. This is indicated by the second and third terms in Equation 11. The equation which determines the minimum current required for ZVS operation is: 1 --2 3 --2 I PRI ( critical ) = 2 × C R × V OSS × V IN ( MAX ) --------------------------------------------------------------------------LR I PRI ( critical ) = 2 × 183 × 10 × 25 × 72 -------------------------------------------------------------------------- = 0.662A 2.55 × 10 – 6 – 12 1 --2 (EQ. 10) 3 --2 Figure 10 shows the curve of output capacitance as a function of drain-to-source voltage. COSS is measured at a drain-to-source voltage = 25V. This voltage point is designated as VOSS. At this voltage point COSS is equal to 162pF as indicated by the curve. The minimum primary current to maintain ZVS switching is 0.662A. To see what this means in terms of output power the following calculation is performed: NP I O ( Critical ) = -------- × 0.662 = 5 × 0.662 = 3.31A NS Maximum variations of COSS for Intersil IRFR120 is ±20% of the measured value as shown by Figure 10. However, changes in COSS can be much more significant when select- P O ( Critical ) = 3.31A × 5V = 16.6W 9 Application Note 9506 ing the same MOSFET from a different manufacturer. This is because each MOSFET manufacturer has different processes, resulting in changes from the typical value. This value can be significantly different from the typical value shown in the data sheets. Therefore, it is a good idea to work closely with your supplier to obtain the measured value for COSS. The measured value for COSS at VOSS = 25V is 162pF as shown in Figure 10. Therefore, one can expect a worst case variation of ±20% from this value as indicated by Figure 10. It will be shown that even for large changes in COSS, the total power dissipation in the converter will not be impacted greatly. It should be pointed out that the initial design proceeded with COSS = 130pF as stated on the data sheet for the typical value. It was later determined that the measured value was 162pF. This difference had no noticeable effect on converter performance confirming that moderate variations in COSS have little or no effect on converter performance. efficiency will be slightly degraded only if the COSS value turns out larger than the target design. To counter this effect of possibly larger COSS, one could simply program the delays slightly longer than the calculated values. It should be pointed out that tSW was chosen to be 10ns in Equation 11, to generate the curves of Figure 11. In conclusion of this topic, once the measured value for COSS is known, one can expect a worst case change of ±20%. This change is insignificant to the converters performance as shown by Figure 11. Once a vendor is selected and transition delays are determined, the delays can be set and forgotten about. 1 405pF 72V PSWLOSS, (COSS, VIN) (W) 0.8 COSS , CAPACITANCE (pF) 1000 800 600 405pF 54V 0.6 COSS ∆COSS 0% 54V 195pF +20% 72V 405pF +150% 195pF 72V 0.4 405pF 36V 162pF 72V 195pF 54V 0.2 400 162pF 54V 195pF 36V +20% 200 0 -20% 0 0 VIN 36 V 162pF 5 10 15 20 VDS , DRAIN-TO-SOURCE VOLTAGE (V) 25 4 6 OUTPUT CURRENT (A) 8 10 Performance Figure 11 shows the effects of increased switching losses by varying COSS and the input voltage (essentially VDS). Equation 11 was used to determine these curves and is derived in appendix A. From the curves of Figure11, it can be seen that even for large variations the impact in switching losses is not that great, especially if the converter is operating near full load. Again, one needs to understand their application to determine how much variation in COSS can be tolerated. Hopefully Figure11 will help give understanding to the impact of COSS variation on converter switching losses. 1 2 FIGURE 11. NON-ZVS OPERATION FIGURE 10. COSS CURVE FOR THE INTERSIL IRFR120 Figures 12 and 13 show the primary voltage and current waveforms of the converter taken at a load current of 10A and an input voltage of 48V. As indicated below, the frequency of the primary side is 250kHz while the secondary side frequency will be twice the primary or 500kHz. The primary current scale is 0.5A per division yielding a 3AP-P waveform. Notice how clean these waveforms are. This is one of the significant benefits of zero voltage switching. Additionally, the primary current and rectified secondary voltage is shown in Figure 14 to illustrate the erosion of the secondary duty cycle as mentioned earlier. The erosion is approximately 200ns, yielding a 10% reduction in the secondary side on time. The calculated value for a 48V input was 11% for a difference of 1%. This exemplifies the importance of using Equation 8 to calculate the erosion of the secondary. On the secondary side we have the same problem as with more classic topologies. A moderate snubber was added to the rectifier to reduce the ringing. The two graphs of Figures 15 and 16 show percent regulation and percent efficiency. Percent regulation was excellent. Over the full input voltage and load range, the maximum change in output voltage was 54mV. During moderate to high output current the efficiency was predominately in the low 80% range. The actual measurements correlated very closely with the loss analysis performed on this converter prior to its design. While this topology offers lossless switching, the conduction 3 ----2 4 2 2 --- × COSS × VOSS × VIN – 1 --- L R × I PRI 3 2 = --------------------------------------------------------------------------------------------------- + P SWLOSS tCLK 162pF 36V 0 (EQ. 11) I PRI × V SWLL × t SWLL I PRI × V SWRL × t SWRL --------------------------------------------------------------------- + ----------------------------------------------------------------------tCLK tCLK From Equation 11 it can be seen that the switching loss is ≤ zero if the resonant inductance has enough energy to displace the output capacitance and if the switching losses are zero due to ZVS operation. In the first term of the Equation, decreasing values of output capacitance are an advantage. Here the resulting energy in the resonant inductance exceeds the energy needed to displace the capacitance charge. Decreasing capacitance also means that the delay time set for the ZVS transition will be longer than necessary. This has no significant effect on converter efficiency. The 10 Application Note 9506 data is given in Table 1. From these figures one can target specific areas to optimize the converter for greater efficiency. For instance, the current sense resistor can be replaced with a current transformer for improved efficiency. losses do increase. What this topology offers for this configuration of input and output voltage is the ability to increase the switching frequency, while at the same time, providing much cleaner waveforms. The breakdown of the power loss TEK RUN: 50.0ms/s AVERAGE TEK RUN: 100ms/s AVERAGE C1 FREQ 251.52kHz M2 FREQ 250.26kHz 1 M2 MATH2 20.0V CH1 10.0mV 0.5A/DIV 500ns PER DIV FIGURE 12. 500ns PER DIV FIGURE 13. TEK RUN: 100ms/s AVERAGE REG AT 48V 1.5 C1 FREQ 252.403kHz REG AT 72V % REGULATION C2 FREQ 506.033kHz 1 1 0.5 REG AT 36V 2 0 CH2 10.0V 0 500ns PER DIV 5 OUTPUT CURRENT (A) FIGURE 14. FIGURE 15. EFF AT 36V 80 EFF AT 72V % EFFICIENCY CH1 10.0 mV 0.5A/DIV EFF AT 48V 60 40 0 5 OUTPUT CURRENT (A) FIGURE 16. 11 10 10 Application Note 9506 The plots shown in Figure 17 illustrate the progression of zero voltage switching. The first and second plots show that the delay time is skewed from the nominal value. This is because the HIP4081A delay was made excessively large to illustrate the resonant half sinusoid. Ideally you want to set the delay to 1/4 the period of the resonant frequency. This delay time is determined by Equation 1. The final plot shows the delay set to the optimum point for proper zero voltage switching. Notice the absence of ringing on VDS compared to when non-zvs operation is taking place! TABLE 1. LOSS ANALYSIS AT VIN = 48V, IOUT = 10A MOSFET Full-Bridge Conduction Losses 4W Output Diode Losses 3W Switching Losses 0W Power Transformer Losses 0.8W Output Inductor Losses 0.75W Resonant Inductor Losses 0.57W Current Sense Resistor Losses 1.2W Snubber Losses 0.38W Miscellaneous Losses 1.24W Total Power Loss 11.94W Efficiency The plots of Figures 18 and 19 illustrate zero voltage switching of switch A and switch B. In the first plot of Figure 18, the voltage across A is zero during turn-on of switch A. Here you can see the HIP4081A driving the high side FET. Notice the 12V step on this waveform. This 12V step voltage is being supplied by the HIP4081A bootstrap capacitor which turns on switch A. The second plot shows the gate drive of switch B, along with the same phase node, VDS of switch B. Here, the voltage across switch B is zero during the turn-on of switch B. In the remaining plots of Figure 19, the mechanism is the same, but here the MOSFETS are being turned off. In all of these waveforms you can see that the delay time is nearly 34ns as calculated in the application note. 81% Operating the converter with a load greater than 5A will require a heatsink attached to the output rectifier. In addition, the full bridge may require a larger copper area or small heatsink for heat removal. TEK RUN: 1.00GS/S AVERAGE TEK RUN: 1.00GS/S AVERAGE 1 1 CH1 20.0V 50.0ns CH1 FIGURE 17A. HIP4081A DELAY SET FOR LARGE SKEW 20.0V 50.0ns FIGURE 17B. HIP4081A DELAY SET FOR MODERATE SKEW TEK RUN: 1.00GS/S AVERAGE 1 CH1 20.0V 50.0ns FIGURE 17C. HIP4081A DELAY SET FOR PROPER ZVS OPERATION FIGURE 17. NON-ZVS TO ZVS PROGRESSION, VDS OF SWITCH B, VIN = 48V, IOUT = 3A 12 Application Note 9506 TEK RUN: 2.00GS/S AVERAGE TEK RUN: 2.00GS/S AVERAGE VOLTAGE OF VOLTAGE OF A AND B PHASE NODE A AND B PHASE NODE 1 1 VGATE TO SOURCE VGATE TO GND SWITCH A SWITCH B 2 2 CH1 20.0V CH2 20.0V CH1 25.0ns PER DIV FIGURE 18A. VOLTAGE ACROSS SWITCH A = 0 DURING TURN-ON OF SWITCH A 20.0V CH2 5.00V 25.0ns PER DIV FIGURE 18B. VOLTAGE ACROSS SWITCH B = ZERO DURING TURN-ON OF SWITCH B FIGURE 18. ZERO VOLTAGE SWITCHING OF SWITCH A AND B, ZVS TURN-ON TEK RUN: 2.00GS/S AVERAGE TEK RUN: 2.00GS/S AVERAGE VOLTAGE OF A AND B PHASE NODE VOLTAGE OF A AND B PHASE NODE 2 2 VGATE TO SOURCE SWITCH B 1 VGATE TO GND SWITCH A CH1 20.0V CH2 20.0V 1 CH1 25.0ns PER DIV FIGURE 19A. VOLTAGE ACROSS SWITCH A = ZERO DURING TURN-OFF OF SWITCH A 5.00V CH2 20.0V 25.0ns PER DIV FIGURE 19B. VOLTAGE ACROSS SWITCH B = ZERO DURING TURN-OFF OF SWITCH B FIGURE 19. ZERO VOLTAGE SWITCHING OF SWITCH A AND B, ZVS TURN-OFF Conclusion References This topology was exciting and surprisingly simple to implement. It has been shown that the HIP4081A can be used successfully to realize the phase shift ZVS full-bridge topology. Not only does the HIP4081A drive the H-bridge but it also is capable of delivering the needed ZVS transition delay times required by this topology. In addition, a simple logic block was used to convert a single ended PWM output into the required phase shift logic drive signals. Guicho Hua, Fred Lee, Milan Jovanovic, An Improved FullBridge Zero-Voltage-Switched PWM Controller Using a Saturating Inductor, IEEE Transactions on Power Electronics, October 1993. J.A. Sabate, V.Valtkovic, R.B. Ridley, F.C. Lee, B.I. Cho, Design Considerations For High-Voltage High-Power Full-Bridge ZeroVoltage-Switched PWM Converter, IEEE APEC 1990 Dhaval B. Dalal, A 500kHz Multi-Output Converter with Zero Voltage Switching, IEEE 1990 Abraham Pressman, Switching Power Supply Design, McGraw Hill, 1991 M.M. Walters, W.M. Polivka, Extending The Range of SoftSwitching In Resonant-Transition DC-DC Converters, International Telecommunications Energy Conference, October 1992. Bill Andreycak, Designing a Phase Shifted Zero Voltage Transition Power Converter, Unitrode SEM-900 Power Supply Design Seminar Handbook. Edwin Oxner, Power FETS And Their Applications, PrenticeHall, 1982 George Danz, HIP4081, 80V High Frequency H-Bridge Driver, Intersil Application Note, Publication # AN9325 A design process was developed to enable designers to accomplish their own designs. This was achieved by deriving essential equations and exposing key concepts. Following these procedures should allow designers to obtain success when incorporating this topology. What’s more, much of the mystery of this topology has been removed, especially in the area of parasitic functionality within the design. It was shown that the output capacitance variation does not have a great impact on overall performance. It was shown that the effects of this variation can be determined easily with graphical methods. 13 Application Note 9506 HIP4081A Converter 14 Application Note 9506 Material List 1 2 3 4 1 2 1 7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 2 1 2 2 1 1 3 1 1 1 2 1 1 1 1 1 1 1 1 1 4 1 1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 2 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 5 C3 C11, C4 C5 C6, C7, C8, C17, C20, C23, C29 C15, C14 C16 C18, C34 C19, C32 C21 C22 C25, C26, C30 C28 D1 D2 D3, D4 D8 D15 D18 IS01 J1 J2 L1 L2 L3 Q1, Q2, Q3, Q4 Q5 Q6 Q7 R1 R2 R3 R4 R5 R21, R7 R11, R12, R13, R14, R34 R23, R22 R24 R33 R35 R38 R39 R40, R41 R42 R43 R44 R45 T1 T2 U1 U2 U4 U5 U6 Appendix A 100µF 4µF 0.47µF 0.1µF Derivation of Equation 1 10V 100V 10V 50V The equation for resonant frequency: 1 Fr = ------------------2π LC 0.1µF 100V 33µF 20V 1µF 20V 470pF 50V 47µF 20V 0.22µF 50V 2200pF 50V 10µF 20V BAV70LT1 BZX84C75LT1 MBRS1100T3 MBRB2535CTL BZX84C12LT1 1N4148 NEC PS2701-1 MOLEX 22-59-1310 MOLEX 22-59-1310 4µH MICROMETALS T50-8 2.0µH MICROMETALS T50-6 470µH COILCRAFT DT1608 IRFR120 INTERSIL BP720T1 MMBT5401LT1 MMBT3904LT1 39 15K 1% 5.11K 1% 4.99K 1% 619K 1% 10K 10 The left leg transition takes place within a period of 1/4 the resonant period. 1 π t LL = --- ( 2π LC ) = --- LC 4 2 Derivation of Equation 2 The output capacity COSS is a depletion-dependant capacity whose value depends upon the impressed drain-to-source voltage. Therefore the drain-to-source capacitance value over varying drain-to-source voltages can be approximated as: V OSS n C DS ( V DS, n ) = C OSS ---------------- V DS Where n is between 1/2 and 1/3 for most MOSFETs, COSS is the measured output capacitance at a drain to source voltage VOSS. Most manufacturers measure this value at VOSS = 25V. Derive Energy and substitute for current: E = ∫ ( v × i ) dt dQ i = -------dt E = ∫ v dQ Capacitance is a function of drain-to-source voltage: C ( V DS ) = dQ d V DS E ( V DS, n ) = ∫ VDS C ( VDS, n) dVDS n ∫ 1–n E ( V DS, n ) = C OSS V OSS V DS dV DS Integrating: 10K 1% 6.49K 1% 33K 100 1W 47K 2.2K 100K 20K 1K 0.470 2W 4.7K EPC-19 MICROMETALS T37-8 HIP4081A INTERSIL UC39432 UC3823A 74ACT86 74ACT74 n 2–n C OSS × V OSS × V DS E ( V DS, n ) = -----------------------------------------------------------2–n Evaluate at n = 1/2 for the INTERSIL IRFR120: 1-- 3--- 2 2 2 E = --- C OSS V OSS V DS 3 Notice that the output capacitance is multiplied by the factor of 2/3. For the phase-shift ZVS topology there are two output capacitances (COSS) in parallel during each resonant transition. Therefore the effective energy and resonant capacitance is multiplied by 2 becoming: 1-- 3--- 2 2 4 E = --- C OSS V OSS V DS 3 4 C R = --- C OSS 3 15 Application Note 9506 Derivation of Equation 10 Determine switched VDS for tLL Skew: ∆tLL tSW When the energy in the resonant inductor is equal to the energy in the resonant capacitance the critical point of ZVS operation is reached. When energy in the resonant inductor is below the stored MOSFET capacitance energy there is Non-ZVS operation. When it is above there is ZVS operation. Therefore: VIN 1 3 ----2 2 2 1 C R × V OSS × V DS = --- × L R × I PRI 2 VMIN Where tSW is the MOSFET switching time during the nonzvs portion of the waveform. This can be caused by a delay too long as shown or by a delay too short. VDS is essentially VIN, where VIN is the maximum input voltage. I PRI ( Critical ) = 1 3 ----2 2 2 × C R × V OSS × V IN ( MAX ) V MIN 1 ∆t LL = ----------------------- × arc sin -------------- 2πF RES V IN --------------------------------------------------------------------------LR Derivation of Equation 11 V MIN sin ( ω RES × ∆t LL ) = -------------V IN The energy of the resonant capacitance CR can be displaced by the energy in the resonant inductance LR. When this happens the capacitive turn on loss is equal to zero: V SWLL ( C OSS, V IN ) = V IN × sin ( ω RES × ∆t LL ( C OSS ) ) 1 3 ----2 2 2 1 C R × V OSS × V DS – --- × L R × I PRI = 0 2 Determine switched VDS for tRL Skew: From Equation 3: Since VDS is essentially VIN, the power required to displace the resonant capacitance is: ∆t RL ( C OSS ) × I PRICRIT V SWRL ( C OSS ) = -------------------------------------------------------------------- 1 3 ---- 2 2 2 1 P SWLOSS = C R × V OSS × V IN – --- × L R × I PRI × F XFMR 2 C Combining: 1 3 ----2 2 1 2 V × – --- × L × I C ×V OSS IN R R PRI 2 P = --------------------------------------------------------------------------------------------------- SWLOSS C ,V t CLK 0SS IN 1 F XFMR = ---------------2t CLK Substituting and multiplying by two since there are two such transitions per period: P SWLOSS = R I PRI × V SWLL C OSS, V IN × t SWLL + -------------------------------------------------------------------------------------------------------------t CLK 1 3 ----2 2 2 1 C R × V OSS × V IN – --- × L R × I PRI 2 ---------------------------------------------------------------------------------------- × 2 2t CLK I PRI × V SWRL C OSS × t SWRL + -------------------------------------------------------------------------------------------------t CLK 1 3 ----2 2 2 1 C R × V OSS × V IN – --- × L R × I PRI 2 = ---------------------------------------------------------------------------------------t CLK From the ZVS Transition times: π ∆t LL ( C OSS ) = --- × C R ( C OSS ) × L R – t LL 2 C R ( C OSS ) × 72 ∆t RL ( C OSS ) = ------------------------------------------------- – t RL I PRICRIT ( C OSS ) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 16

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