AN9998: HC55185 and the IDT821054/64 Programmable Quad PCM CODEC

HC55185 and the IDT821054/64 Programmable
Quad PCM CODEC
®
Application Note
April 2002
AN9998
Author: Don LaFontaine
Reference Design using the HC55185 and
the IDT821054/64 Programmable Quad
PCM CODEC
R S = 133.3 • ( Z L – 2RP ) = 133.3 • ( 600Ω – 2R P )
(EQ. 1)
The value of RS with 49Ω protection resistors is 66.9kΩ. The
closest standard value is 66.5kΩ.
The purpose of this application note is to provide a reference
design for the HC55185 and IDT821054/64 Programmable
Quad PCM CODECs.
SLIC in the Active Mode
Figure 2 shows a simplified AC transmission model of the
HC55185 and the connection of the IDT821054/64 to the
SLIC. Circuit analysis of the HC55185 yields the following
design equations:
The network requirements of many countries require the
analog subscriber line circuit (SLIC) to terminate the
subscriber line with an impedance for voiceband frequencies
which is complex, rather than resistive (e.g. 600Ω). The
HC55185 accomplishes this impedance matching with a
single network connected between the VTX pin and the -IN
pin.
The Sense Amplifier is configured as a 4 input differential
amplifier with a gain of 3/4. The voltage at the output of the
sense amplifier (VSA) is calculated using superposition.
VSA1 is the voltage resulting from V1, VSA2 is the voltage
resulting from V2 and so on (reference Figure 2).
The IDT821054/64 Quad PCM CODECs uses an intergrated
programmable DSP to realize AC Impedance Matching,
Transhybrid Balance, Frequency Response Correction and
Gain Setting functions.
Discussed in this application note are the following:
• 2-wire impedance matching.
• Receive gain (4-wire to 2-wire) and transmit gain
(2-wire to 4-wire) calculations.
• Reference design for both 600Ω and
200Ω +680Ω||0.1µF (China Complex Impedance).
Impedance Matching
Impedance matching of the HC55185 to the subscriber load
is important for optimization of 2 wire return loss, which in
turn cuts down on echoes in the end to end voice
communication path. Impedance matching of the HC55185 is
accomplished by making the SLIC’s impedance (ZO, Figure 1)
equal to the desired terminating impedance ZL, minus the
value of the protection resistors (RP).
3
V SA 1 = – --- ( V 1 )
4
(EQ. 2)
3
V SA 2 = --- ( V 2 )
4
(EQ. 3)
3
V SA 3 = – --- ( V 3 )
4
(EQ. 4)
3
V SA 4 = --- ( V 4 )
4
(EQ. 5)
3
3
V SA = [ ( V 2 – V 1 ) + ( V 4 – V 3 ) ] --- = [ ∆V + ∆V ] --4
4
(EQ. 6)
Where ∆V is equal to IMRSENSE (RSENSE = 20Ω)
3
V SA = 2 ( ∆I M × 20 ) --- = ∆I M 30
4
(EQ. 7)
The voltage at VTX is equal to:
RS
RS
V TX = – V SA  -------- = –  -------- ∆I M 30
 8K
 8K
With the HC55185 programmed to match a ZL of 600Ω, the
IDT821054/64 uses an intergrated programmable DSP to
realize any AC impedance. The formula to program the
HC55185 to match a 2-wire impedance of 600Ω is shown in
Equation 1.
(EQ. 8)
VTR is defined in Figure 2, note polarity assigned to VTR:
V TR = 2 ( V RX + V TX )
(EQ. 9)
CRX 0.47µF
VRX
RP
49Ω
TIP
+
V2W
-
+
ZL
INTERSIL
HC55185
VTX
VTR
-
EG
66.5kΩ
-IN
ZO
ZTR
ZO = ZL - 2RP
RESISTIVE
ZL = ZTR = 600Ω
RS
RING
RP
49Ω
RS
CTX 0.47µF
CFB
RS = 133.3(600 - 2*49)
RS
66.9kΩ
Std value
66.5kΩ
4.7µF
VFB
FIGURE 1. IMPEDANCE MATCHING
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
AN9998
Substitute Equation 10 for RS and -V2w/ZL for ∆IM into
Equation 15.
Setting VRX equal to zero, substituting EQ. 8 into EQ. 9 and
defining ZO = -VTR/∆IM will enable the user to determine the
require feedback to match the line impedance at V2W.
1
Z O = ------------------ R S
133.33
Z O V 2W
V TR = 2V RX + -------------------Z
(EQ. 10)
(EQ. 16)
L
Loop Equation at Tip/Ring interface
R S = 133.33 ( Z L – 2R P )
(EQ. 17)
V 2W -I M 2R P + V TR = 0
ZO is the source impedance of the device and is defined as
ZO = ZL - 2Rp. ZL is the line impedance. RS is defined as:
Substitute Equation16 into Equation 17 and combine terms
(EQ. 11)
Z L + Z O + 2R P
V 2W -------------------------------------- = – 2V RX
ZL
(EQ. 18)
Node Equation at HC55185 VRX input
V RX V TX
I X = ----------- + ----------R
R
where:
(EQ. 12)
VRX = The input voltage at the VRX pin.
VSA = An internal node voltage that is a function of the loop
current and the output of the Sense Amplifier.
IX = Internal current in the SLIC that is the difference between
the input receive current and the feedback current.
Substitute Equation 8 into Equation 12
V RX
R S ∆I M 30
I X = ----------- –  -------------------------
 R8K 
R
(EQ. 13)
IM = The AC metallic current.
RP = A protection resistor (typical 49.9Ω).
Loop Equation at HC55185 feed amplifiers and load
(EQ. 14)
I X R - V TR + I X R = 0
RS = An external resistor/network for matching the line
impedance.
VTR = The tip to ring voltage at the output pins of the SLIC.
V2W = The tip to ring voltage including the voltage across the
protection resistors.
Substitute Equation 13 into Equation 14
R S ∆I M 60
V TR = 2V RX –  -------------------------


8K
(EQ. 15)
ZL = The line impedance.
ZO = The source impedance of the device.
IX
+
-
TIP
R
I
+ M
-
V2
RSENSE
ZL
IM
IDT821054/64
Receive Block
+
Feed
Amplifier
VIN
IX
R
1:1
VOUT1
+
VIN1
CHANNEL 3
+
VTX
E
- G
- IM +
RP
Filter and A/D
CHANNEL 2
-
RING
D/A and Filter
R
VTR
+
CHANNEL 1
VRX
VRX
-
Z0
+
+
V2W
-
IX
V1
20Ω
I
+ M -
RP
-
INTERSIL
HC55185 (1 of 4 )
RSENSE
V3
V4
+
Feed
Amplifier
VTX
-
+
-
20Ω
- IM +
CHANNEL 4
+
IX
-
TA
Feedback Amplifier
R
+
4R
3R
-IN
4R
4R
+
4R
3R
RS
8k
CFB
VFB
VSA = ∆IM30
Sense Amplifier
FIGURE 2. HC55185 SIMPLIFIED AC TRANSMISSION CIRCUIT AND IDT821054/64
2
DSP
Core PCM/GCI
Interface
DR1/DD
DX1/DU
AN9998
HC55185 Receive Gain (VRX to V2W)
4-wire to 2-wire gain across the HC55185 is equal to the
V2W divided by the input voltage VRX, reference Figure 2.
The receive gain is calculated using Equation 18.
Equation 19 expresses the receive gain (VRX to V2W) in
terms of network impedances. From Equation 11, the value
of RS was set to match the line impedance (ZL) to the
HC55185 plus the protection resistors (Z0 + 2RP). This
results in a 4-wire to 2-wire gain of -1, as shown in EQ19.
V 2W
ZL
ZL
G 4-2 = ------------ = -2 ---------------------------------------- = -2 -------------------- = – 1
V RX
Z L + Z O + 2 RP
Z L + ZL
(EQ. 19)
Receive Gain Across the System
The receive gain across the system is defined as the gain
from the PCM highway to the phone (V2W). With the receive
gain through the HC55185 set to 1, the receive gain across
the system is entirely controlled by programming the
IDT821054/64. The IDT821054/64 can program the receive
gain across the system in two ways (reference Figure 3).
• The first is by programming the signal gain in its analog
form. The analog receive gain, also known as Digital to
Analog (D/A) gain, can be programmed in the
IDT821054/64 to be either 0dB or -6dB.
• The second is by programming the signal gain (via.
coefficients) when its in digital form. The digital form of
the receive path can be programmed from +3 to -12dB
with minimum 0.1dB steps.
This results in a possible receive gain (D/A) programming
range from +3dB to -18dB. Note: Analog gain brings less
noise than digital gain. When allocating the CODEC
gain, the majority of the required gain should be
preformed in the analog stage.
Reference section titled “Information Required for IDT to
Calculate IDT821054/64 CODEC DSP Coefficients” for
information on obtaining coefficients for your design.
Transmit Gain Across HC55185
(EG to VTX)
The 2-wire to 4-wire gain is equal to VTX/EG with VRX = 0,
reference Figure 2.
Loop Equation
(EQ. 20)
– E G + Z L I M + 2RP I M – VTR = 0
From Equation 16 with VRX = 0
Z O V 2W
V TR = -------------------ZL
(EQ. 21)
Substituting Equation 21 into Equation 20 and simplifying.
Z L + 2R P + Z O
E G = – V 2W --------------------------------------ZL
(EQ. 22)
Substituting Equation 10 into Equation 8 and defining
∆IM = -V2W/ZL results in Equation 23 for VTX.
3
V 2W Z L – 2R P
V TX = ------------ -----------------------ZL
2
(EQ. 23)
Combining Equations 22 and 23 results in Equation 24.
ZO
V TX
Z L – 2R P
(EQ. 24)
G 2-4 = ---------- = – ------------------------------------------------ = – -----------------------------------------------EG
2 ( Z L + 2R P + Z O )
2 ( Z L + 2R P + Z O )
A more useful form of the equation is rewritten in terms of
VTX /V2W. A voltage divider equation is written to convert
from EG to V2W as shown in Equation 25.
 Z O + 2 RP 
V 2W =  ---------------------------------------- E G
 Z L + Z O + 2 RP
(EQ. 25)
Substituting ZL = ZO + 2RP and rearranging Equation 25 in
terms of EG results in Equation 26.
E G = 2V2W
(EQ. 26)
Substituting Equation 26 into Equation 24 results in an
equation for 2-wire to 4-wire gain that’s a function of the
synthesized input impedance of the SLIC and the protection
resistors.
V TX
ZO
G 2-4 = ------------ = – -------------------------------------------- = 0.416
V 2W
( Z L + 2R P + Z O )
(EQ. 27)
ZL is set to 600Ω, ZO is programmed with RS to be 498.76Ω
(66.5kΩ/133.33), and RP is equal to 49.9Ω. This results in a
2-wire to 4-wire gain of 0.416 or -7.6dB.
Transmit Gain Across the System
The transmit gain across the system is defined as the gain
from the phone or 2-wire side (V2W) to the PCM highway.
Setting the gain of the IDT821054/64 will have to account for
the attenuated signal through the HC55185. The system
gain is entirely controlled by programming the
IDT821054/64. The IDT821054/64 can program the transmit
gain across the system in two ways (reference Figure 3).
• The first is by programming the signal gain in its analog
form. The analog transmit gain, also known as Analog
to Digital (A/D) gain, can be programmed in the
IDT821054/64 to be either 0dB or +6dB.
• The second is by programming the signal gain (via.
coefficients) when its in digital form. The digital form of
the transmit path can be programmed from -3dB to
+12dB with minimum 0.1dB steps.
This results in a possible transmit gain (A/D) programming
range from -3dB to +18dB. Note: Analog gain brings less
noise than digital gain. When allocating the CODEC
gain, the majority of the required gain should be
preformed in the analog stage.
Reference section titled “Information Required for IDT to
Calculate IDT821054/64 CODEC DSP Coefficients” for
information on obtaining coefficients for your design.
AN9998
INTERSIL
HC55185 (1of 4 )
RP
49Ω
VRX
TIP
+
V2W
-
CHANNEL 1
CRX
+
ZL
Analog
Gain
0dB to -6dB
Digital
Gain
+3dB to -12dB
VIN1
Analog
Gain
0dB to +6dB
Digital
Gain
-3dB to +12dB
FRR
filter
Receive path
CTX
VTX
RING
RP
49Ω
ZTR
VOUT1
0.47µf
VTR
-
EG
IDT821054/64
0.47µf
RS
CFB
ZO = ZL - 2RP
VFB
Transmit path
CHANNEL 2
-IN
ZO
FRX
filter
4.7µf
..
.
DSP
Core PCM/GCI
Interface
DR1/DD
DX1/DU
CHANNEL 4
FIGURE 3. RECEIVE GAIN G(4-2), TRANSMIT GAIN (2-4)
Transhybrid Balance G(4-4)
Transhybrid balance is a measure of how well the input
signal is canceled (that being received by the SLIC) from the
transmit signal (that being transmitted from the SLIC to the
CODEC). Without this function, voice communication would
be difficult because of the echo. The Transhybrid balancing
filter inside the IDT821054/64 is used to adjust transhybrid
balance to ensure the echo cancellation meets the ITU-T
specifications. The coefficient for Echo Cancellation is ECF.
Frequency Response Correction
The FRR filter in the receive path and the FRX filter in the
transmit path can be programmed to correct any frequency
distortion caused by the impedance matching filters. The
coefficients of Frequency Response Correction are FRR for
receive path and FRX for the transmit path.
Information Required for IDT to Calculate
IDT821054/64 CODEC DSP Coefficients
For IDT to calculate IDT821054/64 DSP coefficient,
customers should provide the following information about
their subscriber line card:
• Accurate SLIC PSPICE model. It can be provided in .lib
file or PSPICE schematic file.
• System Impedance
• Gain (Transmit path and Receive path)
Using the DSP coefficients provided by IDT, the overall
performance of the system will pass ITU-T requirements.
When the COF RAM button is selected from the MPI
Operation General Interface screen, the COF RAM
Operation screen will appear (Figure 4). From this screen,
the user can configure all the coefficients for the current
channel.
FIGURE 4. COEFFICIENT RAM OPERATION SCREEN
Reference Design of the HC55185 and the
IDT821054/64 With a 600Ω Load
The design criteria is as follows:
• 4-wire to 2-wire gain (DR1/DD to V2W) equal 0dB
• 2-wire to 4-wire gain (V2W to DX1/DU) equal 0dB
• Rp = 49.9Ω
Figure 5 gives the reference design using the Intersil
HC55185 and the IDT821054/64 Programmable Quad PCM
CODEC. Also shown in Figure 5 are the voltage levels at
specific points in the circuit.
Impedance Matching
The 2-wire impedance is matched to the line impedance Z0
using Equation 1, repeated here in Equation 28.
R S = 133.3 • ( Z L – 2RP )
(EQ. 28)
For a line impedance of 600Ω, RS equals:
R S = 133.3 • ( 600 – 98 ) = 66.9kΩ
(EQ. 29)
The closest standard value for RS would be 66.5kΩ.
4
AN9998
G4-2
System Requirements:
Impedance: 600Ω
Transmit Gain (A/D): 0dB
Receive Gain (D/A): 0dB
0dBm0(600Ω)
0.7745VRMS
0dBm0(600Ω)
0dBm0(600Ω)
0.7745VRMS
0.7745VRMS
INTERSIL
HC55185 (1 of 4 )
RP
49Ω
VRX
TIP
+
V2W
-
CHANNEL 1
CRX
+
ZL
VOUT1
Analog
Gain
0dB
Digital
Gain
0dB
VIN1
Analog
Gain
6dB
Digital
Gain
+1.6dB
0.47µf
VTR
-
EG
RING
VTX
RS 0.47µf
66.5kΩ
ZO = ZL - 2RP
CFB
0.7745VRMS
VFB
DSP
Core PCM/GCI
Interface
DR1/DD
DX1/DU
CHANNEL 4
-IN
0dBm0(600Ω)
PCM
Bus
Transmit path
.
.
.
CTX
ZO
Receive path
CHANNEL 2
RP
49Ω
ZTR
IDT821054/64
-7.5769dBm0(600Ω)
4.7µf
REFERENCE TABLE 1
FOR COEFFICIENTS
0.3239VRMS
0dBm0(600Ω)
0.7745VRMS
G2-4
FIGURE 5. REFERENCE DESIGN OF THE HC55185 AND THE IDT821054/64 WITH A 600Ω LOAD IMPEDANCE
However, it would be very convenient and cost effective if
system manufacturers can use only one type of line card to
meet different impedance requirements and different gain
requirements. The programmability of IDT821054/64 can
help system manufactures to reach this goal. By using
different coefficients this reference design can meet both
600Ω and 200Ω + 680Ω||0.1µ F impedance requirements.
With the value of RS selected to be 66.5kΩ ± 1%, the
coefficients (with a line impedance of 600Ω) are given in
Table 1.
system is 0dB (-2.19dB(811Ω) = -3.5dB(600Ω)) as explained
in the following section.
Adjustment to Get -3.5dBm0 at the Load
Referenced to 600Ω
The voltage equivalent to 0dBm0 into 811Ω (0dBm0(811Ω))
is calculated using Equation 30 (811Ω is the impedance of
complex China load at 1020Hz).
2
V
0dBm ( 811Ω ) = 10 log ------------------------------ = 0.90055V RMS
811 ( 0.001 )
(EQ. 30)
The gain referenced back to 0dBm0(600Ω) is equal to:
Specific Implementation for China
0.90055V RMS
GAIN = 20 log -------------------------------------- = 1.309dB
0.7745V RMS
The design criteria for a China specific solution are as
follows:
The adjustment to get -3.5dBm0 at the load referenced to
600Ω is:
• Desired line circuit impedance is 200 + 680//0.1µF
Adjustment = – 3.5dBm0 + 1.309dBm0 = – 2.19 dB
(EQ. 31)
(EQ. 32)
• Receive gain (V2W/(DR1/DD)) is -3.5dB
• Transmit gain ((DX1/DU)/V2W) is 0dB
• 0dBm0 is defined as 1mW into the complex impedance at
1020Hz
• Rp = 49.9Ω
Figure 6 gives the reference design using the Intersil
HC55185 and the IDT821054/64 Programmable Quad PCM
CODEC. Also shown in Figure 6 are the voltage levels at
specific points in the circuit. Note: The transmit gain of the
5
The voltage at the load (referenced to 600Ω) is given in
Equation 33:
2
V
– 2.19 dBm ( 600Ω ) = 10 log ------------------------------ = 0.60196V RMS (EQ. 33)
600 ( 0.001 )
Impedance Matching
With the value of RS selected to be 66.5kΩ ± 1%, the
coefficients (with a line impedance of 200Ω + 680Ω||0.1µ F)
are given in Table 2.
AN9998
G4-2
System Requirements:
Impedance: 200Ω+600Ω||0.1µF
Transmit Gain (A/D): 0dB
Receive Gain (D/A): -3.5dB
-2.19dBm0(600Ω)
0.60196VRMS
RP
49Ω
CRX
TIP
+
V2W
-
VRX
+
ZL
VTR
-
EG
0.47µf
-2.19dBm0(600Ω)
0.60196VRMS
CHANNEL 1
VPWRO+
Analog
VOUT1
Gain
0dB
VIN1
RING
RP
49Ω
ZTR
IDT821054/64
Digital
Gain
-2.19dB
Receive path
Digital
Gain
+1.6dB
Analog
Gain
+6dB
Transmit path
CHANNEL 2
INTERSIL
HC55185
ZO
RS 0.47µf
66.5kΩ
ZO = ZL - 2RP
DSP
Core PCM/GCI
Interface
.
.
.
CTX
VTX
0dBm0(600Ω)
0.7745VRMS
DR1/DD
DX1/DU
CHANNEL 4
-IN
CFB
REFERENCE TABLE 2
FOR COEFFICIENTS
4.7µf
VFB
-2.19dBm0(600Ω)
-9.3294dBm0(600Ω)
0.60196VRMS
0.26461RMS
VPCMOUT
-3.5dBm0(600Ω)
0.51769VRMS
G2-4
FIGURE 6. REFERENCE DESIGN OF THE HC55185 AND THE IDT821054/64 WITH CHINA COMPLEX LOAD IMPEDANCE
TABLE 1. 600Ω COEFFICIENTS, SYSTEM GAINS: (TRANSMIT GAIN (0dB), RECEIVE GAIN (0dB)),
CODEC ANALOG GAINS: (TRANSMIT PATH +6dB, RECEIVE PATH 0dB)
Coefficient RAM
CHANNEL 1
IMF:
47
08
53
F5
00
00
00
00
00
00
00
00
00
00
00
00
ECF:
3C
03
00
00
00
00
00
00
00
00
56
62
F4
D6
00
00
KM:
00
00
34
E6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
36
02
97
DE
95
48
95
48
97
DE
36
02
99
31
GTX FF
1F
ACR:
F8
00
55
FD
70
3F
70
3F
55
FD
F8
00
CE
84
GRX 0C
03
Coefficient RAM
CHANNEL 2
IMF:
47
08
53
F5
00
00
00
00
00
00
00
00
00
00
00
00
ECF:
3C
03
00
00
00
00
00
00
00
00
56
62
F4
D6
00
00
KM:
00
00
34
E6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
36
02
97
DE
95
48
95
48
97
DE
36
02
99
31
GTX FF
1F
ACR:
F8
00
55
FD
70
3F
70
3F
55
FD
F8
00
CE
84
GRX 0C
03
Coefficient RAM
CHANNEL 3
IMF:
47
08
53
F5
00
00
00
00
00
00
00
00
00
00
00
00
ECF:
3C
03
00
00
00
00
00
00
00
00
56
62
F4
D6
00
00
KM:
00
00
34
E6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
36
02
97
DE
95
48
95
48
97
DE
36
02
99
31
GTX FF
1F
ACR:
F8
00
55
FD
70
3F
70
3F
55
FD
F8
00
CE
84
GRX 0C
03
6
AN9998
TABLE 1. 600Ω COEFFICIENTS, SYSTEM GAINS: (TRANSMIT GAIN (0dB), RECEIVE GAIN (0dB)),
CODEC ANALOG GAINS: (TRANSMIT PATH +6dB, RECEIVE PATH 0dB) (Continued)
Coefficient RAM
CHANNEL 4
IMF:
47
08
53
F5
00
00
00
00
00
00
00
00
00
00
00
00
ECF:
3C
03
00
00
00
00
00
00
00
00
56
62
F4
D6
00
00
KM:
00
00
34
E6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
36
02
97
DE
95
48
95
48
97
DE
36
02
99
31
GTX FF
1F
ACR:
F8
00
55
FD
70
3F
70
3F
55
FD
F8
00
CE
84
GRX 0C
03
TABLE 2. 200Ω + 680Ω || 0.1µF COEFFICIENTS, SYSTEM GAINS: (TRANSMIT GAIN (0dB), RECEIVE GAIN (-3.5dB)),
CODEC ANALOG GAINS: (TRANSMIT PATH +6dB, RECEIVE PATH 0dB))
COEFFICIENT RAM
CHANNEL 1
IMF:
52
F8
20
1D
00
00
00
00
22
65
00
00
00
00
00
00
ECF:
0B
03
00
00
00
00
00
00
00
00
36
72
29
C2
00
00
KM:
00
00
74
C6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
C9
FE
9C
10
D4
45
D4
45
9C
10
C9
FE
00
38
GTX
FF
1F
ACR:
0A
FA
1D
0D
AF
39
AF
39
1D
0D
0A
FA
CE
84
GRX
0C
03
COEFFICIENT RAM
CHANNEL 2
IMF:
52
F8
20
1D
00
00
00
00
22
65
00
00
00
00
00
00
ECF:
0B
03
00
00
00
00
00
00
00
00
36
72
29
C2
00
00
KM:
00
00
74
C6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
C9
FE
9C
10
D4
45
D4
45
9C
10
C9
FE
00
38
GTX
FF
1F
ACR:
0A
FA
1D
0D
AF
39
AF
39
1D
0D
0A
FA
CE
84
GRX
0C
03
COEFFICIENT RAM
CHANNEL 3
IMF:
52
F8
20
1D
00
00
00
00
22
65
00
00
00
00
00
00
ECF:
0B
03
00
00
00
00
00
00
00
00
36
72
29
C2
00
00
KM:
00
00
74
C6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
C9
FE
9C
10
D4
45
D4
45
9C
10
C9
FE
00
38
GTX
FF
1F
ACR:
0A
FA
1D
0D
AF
39
AF
39
1D
0D
0A
FA
CE
84
GRX
0C
03
COEFFICIENT RAM
CHANNEL 4
IMF:
52
F8
20
1D
00
00
00
00
22
65
00
00
00
00
00
00
ECF:
0B
03
00
00
00
00
00
00
00
00
36
72
29
C2
00
00
KM:
00
00
74
C6
00
00
00
00
00
00
00
00
00
00
00
00
ACT:
C9
FE
9C
10
D4
45
D4
45
9C
10
C9
FE
00
38
GTX
FF
1F
ACR:
0A
FA
1D
0D
AF
39
AF
39
1D
0D
0A
FA
CE
84
GRX
0C
03
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
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