UniSLIC14 and the IDT821054/64 Programmable Quad CODEC ® Application Note May 2002 AN9999.0 Author: Don LaFontaine Reference Design using the UniSLIC14 and the IDT821054/64 Programmable Quad CODEC to calculate the proper ZT for matching the 2-wire impedance is shown in Equation 1. With the UniSLIC14 programmed to match a ZL of 600Ω, the IDT821054/64 uses an intergrated programmable DSP to realize any AC impedance. The purpose of this application note is to provide a reference design for the UniSLIC14 and IDT821054/64 Programmable Quad CODEC. The network requirements of many countries require the analog subscriber line circuit (SLIC) to terminate the subscriber line with an impedance for voiceband frequencies which is complex, rather than resistive (e.g. 600Ω). The UniSLIC14 accomplishes this impedance matching with a single network connected to the ZT pin. The value of ZT with 30Ω protection resistors is108kΩ. The closest standard value is 107kΩ. SLIC in the Active Mode Figure 2 shows a simplified AC transmission model of the UniSLIC14 and the connection of the IDT821054/64 to the SLIC. Circuit analysis of the UniSLIC14 yields the following design equations: The IDT821054/64 Quad PCM CODEC uses an intergrated programmable DSP to realize AC Impedance Matching, Transhybrid Balance, Frequency Response Correction and Gain Setting functions. Discussed in this application note are the following: • 2-wire impedance matching. • Receive gain (4-wire to 2-wire) and transmit gain (2wire to 4-wire) calculations. • Reference design for both 600Ω and 200Ω +680Ω||0.1µF (China Complex Impedance). RING (EQ. 5) Loop Equation at UniSLIC14 feed amplifier and load IX 500k - V TR + IX 500k = 0 CRX 0.47µF (EQ. 6) ZT RESISTIVE CTX 0.47µF VTX VTR - (EQ. 4) IM ( ZTR – 2R P ) VRX IX = ------------- - ----------------------------------------500k 1000k TIP ZL = ZTR = 600Ω ZT = 200(600 - 2*30) ZT ZT RP 30Ω ZTR (EQ. 3) VRX + VS IM VA = ------- ( Z TR – 2R P ) 2 Substitute Equation 3 into Equation 4 INTERSIL UniSLIC14 ZL (EQ. 2) VA V RX ------------- - ------------- = I X 500k 500k Impedance matching of the UniSLIC14 to the subscriber load is important for optimization of 2 wire return loss, which in turn cuts down on echoes in the end to end voice communication path. It is also important for maintaining voice signal levels on long loops. Impedance matching of the UniSLIC14 is accomplished by making the SLIC’s impedance (ZO, Figure 1) equal to the desired terminating impedance ZL, minus the value of the protection resistors (RP). The formula + V2W - 1 V A = I M × 2R S × ---------- × 200 ( ZTR – 2R P ) × 5 80k Node Equation at UniSLIC14 VRX input Impedance Matching RP 30Ω (EQ. 1) ZT = 200 • ( Z TR – 2R P ) ZT 108kΩ Std. value 107kΩ ZO PTG FLOATING FIGURE 1. IMPEDANCE MATCHING 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved AN9999 ZT = An external resistor/network for matching the line impedance. Substitute Equation 5 into Equation 6 (EQ. 7) VTR = 2V RX – IM ( ZTR – 2RP ) VTR = The tip to ring voltage at the output pins of the SLIC. Loop Equation at Tip/Ring interface V 2W -I M 2RP + VTR = 0 V2W = The tip to ring voltage including the voltage across the protection resistors. Substitute Equation 7 into Equation 8 ZL = The line impedance. (EQ. 8) ZO = The source impedance of the SLIC . (EQ. 9) V2W = I M Z TR – 2V RX ZTR = The input impedance of the SLIC including protection resistors. Substituting -V2W/ZL into Equation 9 for IM and rearranging to solve for V 2W results in Equation 10. Z TR V 2W 1 + ----------- = – 2 VRX ZL Receive Gain (VRX to V2W) (EQ. 10) 4-wire to 2-wire gain across the UniSLIC14 is equal to the V2W divided by the input voltage VRX, reference Figure 2.The receive gain is calculated using Equation 10. where: VRX = The input voltage at the VRX pin. Equation 11 expresses the receive gain (V RX to V2W) in terms of network impedances. From Equation 1, the value of ZT was set to match the line impedance (ZL) to the UniSLIC14 plus the protection resistors (ZO + 2RP). This results in a 4-wire to 2-wire gain of -1, as shown in Equation 11. VA = An internal node voltage that is a function of the loop current detector and the impedance matching networks. IX = Internal current in the SLIC that is the difference between the input receive current and the feedback current. IM = The AC metallic current. V 2W ZL ZL G 4-2 = ------------ = -2 ---------------------------------------- = -2 -------------------- = – 1 VRX Z L + Z O + 2 RP ZL + Z L RP = A protection resistor (typical 30Ω). IX TIP 500K I + M - RS + 20Ω VOUT1 + VIN1 VRX - 500K CHANNEL 1 VRX 500K IX ZL - IDT821054/64 VIN IX RINT 20Ω RP D/A and Filter Filter and A/D CHANNEL 2 IM - + + V2W - INTERSIL UniSLIC14 (1 of 4) + - (EQ. 11) CHANNEL 3 VTR + IX + E - G A=1 + VTX CHANNEL 4 + - IM + RING RP RS VTX - RINT 20Ω + IX 20Ω + - 500K - PTG 500K 1/80K ZTR FLOATING 5 500K VA = IM(ZTR-2RP) 2 ZT = 200 (ZTR - 2RP) FIGURE 2. UniSLIC14 SIMPLIFIED AC TRANSMISSION CIRCUIT AND IDT821054/64 2 DSP Core PCM/GCI Interface DR1/DD DX1/DU AN9999 Receive Gain Across the System The receive gain across the system is defined as the gain from the PCM highway to the phone (V2W). With the receive gain through the UniSLIC14 set to 1, the receive gain across the system is entirely controlled by programming the IDT821054/64. The IDT821054/64 can program the receive gain across the system in two ways (reference Figure 3). • The first is by programming the signal gain in its analog form. The analog receive gain, also known as Digital to Analog (D/A) gain, can be programmed in the IDT821054/64 to be either 0dB or -6dB. • The second is by programming the signal gain (via. coefficients) when its in digital form. The digital form of the receive path can be programmed from +3 to -12dB with minimum 0.1dB steps. To match a 600Ω line, ZTR is set to 595Ω (EQ 1, 107k/200+60) where RP is equal to 30.0Ω. This results in a 2-wire to 4-wire gain of 0.9 or -0.915dB (EQ 17, 595-60/595). Notice that the phase of the 2-wire to 4-wire signal is in phase with the input signal and that the gain will always be less than one because of the protection resistors. Transmit Gain Across the System The transmit gain across the system is defined as the gain from the phone or 2-wire side (V2W) to the PCM highway. Setting the gain of the IDT821054/64 will have to account for the attenuated signal through the UniSLIC14. The system gain is entirely controlled by programming the IDT821054/64. The IDT821054/64 can program the transmit gain across the system in two ways (reference Figure 3). This results in a possible receive gain (D/A) programming range from +3dB to -18dB. Note: Analog gain brings less noise than digital gain. When allocating the CODEC gain, the majority of the required gain should be preformed in the analog stage. • The first is by programming the signal gain in its analog form. The analog transmit gain, also known as Analog to Digital (A/D) gain, can be programmed in the IDT821054/64 to be either 0dB or +6dB. Reference section titled “Information Required for IDT to Calculate IDT821054/64 CODEC DSP Coefficients” for information on obtaining coefficients for your design. • The second is by programming the signal gain (via. coefficients) when its in digital form. The digital form of the transmit path can be programmed from -3dB to +12dB with minimum 0.1dB steps. Transmit Gain Across UniSLIC14 (EG to VTX) The 2-wire to 4-wire gain is equal to V TX/ EG with V RX = 0, reference Figure 2. Loop Equation (EQ. 12) – E G + ZL I M + 2R P IM – VTR = 0 From Equation 7 with VRX = 0 V TR = – IM ( ZTR – 2R P ) (EQ. 13) Substituting Equation 13 into Equation 12 and simplifying. E G = I M ( Z L + ZTR ) (EQ. 14) By design, VTX = -VTR, therefore, V TX I M ( Z TR – 2R P ) ( ZTR – 2R P ) G 2-4 = ---------- = ---------------------------------------- = --------------------------------EG ( Z L + ZTR ) I M ( Z L + ZTR ) (EQ. 15) A more useful form of the equation is rewritten in terms of VTX /V 2W. A voltage divider equation is written to convert from EG to V2W as shown in Equation 16. ZTR V 2W = ------------------------ E G Z TR + Z L (EQ. 16) Rearranging Equation 16 in terms of EG, and substituting into Equation 15 results in an equation for 2-wire to 4-wire gain that’s a function of the synthesized input impedance of the SLIC and the protection resistors (Z TR). V TX ZTR - 2R P 600 – 60 G 2-4 = ------------ = ----------------------------- = ---------------------- = 0.9 600 V 2W Z TR 3 (EQ. 17) This results in a possible transmit gain (A/D) programming range from -3dB to +18dB. Note: Analog gain brings less noise than digital gain. When allocating the CODEC gain, the majority of the required gain should be preformed in the analog stage. Reference section titled “Information Required for IDT to Calculate IDT821054/64 CODEC DSP Coefficients” for information on obtaining coefficients for your design. Transhybrid Balance G(4-4) Transhybrid balance is a measure of how well the input signal is canceled (that being received by the SLIC) from the transmit signal (that being transmitted from the SLIC to the CODEC). Without this function, voice communication would be difficult because of the echo. The Transhybrid balancing filter inside the IDT821054/64 is used to adjust transhybrid balance to ensure the echo cancellation meets the ITU-T specifications. The coefficient for Echo Cancellation is ECF. Frequency Response Correction The FRR filter in the receive path and the FRX filter in the transmit path can be programmed to correct any frequency distortion caused by the impedance matching filters. The coefficients of Frequency Response Correction are FRR for receive path and FRX for the transmit path. AN9999 INTERSIL UniSLIC14 (1 of 4) RP 30Ω + ZL Analog Gain 0dB to -6dB Digital Gain +6dB to -12dB VIN1 Analog Gain 0dB to +6dB Digital Gain -6dB to +12dB ZT ZT RP 30Ω ZO FRR filter Receive path CTX 0.47µF RING ZTR VOUT1 VTX VTR - VS CRX 0.47µF VRX TIP + V2W - IDT821054/64 CHANNEL 1 PTG FLOATING FRX filter Transmit path CHANNEL 2 .. . DSP Core PCM/GCI Interface DR1/DD DX1/DU CHANNEL 4 FIGURE 3. RECEIVE GAIN G(4-2), TRANSMIT GAIN (2-4) Information Required for IDT to Calculate IDT821054/64 CODEC DSP Coefficients Reference Design of the UniSLIC14 and the IDT821054/64 With a 600Ω Load For IDT to calculate IDT821054/64 DSP coefficient, customers should provide the following information about their subscriber line card: The design criteria is as follows: • Accurate SLIC PSPICE model. It can be provided in .lib file or PSPICE schematic file. • System Impedance • Gain (Transmit path and Receive path) Using the DSP coefficients provided by IDT, the overall performance of the system will pass ITU-T requirements. When the COF RAM button is selected from the MPI Operation General Interface screen, the COF RAM Operation screen will appear (Figure 4). From this screen, the user can configure all the coefficients for the current channel. • 4-wire to 2-wire gain (DR1/DD to V2W) equal 0dB • 2-wire to 4-wire gain (V2W to DX1/DU) equal 0dB • Rp = 30Ω Figure 5 gives the reference design using the Intersil UniSLIC14 and the IDT821054/64 Programmable Quad PCM CODEC. Also shown in Figure 5 are the voltage levels at specific points in the circuit. Impedance Matching The 2-wire impedance is matched to the line impedance Z0 using Equation 1, repeated here in Equation 18. ZT = 200 • ( Z TR – 2R P ) (EQ. 18) For a line impedance of 600Ω, ZT equals: ZT = 200 • ( 600 – 60 ) = 108kΩ (EQ. 19) The closest standard value for ZT is 107kΩ. However, it would be very convenient and cost effective if system manufacturers can use only one type of line card to meet different impedance requirements and different gain requirements. The programmability of IDT821054/64 can help system manufactures to reach this goal. By using different coefficients this reference design can meet both 600Ω and 200Ω + 680Ω||0.1µ F impedance requirements. With the value of ZT selected to be 107kΩ ± 1%, the coefficients for Transmit Gain (A/D) and Receive Gain of zero (with a line impedance of 600Ω) is given in Table 1. FIGURE 4. COEFFICIENT RAM OPERATION SCREEN 4 AN9999 G4-2 System Requirements: Impedance: 600Ω Transmit Gain (A/D): 0dB Receive Gain (D/A): 0dB 0dBm0(600Ω) 0.7745VRMS 0dBm0 (600Ω) CRX 0.47µF + ZL Analog Gain 0dB Digital Gain 0dB VIN1 Analog Gain 0dB Digital Gain +0.9dB CTX 0.47µF Receive path RP 30Ω DSP Core PCM/GCI Interface . . . ZT ZO PCM Bus Transmit path CHANNEL 2 ZT RING ZTR IDT821054/64 VOUT1 VTX VTR - VS CHANNEL 1 VRX TIP + V2W - 0.7745VRMS 0.7745VRMS INTERSIL UniSLIC14 (1 of 4) RP 30Ω 0dBm0(600Ω) DR1/DD DX1/DU CHANNEL 4 ZO = ZL - 2RP PTG FLOATING 0dBm0(600Ω) -0.915dBm0 (600Ω) 0.7745VRMS 0.69714VRMS REFERENCE TABLE 1 FOR COEFFICIENTS 0dBm0(600Ω) 0.7745VRMS G2-4 FIGURE 5. REFERENCE DESIGN OF THE UniSLIC14 AND THE IDT821054/64 WITH A 600Ω LOAD IMPEDANCE Specific Implementation for China The design criteria for a China specific solution are as follows: • Desired line circuit impedance is 200 + 680//0.1µF • Receive gain (V2W/(DR1/DD)) is -3.5dB • Transmit gain ((DX1/DU)/V2W) is 0dB • 0dBm0 is defined as 1mW into the complex impedance at 1020Hz • Rp = 30Ω Figure 6 gives the reference design using the Intersil UniSLIC14 and the IDT821054/64 Programmable Quad CODEC. Also shown in Figure 6 are the voltage levels at specific points in the circuit. These voltages will be used to adjust the gains of the network. Adjustment to Get -3.5dBm0 at the Load Referenced to 600Ω The voltage equivalent to 0dBm0 into 811Ω (0dBm0(811Ω)) is calculated using Equation 20 (811Ω is the impedance of complex China load at 1020Hz). 2 V 0d Bm ( 811Ω ) = 10 log ------------------------------ = 0.90055V RMS 811 ( 0.001 ) (EQ. 20) The gain referenced back to 0dBm0(600Ω) is equal to: 0.90055V RMS G AIN = 20 log -------------------------------------- = 1.309dB 0.7745V RMS (EQ. 21) The adjustment to get -3.5dBm0 at the load referenced to 600Ω is: Adjus tm ent = – 3.5dBm0 + 1.309dBm0 = – 2.19 dB (EQ. 22) The voltage at the load (referenced to 600Ω) is given in Equation23: 2 V – 2.19 dBm ( 600Ω ) = 10 log ------------------------------ = 0.60196V RMS (EQ. 23) 600 ( 0.001 ) Impedance Matching Contact IDT for specific coefficiens for this design. 5 AN9999 I G4-2 System Requirements: Impedance: 200Ω+600Ω||0.1µF Transmit Gain (A/D): 0dB Receive Gain (D/A): -3.5dB -2.19dBm0(600Ω) -2.19dBm0(600Ω) 0.60196VRMS INTERSIL UniSLIC14 (1 of 4) TIP Analog Gain 0dB Digital Gain -2.19dB CTX 0.47µF VIN1 Analog Gain 0dB Digital Gain -0.4dB VTX VTR - VS VOUT1 VRX + ZL Receive path Transmit path CHANNEL 2 ZT RING RP 30Ω DSP Core PCM/GCI Interface . . . ZT DR1/DD DX1/DU CHANNEL 4 ZO ZTR IDT821054/64 CHANNEL 1 VPWRO+ CRX 0.47µF RP 30Ω + V2W - 0.60196VRMS 0dBm0(600Ω) 0.7745VRMS PTG FLOATING CONTACT IDT FOR COEFFICIENTS -2.19dBm0 (600Ω) -3.1dBm0(600Ω) 0.60196VRMS 0.54176 RMS VPCMOUT -3.5dBm0(600Ω) 0.51769VRMS G2-4 FIGURE 6. REFERENCE DESIGN OF THE UniSLIC14 AND THE IDT821054/64 WITH CHINA COMPLEX LOAD IMPEDANCE TABLE 1. 600Ω COEFFICIENTS, SYSTEM GAINS: (TRANSMIT GAIN (0dB), RECEIVE GAIN (0dB)), CODEC ANALOG GAINS: (TRANSMIT PATH +6dB, RECEIVE PATH 0dB) Coefficient RAM CHANNEL 1 IMF: 04 00 EE FF 00 00 00 00 00 00 00 00 00 00 00 00 ECF: C2 08 00 00 00 00 00 0 00 00 A2 5E 75 D9 00 00 KM: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 ACT: D7 00 F9 EF 16 25 16 25 F9 EF D7 00 99 31 GTX FF 1F ACR: FF 00 84 FE 49 3F 49 3F 84 FE FF 00 CE 84 GRX 0C 03 Coefficient RAM CHANNEL 2 IMF: 04 00 EE FF 00 00 00 00 00 00 00 00 00 00 00 00 ECF: C2 08 00 00 00 00 00 0 00 00 A2 5E 75 D9 00 00 KM: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 ACT: D7 00 F9 EF 16 25 16 25 F9 EF D7 00 99 31 GTX FF 1F ACR: FF 00 84 FE 49 3F 49 3F 84 FE FF 00 CE 84 GRX 0C 03 Coefficient RAM CHANNEL 3 IMF: 04 00 EE FF 00 00 00 00 00 00 00 00 00 00 00 00 ECF: C2 08 00 00 00 00 00 0 00 00 A2 5E 75 D9 00 00 KM: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 ACT: D7 00 F9 EF 16 25 16 25 F9 EF D7 00 99 31 GTX FF 1F ACR: FF 00 84 FE 49 3F 49 3F 84 FE FF 00 CE 84 GRX 0C 03 6 AN9999 TABLE 1. 600Ω COEFFICIENTS, SYSTEM GAINS: (TRANSMIT GAIN (0dB), RECEIVE GAIN (0dB)), CODEC ANALOG GAINS: (TRANSMIT PATH +6dB, RECEIVE PATH 0dB) (Continued) Coefficient RAM CHANNEL 4 IMF: 04 00 EE FF 00 00 00 00 00 00 00 00 00 00 00 00 ECF: C2 08 00 00 00 00 00 0 00 00 A2 5E 75 D9 00 00 KM: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 ACT: D7 00 F9 EF 16 25 16 25 F9 EF D7 00 99 31 GTX FF 1F ACR: FF 00 84 FE 49 3F 49 3F 84 FE FF 00 CE 84 GRX 0C 03 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7

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