DATASHEET

HS-0546RH, HS-0547RH
®
Data Sheet
March 13, 2006
Radiation Hardened Single 16/Differential
8 Channel CMOS Analog Multiplexers with
Active Overvoltage Protection
The HS-0546RH and HS-0547RH are radiation hardened
analog multiplexers with Active Overvoltage Protection and
guaranteed rON matching. Analog input levels may greatly
exceed either power supply without damaging the device or
disturbing the signal path of other channels. Active protection
circuitry assures that signal fidelity is maintained even under
fault conditions that would destroy other multiplexers. Analog
inputs can withstand constant 70V peak-to-peak levels with
±15V supplies and digital inputs will sustain continuous faults
up to 4V greater than either supply. In addition, signal sources
are protected from short circuiting should multiplexer supply
loss occur: each input presents 1kΩ of resistance under this
condition. These features make the HS-0546RH and
HS-0547RH ideal for use in systems where the analog inputs
originate from external equipment or separately powered
circuitry. Both devices are fabricated with 44V dielectrically
isolated CMOS technology. The HS-0546 is a 16 channel
device and the HS-0547 is an 8 channel differential version. If
input overvoltage protection is not needed, the HS-0506 and
HS-0507 multiplexers are recommended.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95693. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com
FN3544.4
Features
• Electrically Screened to SMD # 5962-95693
• QML Qualified per MIL-PRF-38535 Requirements
• Gamma Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 104RAD(Si)
• No Latch-Up
• No Channel Interaction During Overvoltage
• Guaranteed rON Matching
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . .44V
• Break-Before-Make Switch
• Analog Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs
Applications
• Data Acquisition Systems
• Control Systems
• Telemetry
Ordering Information
ORDERING
NUMBER
INTERNAL
MKT. NUMBER
5962D9569301V9A HS0-0546RH-Q
PART
MARKING
TEMP.
RANGE
(°C)
Q-5962D9569301V9A
25
5962D9569301VXC HS1B-0546RH-Q Q-5962D9569301VXC
5962D9569302V9A HS0-0547RH-Q
Q-5962D9569302V9A
-55 to
125
25
5962D9569302VXC HS1B-0547RH-Q Q-5962D9569302VXC -55 to
125
Pinouts
HS-0546RH GDIP1-T28 (CERDIP) OR CDIP2-T28 (SBDIP)
TOP VIEW
28 OUT
VSUPPLY 1
HS-0547RH GDIP1-T28 (CERDIP) OR CDIP2-T28 (SBDIP)
TOP VIEW
+VSUPPLY 1
NC 2
27 -VSUPPLY
NC 3
26 IN 8
NC 3
26 IN 8A
IN 16 4
25 IN 7
IN 8B 4
25 IN 7A
IN 15 5
24 IN 6
IN 7B 5
24 IN 6A
IN 14 6
23 IN 5
IN 6B 6
23 IN 5A
IN 13 7
22 IN 4
IN 5B 7
22 IN 4A
IN 12 8
21 IN 3
IN 4B 8
21 IN 3A
IN 11 9
20 IN 2
IN 3B 9
20 IN 2A
IN 10 10
19 IN 1
IN 2B 10
19 IN 1A
18 ENABLE
IN 1B 11
18 ENABLE
IN 9 11
OUT B 2
28 OUT A
27 -VSUPPLY
GND 12
17 ADDRESS A0
GND 12
17 ADDRESS A0
VREF 13
16 ADDRESS A1
VREF 13
16 ADDRESS A1
ADDRESS A3 14
15 ADDRESS A2
NC 14
15 ADDRESS A2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HS-0546RH, HS-0547RH
Functional Diagrams
HS-0546RH
HS-0547RH
IN1
OUT
IN1A
1K
OUT A
1K
IN8A
IN2
1K
1K
DECODER/
DRIVER
IN1B
1K
OUT B
1K
DECODER/
DRIVER
IN8B
IN16
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
5V
REF
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
LEVEL
SHIFT
† DIGITAL INPUT
† † † † †
5V
REF
LEVEL
SHIFT
† DIGITAL INPUT
† † †
†
PROTECTION
PROTECTION
VREF A0 A1 A2
VREF A0 A1 A2 A3 EN
HS-0546RH TRUTH TABLE
EN
HS-0547RH TRUTH TABLE
A3
A2
A1
A0
EN
“ON”
CHANNEL
A2
A1
A0
EN
“ON” CHANNEL
PAIR
X
X
X
X
L
NONE
X
X
X
L
NONE
L
L
L
L
H
1
L
L
L
H
1
L
L
L
H
H
2
L
L
H
H
2
L
L
H
L
H
3
L
L
H
H
H
4
L
H
L
H
3
L
H
L
L
H
5
L
H
H
H
4
L
H
L
H
H
6
H
L
L
H
5
L
H
H
L
H
7
H
L
H
H
6
L
H
H
H
H
8
H
H
L
H
7
H
L
L
L
H
9
H
H
H
H
8
H
L
L
H
H
10
H
L
H
L
H
11
H
L
H
H
H
12
H
H
L
L
H
13
H
H
L
H
H
14
H
H
H
L
H
15
H
H
H
H
H
16
2
FN3544.4
March 13, 2006
HS-0546RH, HS-0547RH
Switching Waveforms
VAH = 4.0 ADDRESS
DRIVE (VA)
VA
0V
±10V
IN 1
IN 2 THRU IN 15
IN 16
+10V
EN
OUTPUT A
GND
OUT
VAH
-8V
VA INPUT
2V/DIV.
CH1 ON
A0
±
50%
A3
A2
A1
10V
OUTPUT A
5V/DIV.
VOUT
10K
-10V
CH16 ON
tA
200ns/DIV
FIGURE 1. ACCESS TIME
VAH = 4.0
ADDRESS
DRIVE (VA)
0V
A3
A2
A1
VA
+5V
IN 1
VA INPUT
2V/DIV.
IN 2 THRU IN 15
A0
50%
50%
IN 16
OUTPUT
EN
GND
OUT
VOUT
OUTPUT
1V/DIV.
VAH
1K
tOPEN
100ns/DIV
FIGURE 2. BREAK-BEFORE-MAKE DELAY (tOPEN)
VAH = 4.0
50%
0V
A3
A2
A1
IN 1
A0
IN 2 THRU IN 16
+10V
CH1 ON
OUTPUT
90%
EN
90%
tON(EN)
VA
GND
OUT
1K
CH1 OFF
OUTPUT
4V/DIV.
tOFF
(EN)
100ns/DIV
FIGURE 3. ENABLE DELAY tON(EN), tOFF(EN)
3
FN3544.4
March 13, 2006
HS-0546RH, HS-0547RH
Schematic Diagrams
TTL REFERENCE CIRCUIT
V+
R10
R9
Q1
Q4
D3
LEVEL SHIFTER
V+
P
P
P
P
OVERVOLTAGE
PROTECTION
R3
V+
ADD
IN.
D2
R1
P
P
P
LEVEL
SHIFTED
ADDRESS
TO
DECODE
R2
N
P
P
P
N
R5
R7
R6
R8
LEVEL
SHIFTED
ADDRESS
TO
DECODE
R4
N
N
N
N
N
N
N
N
200Ω
D1
V-
V-
FIGURE 4. ADDRESS INPUT BUFFER AND LEVEL SHIFTER
FROM
DECODE
+V
P
P
P
P
P
OVERVOLTAGE
P
PROTECTION
N
V+
P
N
A0 OR A0
N
Q5
N
R11
N
D6
D7
D4
D5
IN
OUT
N
1K
A1 OR A1
N
N
Q6
A2 OR A2
N
V
ENABLE
P
VTO N-CHANNEL DEVICE OF THE SWITCH PAIR
TO P-CHANNEL DEVICE OF THE SWITCH PAIR
FIGURE 5. ADDRESS DECODER
4
FROM
DECODE
FIGURE 6. MULTIPLEX SWITCH
FN3544.4
March 13, 2006
HS-0546RH, HS-0547RH
Burn-In/Life Test Circuits
R2
V1
C1 D1
R1
F3
1
28
2
27
3
26
4
5
V2
V2
R2
1
28
2
27
3
26
25
4
25
24
5
24
6
23
6
23
7
22
7
22
8
21
8
21
9
20
9
20
10
19
10
19
11
18
F4
11
18
12
17
F0
12
17
13
16
F1
13
16
14
15
F2
14
15
D2 C2
C1 D1
R1
V1
DYNAMIC AND LIFE TEST
V3
D2 C2
STATIC
NOTES:
NOTES:
1. The Dynamic Test Circuit is utilized for all life testing.
8. V1 = +5V minimum, +6V maximum.
2. V1 = +15V minimum, +16V maximum.
9. V2 = +15V minimum, +16V maximum.
3. V2 = -15V maximum, -16V minimum.
10. V3 = -15V maximum, -16V minimum.
4. R1, R2 = 10kΩ, ±5%, 1/4 or 1/2W (per socket).
11. R1, R2 = 10kΩ, ±5%, 1/4 or 1/2W (per socket).
5. C1, C2 = 0.01µF minimum (per socket) or 0.1µF minimum
(per row).
12. C1, C2 = 0.01µF minimum (per socket) or 0.1µF minimum
(per row).
6. D1, D2 = 1N4002 or equivalent (per board).
13. D1, D2 = 1N4002 or equivalent (per board).
7. F0 = 100kHz, 10%; F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2
40% - 60% duty cycle; VIL = 0.8V maximum;
VIH = 4.0V minimum.
Irradiation Circuit
+15V
10kΩ
1
28
2
27
NC
3
26
+1V
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
-15V
10kΩ
+5V
5
FN3544.4
March 13, 2006
HS-0546RH, HS-0547RH
Die Characteristics
DIE DIMENSIONS:
83.9 mils x 159 mils x 19 mils
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
INTERFACE MATERIALS:
Glassivation:
Type: Nitride
Thickness: 7kÅ ±0.7kÅ
ADDITIONAL INFORMATION:
Top Metallization:
Type: Al
Thickness: 16kÅ ±2kÅ
Transistor Count:
HS-0546 - 485
HS-0547 - 485
Worst Case Current Density:
1.4 x 105 A/cm2
Substrate:
CMOS, DI
Metallization Mask Layout
HS-0546RH
EN
A0
A1 A2
HS-0547RH
A3
VREF
EN
GND
A0
A1 A2
NC VREF
GND
IN 1
IN 9
IN 1A
IN 1B
IN 2
IN 10
IN 2A
IN 2B
IN 3
IN 11
IN 3A
IN 3B
IN 4
IN 12
IN 4A
IN 4B
IN 5
IN 13
IN 5A
IN 5B
IN 6
IN 14
IN 6A
IN 6B
IN 7
IN 15
IN 7A
IN 7B
IN 8
IN 16
IN 8A
IN 8B
-V
OUT
+V
NC
-V
OUT A
+V
OUT B
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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6
FN3544.4
March 13, 2006
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