DATASHEET

Radiation Hardened Quad Differential Line Driver
HS-26C31RH, HS-26C31EH
Features
The Intersil HS-26C31RH, HS-26C31EH are quad differential
line drivers designed for digital data transmission over
balanced lines and meets the requirements of EIA standard
RS-422. Radiation hardened CMOS processing assures low
power consumption, high speed, and reliable operation in the
most severe radiation environments.
• Electrically screened to SMD #5962-96663
The HS-26C31RH, HS-26C31EH accept CMOS levels and converts
them to RS-422 compatible outputs. These circuits uses special
outputs that enable the drivers to power-down without loading
down the bus. Enable and disable pins allow several devices to be
connected to the same data source and addressed
independently.
• EIA RS-422 compatible outputs (except for IOS)
• QML qualified per MIL-PRF-38535 requirements
• 1.2 Micron radiation hardened CMOS
- Total dose up to . . . . . . . . . . . . . . . . . . . . . . . . 300kRAD(Si)
• Latchup free
• CMOS inputs
• High impedance outputs when disabled or powered down
• Low power dissipation . . . . . . . . . . . . 2.75mW standby (max)
• Single 5V supply
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
• Low output impedance . . . . . . . . . . . . . . . . . . . . . .10Ω or less
• Full -55°C to +125°C military temperature range
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96663. A “hot-link” is provided on our
homepage for downloading.
Applications
• Line transmitter for MIL-STD-1553 serial data bus
Ordering Information
ORDERING NUMBER
(Note 1)
INTERNAL
MKT. NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
5962F9666301QEC
HS1-26C31RH-8
Q 5962F96 6630QEC
-55 to +125
16 LD SBDIP
D16.3
5962F9666301QXC
HS9-26C31RH-8
Q 5962F96 66301QXC
-55 to +125
16 LD FLATPACK
K16.A
5962F9666301VEC
HS1-26C31RH-Q
Q 5962F96 66301VEC
-55 to +125
16 LD SBDIP
D16.3
5962F9666301VXC
HS9-26C31RH-Q
Q 5962F96 66301VXC
-55 to +125
16 LD FLATPACK
K16.A
HS1-26C31RH/PROTO
HS1-26C31RH/PROTO
HS1- 26C31RH/PROTO
-55 to +125
16 LD SBDIP
D16.3
HS0-26C31RH/SAMPLE
HS0-26C31RH/SAMPLE
-55 to +125
Die
HS9-26C31RH/PROTO
HS9-26C31RH/PROTO
-55 to +125
16 LD FLATPACK
5962F9666301V9A
HS0-26C31RH-Q
-55 to +125
Die
5962F9666303VEC
HS1-26C31EH-Q
Q 5962F96 66303VEC
-55 to +125
16 LD SBDIP
5962F9666303VXC
HS9-26C31EH-Q
Q 5962F96 66303VXC
-55 to +125
16 LD FLATPACK
5962F9666303V9A
HS0-26C31EH-Q
-55 to +125
Die
5962F9666301VYC
HS9G-26C31RH-Q (Note 2)
-55 to +125
16 LD FLATPACK
K16.A
HS9G-26C31RH/PROTO
HS9G-26C31RH/PROTO (Note 2) HS9G-26C31RH/PROTO
-55 to +125
16 LD FLATPACK
K16.A
HS9- 26C31RH/PROTO
Q 5962F96 66301VYC
K16.A
D16.3
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. The lid of these packages are connected to the ground pin of the device.
May 23, 2013
FN3401.7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
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HS-26C31RH, HS-26C31EH
Pin Configurations
HS9-26C31RH, HS9-26C31EH
(16 LD FLATPACK) CDFP4-F16
TOP VIEW
HS1-26C31RH, HS1-26C31EH
(16 LD SBDIP) CDIP2-T16
TOP VIEW
16 VDD
AIN
1
16
VDD
15 DIN
AO
2
15
DIN
AO 3
14 DO
AO
3
14
DO
ENABLE 4
13 DO
ENABLE
4
13
DO
BO
5
12
ENABLE
BO
6
11
CO
BIN
7
10
CO
GND
8
9
CIN
AIN 1
AO 2
BO 5
12 ENABLE
BO 6
11 CO
BIN 7
10 CO
GND 8
9 CIN
Logic Diagram
ENABLE
ENABLE
DIN
CIN
BIN
AIN
DO DO
CO CO
BO BO
AO AO
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
2
FN3401.7
May 23, 2013
HS-26C31RH, HS-26C31EH
Die Characteristics
Substrate:
AVLSI1RA
DIE DIMENSIONS:
Backside Finish:
96.5 mils x 195 mils x 21 mils
(2450 x 4950)
Silicon
INTERFACE MATERIALS:
ASSEMBLY RELATED INFORMATION:
Glassivation:
Substrate Potential (Powered Up):
Type: PSG (Phosphorus Silicon Glass)
Thickness: 10kÅ ±1kÅ
VDD
ADDITIONAL INFORMATION:
Metallization:
Worst Case Current Density:
M1: Mo/TiW
Thickness: 5800Å
M2: Al/Si/Cu (Top)
Thickness: 10kÅ ±1kÅ
<2.0x105A/cm2
Bond Pad Size:
110µmx100µm
Metallization Mask Layout
(15) DIN
(16) VDD
(1) AIN
(16) VDD
HS-26C31RH, HS-26C31EH
AO (2)
(14) DO
AO (3)
(13) DO
ENABLE (4)
(12) ENABLE
3
CIN (9)
(10) CO
GND (8)
BO (6)
GND (8)
(11) CO
BIN (7)
BO (5)
FN3401.7
May 23, 2013
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