95632

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Add paragraph 1.3 and Appendix A in accordance with NOR 5962-R031-97.
96-11-06
R. MONNIN
B
Add device class T criteria. Editorial changes throughout. Redrawn. -lgt
98-12-23
R. MONNIN
C
Add vendor CAGE F8859. Updated footnote 2/ in table I to accommodate
RHA designator “D”. Update boilerplate to reflect current requirements. -rrp
02-11-27
R. MONNIN
D
Add junction temperature to 1.3. Made change to propagation delay time tests,
tPZH/tPZL and tPLZ/tPHZ in table I. - rrp
07-03-02
J. RODENBECK
E
Make a correction to Figure 2 by replacing the second from the left ENABLE
with ENABLE . - ro
08-03-20
R. HEBER
F
Add device type 02. Update radiation features under paragraph 1.5.
Add paragraph 2.2 ASTM information and Table IB. Delete table III, Dose rate
induced latchup testing and Dose rate upset testing paragraphs. - ro
12-04-17
C. SAFFLE
G
Add case outline Y. Add note under figure 1. Delete device class M
references. - ro
13-05-22
C. SAFFLE
H
Make correction to footnote 5/ as specified under Table I by deleting 500 Ω and
replace with 50 Ω. - ro
14-04-01
C. SAFFLE
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PMIC N/A
PREPARED BY
KENNETH S. RICE
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
SANDRA ROONEY
APPROVED BY
MICHAEL FRYE
DRAWING APPROVAL DATE
95-07-13
REVISION LEVEL
H
MICROCIRCUIT, LINEAR, RADIATION
HARDENED, CMOS, QUAD DIFFERENTIAL, LINE
DRIVER, MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-95632
1 OF 24
5962-E244-14
1. SCOPE
1.1 Scope. This drawing documents three product assurance class levels consisting of high reliability (device class Q), space
application (device class V) and for appropriate satellite and similar applications (device class T). A choice of case outlines and
lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation
Hardness Assurance (RHA) levels is reflected in the PIN. For device class T, the user is encouraged to review the
manufacturer’s Quality Management (QM) plan as part of their evaluation of these parts and their acceptability in the intended
application.
1.2 PIN. The PIN is as shown in the following example:
5962
F
Federal
stock class
designator
\
95632
RHA
designator
(see 1.2.1)
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q, T and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
Generic number
26CT31RH
26CT31EH
Circuit function
Radiation hardened quad differential line driver
Radiation hardened quad differential line driver
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
Q, V
Certification and qualification to MIL-PRF-38535
T
Certification and qualification to MIL-PRF-38535 with performance as specified
in the device manufacturers approved quality management plan.
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
E
X
Y
Descriptive designator
Terminals
CDIP2-T16
CDFP4-F16
CDFP4-F16
16
16
16
Package style
Dual-in-line
Flat pack
Flat pack with grounded lid
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q, T and V.
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1.3 Absolute maximum ratings. 1/
Supply voltage ...........................................................................................................
Inputs, E, E voltage ..................................................................................................
Output voltage (power on or off (0.0 V)) ....................................................................
DC diode input current (any input) .............................................................................
DC drain current (any output) ....................................................................................
DC VDD or ground current ..........................................................................................
Power dissipation at TA = 125°C (PD) .......................................................................
-0.5 V to +7.0 V
-0.5 V to VDD+0.5 V
-0.5 V to +7.0 V
±20 mA
350 mA
400 mA
0.44 W 2/
For TA = -55°C to 125°C:
Case outline E ...................................................................................................
Case outlines X and Y ......................................................................................
Storage temperature range ........................................................................................
Lead temperature (soldering, 10 seconds) ................................................................
Junction temperature (TJ) ..........................................................................................
0.667 W
0.526 W
-65°C to +150°C
300°C
+175°C
Thermal resistance, junction-to-case (θJC) ................................................................ See MIL-STD-1835
Thermal resistance, junction-to-ambient (θJA):
Case outline E ........................................................................................................ 75°C/W
Case outlines X and Y ............................................................................................ 95°C/W
1.4 Recommended operating conditions.
Operating temperature range (TA) ............................................................................. -55°C to +125°C
Supply voltage range (VDD) ...................................................................................... +4.5 V to +5.5 V
Low input voltage (VIL) .............................................................................................. 0 V to 0.8 V, maximum
High input voltage (VIH) ............................................................................................. VDD to VDD/2 V, minimum
Input rise and fall time ............................................................................................... 500 ns maximum
Dynamic current (IDYN) at +25 °C ............................................................................. 3 mA
Power dissipation capacitance (CPD) at +25°C ......................................................... 170 pF
_______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Maximum device power dissipation is defined as VDD x ICC and must withstand the added PD due to output current
test IO at TA = +125°C.
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1.5 Radiation features.
Maximum total dose available (dose rate = 50 – 300 rads(Si)/s):
Device type 01 classes Q or V ...............................................................................
Device type 01 class T ..........................................................................................
Device type 02 .......................................................................................................
Maximum total dose available (dose rate < 0.01 rad(Si)/s):
Device type 02 ........................................................................................................
Single event phenomena (SEP):
No single event latch up (SEL) occurs at effective (LET) (see 4.4.3.) ...................
300 krads(Si) 3/
100 krads(Si) 3/
300 krads(Si) 4/
50 krad(Si) 4/
≤ 100 MeV/mg/cm
2
5/
The manufacturer supplying RHA device types 01 and 02 on this drawing has performed characterization testing to demonstrate
that the parts do not exhibit enhanced low dose rate sensitivity (ELDRS) in accordance with MIL-STD-883, method 1019,
paragraph 3.13.1.1. Therefore these parts may be considered ELDRS free at a level of 100 krads(Si). The manufacturer will
perform only high dose rate lot acceptance testing on a wafer by wafer basis in accordance with MIL-STD-883, method 1019,
condition A for device type 01. The manufacturer will perform high dose rate and low dose rate lot acceptance testing on a
wafer by wafer basis in accordance with MIL-STD-883, method 1019, conditions A and D for device type 02.
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
____
3/ The manufacturer supplying device type 01 has performed characterization testing in accordance with MIL-STD-883
method 1019 paragraph 3.13.1.1 and the parts exhibited no enhanced low dose rate sensitivity (ELDRS) at a level of
100 krads(Si). The radiation end point limits for the noted parameters are guaranteed only for the conditions as specified
in MIL-STD-883, method 1019, condition A to a maximum total dose of 300 krads(Si) for device classes V, Q, or M and
100 krads(Si) for device class T.
4/
The manufacturer supplying device type 02 has performed characterization testing in accordance with MIL-STD-883
method 1019 paragraph 3.13.1.1 and the parts exhibited no enhanced low dose rate sensitivity (ELDRS) at a level of
100 krads(Si). The radiation end point limits for the noted parameters are guaranteed only for the conditions as specified
in MIL-STD-883, method 1019, condition A to a maximum total dose of 300 krads(Si), and condition D to a maximum total
dose of 50 krads(Si).
5/
Guaranteed by process or design, not tested.
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2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract.
ASTM INTERNATIONAL (ASTM)
ASTM F1192 – Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of Semiconductor Devices.
(Copies of this document is available online at http://www.astm.org/ or from ASTM International, P.O. Box C700,
100 Bar Harbor Drive, West Conshohocken, PA 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q, T and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q, T and V.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q, T and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q, T and V shall be a "QML" or "Q" as required
in MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q, T and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q, T and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q, T and V in MIL-PRF-38535
shall be provided with each lot of microcircuits delivered to this drawing.
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TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/ 2/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
High level output voltage
VOH
Low level output voltage
VOL
Differential output voltage
VT, VT
VDD = 4.5 V and 5.5 V,
IO = -20 mA
3/
Max
1, 2, 3
01, 02
2.5
V
1, 2, 3
01, 02
1, 2, 3
01, 02
1, 2, 3
01, 02
0.4
V
1, 2, 3
01, 02
3.0
V
1, 2, 3
01, 02
0.4
V
4/
VDD = 4.5 V and 5.5 V,
IO = 20 mA
Unit
0.5
V
3/ 4/
VDD = VIH = 4.5 V,
2.0
V
VIL = 0 V, RL = R1 + R2 5/
VT –
VDD = VIH = 4.5 V,
 VT 
VIL = 0 V, RL = R1 + R2 5/
VOS –
VDD = VIH = 4.5 V,
VOS 
VIL = 0 V, RL = R1 + R2 5/
VOS –
VDD = VIH = 4.5 V,
VOS 
VIL = 0 V, RL = R1 + R2 5/
High level input voltage
VIH
VDD = 4.5 V, 5.5 V 6/
1, 2, 3
01, 02
Low level input voltage
VIL
VDD = 4.5 V, 5.5 V 6/
1, 2, 3
01, 02
0.8
V
1, 2, 3
01, 02
500
µA
1, 2, 3
01, 02
±5.0
µA
1, 2, 3
01, 02
2.0
mA
1, 2, 3
01, 02
±1.0
µA
1, 2, 3
01, 02
100
µA
1, 2, 3
01, 02
-1.5
V
Difference in differential
output
Common Mode Output
voltage
Difference in Common
Mode Output
V
VDD/2.0
VDD = 5.5 V,
Standby supply current
IDDSB
output = open,
VIN = VDD or GND
VDD = 5.5 V,
Three-state output leakage
current
IOZ
Delta supply current
∆ICC
Input leakage current
IIN
force voltages = 0 V or
VDD
7/
VDD = 5.5 V,
VIN = 2.4 V, 0.5 V
VDD = 5.5 V,
VIN = VDD or GND
VDD = 0.0 V,
Output leakage current
power off
IOFF
VOUT = 6.0 V, 250 mV,
-100
Inputs = GND
Input clamp voltage
VIC
at -1.0 mA
at +1.0 mA
Functional test
+1.5
See 4.4.1b
7, 8A, 8B
01, 02
See footnotes at end of table.
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TABLE IA. Electrical performance characteristics - Continued.
Test
Propagation delay time
Rise and Fall time
Output skew
Symbol
TPLH,
TPHL
Conditions 1/ 2/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
VDD = 4.5 V
Group A
subgroups
9, 10 ,11
5/
Device
type
01, 02
Limits
Unit
Min
Max
2
22
ns
TPZH,
9, 11
5
28
TPZL
10
5
33
TPLZ,
9, 11
2
22
TPHZ
10
2
27
1
10
ns
3
ns
TTHL,
VDD = 4.5 V
5/
TSKEW
VDD = 4.5 V
5/
8/
RL = 100 Ω, CL = 40 pF
TTLH
9, 10, 11
01, 02
9, 10, 11
01, 02
Note : The below parameters are not part of the post irradiation electrical performance characteristics. 9/
Input capacitance
CIN
VDD = open, f = 1 MHz
4
01, 02
12
pF
Output capacitance
COUT
VDD = open, f = 1 MHz
4
01, 02
12
pF
1, 2, 3
01, 02
-150
mA
1, 2, 3
01, 02
VDD = 5.5 V,
Operating short circuit
IOS
VIN = VDD or GND,
VOUT = 0 V
-30
10/
VDD = 4.5 V,
On-state resistance
RON
VOUT = 1.5 V,
10
Ω
VIN = VDD or GND
1/
RHA device type 01 supplied to this drawing meet all levels M, D, P, L, R and F of irradiation for device classes Q or V and
levels M, D, P, L, and R for device class T. However, device type 01 for device classes Q and V are only tested at the
“F” level, and device class T is only tested at the “R” level (see 1.5 herein) in accordance with MIL-STD-883 method
1019 condition A.
RHA device type 02 supplied to this drawing will meet all levels M, D, P, L, R, and F of irradiation for condition A and
levels M, D, P, and L for condition D. However, device type 02 is only tested at the “F” level in accordance with
MIL-STD-883, method 1019, condition A, and tested at the ”L” level in accordance with MIL-STD-883, method 1019,
condition D (see 1.5 herein).
Pre and post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation
electricals measurements for any RHA level, TA = +25°C.
2/
3/
4/
All voltages referenced to device ground.
Force/measure functions may be interchanged.
VIL = 0.8 V and VIN = VDD/2.
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TABLE IA. Electrical performance characteristics - Continued.
5/
6/
These conditions are detailed in EIA specification RS-422, (R1 = R2 = 50 Ω). See figure 3 as applicable.
This parameter tested as inputs for the VOL, VOH, and IOZ, and function tests.
7/
8/
9/
The inputs are conditioned to have the output in the opposite state of the forcing IOZ condition.
Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.
Tested initially and after any design or process changes that affect these parameters, and therefore shall meet the values
listed in table IA.
10/ Only one output at a time shall be shorted.
TABLE IB. SEP test limits. 1/ 2/
Device
types
Bias for
Single event latch-up (SEL) test; maximum operating voltage
VDD = 5.5 V
2
No SEL at effective LET = [MeV/mg/cm ]
LET ≤ 100
01, 02
1/
2/
3/
For SEP test conditions, see 4.4.4.3 herein.
Technology characterization and model verification supplemented by in-line data
may be used in lieu of end-of-line testing. Test plan must be approved by TRB
and qualifying activity.
Tested for latch-up at worst case operating temperature, TA = +125°C ± 10°C.
4/
5/
Tested to LET ≤ 100 MeV/mg/cm and no latch-up occurs.
Guaranteed by process or design, not tested.
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Device types
01 and 02
Case outlines
E, X and Y
SEE NOTE
Terminal number
Terminal symbol
1
AIN
2
AO
3
AO
4
ENABLE
5
BO
6
BO
7
BIN
8
GND
9
CIN
10
CO
11
CO
12
ENABLE
13
DO
14
DO
15
DIN
16
VDD
Note: For case outline Y only, the lid is grounded.
FIGURE 1. Terminal connections.
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Device Power
INPUTS
OUTPUT
ON/OFF
ENABLE
ENABLE
IN
OUT
OUT
ON
0
1
X
HI-Z
HI-Z
ON
1
X
0
0
1
ON
X
0
0
0
1
ON
1
X
1
1
0
ON
X
0
1
1
0
OFF ( 0 V )
X
X
X
HI-Z
HI-Z
FIGURE 2. Truth table.
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Propagation delay timing diagram
Note : Voltage levels
VDD = 4.50 V
VIH = 3.00 V
VS = 1.30 V
VIL = 0.0 V
GND = 0.0 V
VSO = 50%
Propagation delay load circuit
C1 = C2 = C3 = 40 pF
R1 = R2 = 50 Ω
FIGURE 3. Timing and load circuit diagrams.
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Three-state low timing diagram
Note : Voltage levels
VDD = 4.50 V
VIH = 3.00 V
VS = 1.30 V
VW = VOL + 0.3 V
VT = 0.60 V
Three-state low load circuit
C1 = C2 = C3 = 40 pF
R1 = R2 = 50 Ω
R3 = 500 Ω
FIGURE 3. Timing and load circuit diagrams – Continued.
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Three-state high timing diagram
Note : Voltage levels
VDD = 4.50 V
VIH = 3.00 V
VS
= 1.30 V
VT = VOH -0.3 V
VW = 2.00 V
Three-state high load circuit
C1 = C2 = C3 = 40 pF
R1 = R2 = 50 Ω
R3 = 500 Ω
FIGURE 3. Timing and load circuit diagrams – Continued.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q, and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan, including screening (4.2),
qualification (4.3), and conformance inspection (4.4). The modification in the QM plan shall not affect the form, fit, or function as
described herein. For device class T, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 and the
device manufacturer’s QM plan including screening, qualification, and conformance inspection. The performance envelope and
reliability information shall be as specified in the manufacturer’s QM plan.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class T, screening shall be in
accordance with the device manufacturer’s Quality Management (QM) plan, and shall be conducted on all devices prior to
qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q, T and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
For device classes Q, T and V interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, Appendix B.
4.3 Qualification inspection for device classes Q, T and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Qualification inspection for device class T shall be in accordance with the device
manufacturer’s Quality Management (QM) plan. Inspections to be performed shall be those specified in MIL-PRF-38535 and
herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein. Technology conformance inspection
for class T shall be in accordance with the device manufacturer’s Quality Management (QM) plan.
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
d.
Subgroup 4 (CIN and COUT measurement) shall be measured only for the initial test and after process or design
changes which may affect input capacitances.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device classes Q, T and V. The steady-state life test duration, test condition and test
temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with
MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in
accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test
circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1005 of MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
STANDARD
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TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
1,7,9
Device
class V
1,7,9
Device
class T
As specified
in QM plan
1,2,3,7,8A, 1/
8B,9,10,11
1,2,3,7, 1/ 2/
8A,8B 9,10,11
As specified
in QM plan
Group A test
requirements (see 4.4)
1,2,3,4,7, 3/
8A,8B,9,10,11
1,2,3,4,7, 3/
8A,8B,9,10,11
As specified
in QM plan
Group C end-point electrical
parameters (see 4.4)
1,2,3,7,8A,8B,9,
10,11
1,2,3,7, 2/
8A,8B,9,10,11
As specified
in QM plan
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1,7,9
1,7,9
As specified
in QM plan
1,7,9
1,7,9
As specified
in QM plan
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
1/ PDA applies to subgroups 1, 7, and 9. For class V to subgroups 1, 7, 9, and ∆.
2/ Delta limits (see table IIB) shall be required and the delta values shall be computed
with reference to the zero hour electrical parameters (see table IA).
3/ Subgroup 4, if not tested, shall be guaranteed to the limits specified in table IA.
TABLE IIB. Burn-in and operating life test delta parameters. (TA = +25°C)
Test 1/
Symbol
Device types
Delta limits
High level output voltage
VOH
01, 02
±150 mV
Low level output voltage
VOL
01, 02
±60 mV
Standby supply current
IDDSB
01, 02
±100 µA
Three state output leakage current
IOZ
01, 02
±1.0 µA
Input leakage current
IIN
01, 02
±150 nA
1/ The above parameters shall be recorded before and after the required burn-in
and life test to determine the delta.
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4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End-point electrical
parameters shall be as specified in table IIA herein.
4.4.4.1 Group E inspection for device class T. For device class T, the RHA requirements shall be in accordance with the
class T radiation requirements of MIL-PRF-38535. End-point electrical parameters shall be as specified in table IIA herein.
4.4.4.2 Total dose irradiation testing. Total dose irradiation testing high dose rate shall be performed in accordance with
MIL-STD-883 method 1019, condition A and as specified herein for device types 01 and 02. Total dose irradiation testing at
low dose rate shall be performed in accordance with MIL-STD-883 method 1019, condition D and as specified herein for device
type 02.
4.4.4.2.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5 krads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
4.4.4.3 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The recommended test conditions for SEP are as follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b.
The fluence shall be ≥ 100 errors or ≥ 10 ions/cm .
c.
The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d.
The particle range shall be ≥ 20 microns in silicon.
e.
The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f.
Bias conditions shall be defined by the manufacturer for latchup measurements.
g.
Test four devices with zero failures.
7
2
5
2
2
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q, T and V.
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6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q, T and V. Sources of supply for device classes Q, T and V are listed in
MIL-HDBK-103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate of
compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing.
6.7 Additional information. When applicable a copy of the following additional data shall be maintained and available from the
device manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Occurrence of latchup (SEL).
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95632
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
F
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
95632
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels.
A dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
Generic number
26CT31RH
26CT31EH
Circuit function
Radiation hardened quad differential line driver
Radiation hardened quad differential line driver
A.1.2.3 Device class designator.
Device class
Q or V
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Certification and qualification to the die requirements of MIL-PRF-38535
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95632
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding
pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product
and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01, 02
A-1
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01, 02
A-1
A.1.2.4.3 Interface materials.
Die type
Figure number
01, 02
A-1
A.1.2.4.4 Assembly related information.
Die type
Figure number
01, 02
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
A.1.5 Radiation features. See paragraph 1.5 herein for details.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95632
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein and the manufacturer’s QM plan for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1.
A.3.2.5 Truth table. The truth table shall be as defined in figure 2.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in 3.2.4.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95632
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this appendix shall
affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the
requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4,
4.4.4.1, 4.4.4.2, 4.4.4.2.1, and 4.4.4.3 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
STANDARD
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95632
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DLA Land and Maritime -VA, Columbus, Ohio,
43218-3990 or telephone (614)-692-0540.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DLA Land and
Maritime -VA and have agreed to this drawing.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95632
NOTE: Pad numbers reflect terminal numbers when placed in case outlines E, X, and Y (see figure 1).
FIGURE A-1. Die bonding pad locations and electrical functions.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95632
Die bonding pad locations and electrical functions
Die physical dimensions.
Die size: 2450 x 4950 microns
Die thickness: 21 ± 1 mils
Interface materials.
Top metallization: Si Al Cu 10.0 kÅ ± 2 kÅ
Backside metallization: None: chemical etch
Glassivation.
Type: PSG
Thickness: 8 kÅ ± 1 kÅ
Substrate: Single crystal silicon
Assembly related information.
Substrate potential: Substrate internally tied to VDD
Special assembly instructions: None
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
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STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 14-04-01
Approved sources of supply for SMD 5962-95632 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962D9563201QXA
3/
26T31K02Q
5962D9563201VXA
3/
26T31K02V
5962D9563201QXC
3/
26T31K01Q
5962D9563201VXC
3/
26T31K01V
5962D9563201QEA
3/
26T31D09Q
5962D9563201VEA
3/
26T31D09V
5962D9563201QEC
3/
26T31D08Q
5962D9563201VEC
3/
26T31D08V
5962F9563201QEC
34371
HS1-26CT31RH-8
5962F9563201QXC
34371
HS9-26CT31RH-8
5962F9563201VEC
34371
HS1-26CT31RH-Q
5962F9563201VXC
34371
HS9-26CT31RH-Q
5962F9563201VYC
34371
HS9G-26CT31RH-Q
5962R9563201TEC
34371
HS1-26CT31RH-T
5962R9563201TXC
34371
HS9-26CT31RH-T
5962F9563201V9A
34371
HS0-26CT31RH-Q
1 of 2
STANDARD MICROCIRCUIT DRAWING BULLETIN – CONTINUED.
DATE: 14-04-01
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962F9563202VEC
34371
HS1-26CT31EH-Q
5962F9563202VXC
34371
HS9-26CT31EH-Q
5962F9563202V9A
34371
HS0-26CT31EH-Q
Standard
microcircuit drawing
PIN 1/
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
Vendor name
and address
34371
Intersil Corporation
1001 Murphy Ranch Road
Milpitas, CA 95035-6803
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
2 of 2