DATASHEET

Radiation Hardened Quad Differential Line Receivers
HS-26CT32RH, HS-26CT32EH
The Intersil HS-26CT32RH, HS-26CT32EH are differential line
receivers designed for digital data transmission over balanced
lines and meets the requirements of EIA standard RS-422.
Radiation hardened CMOS processing assures low power
consumption, high speed, and reliable operation in the most
severe radiation environments.
The HS-26CT32RH, HS-26CT32EH have an input sensitivity
typically of 200mV over the common mode input voltage
range of ±7V. The receivers are also equipped with input fail
safe circuitry, which causes the outputs to go to a logic “1”
when the inputs are open. Enable and Disable functions are
common to all four receivers.
Features
• Electrically screened to SMD # 5962-95631
• QML qualified per MIL-PRF-38535 requirements
• 1.2 Micron radiation hardened CMOS
- Total dose . . . . . . . . . . . . . . . . . . . . . . . . Up to 300kRAD(Si)
• Latch-up free
• EIA RS-422 compatible outputs
• Operation with TTL based on VIH = VDD/2
• Input fail safe circuitry
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the “Ordering Information” must be used
when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95631. A “hot-link” is also provided on
our homepage for downloading.
• High impedance inputs when disabled or powered down
• Low power dissipation standby (Max) . . . . . . . . . . . . .138mW
• Single 5V supply
• Full Military temperature range . . . . . . . . . -55°C to +125°C
Applications
• Line receiver for MIL-STD-1553 serial data bus
• Line receiver for RS422
Logic Diagram
ENABLE
ENABLE DIN DIN
+
-
DOUT
CIN CIN
BIN BIN
AIN AIN
+
+
+
-
COUT
-
BOUT
-
AOUT
Ordering Information
ORDERING NUMBER
(Note 1)
INTERNAL
MKT. NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
5962F9563101QEC
HS1-26CT32RH-8
Q 5962F95 63101QEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9563101QXC
HS9-26CT32RH-8
Q 5962F95 63101QXC
-55 to +125
16 Ld Flatpack
K16.A
5962F9563101V9A
HS0-26CT32RH-Q
-55 to +125
Die
HS0-26CT32RH/SAMPLE
HS0-26CT32RH/SAMPLE
-55 to +125
Die
5962F9563101VEC
HS1-26CT32RH-Q
Q 5962F95 63101VEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9563101VXC
HS9-26CT32RH-Q
Q 5962F95 63101VXC
-55 to +125
16 Ld Flatpack
K16.A
5962F9563102VXC
HS9-26CT32EH-Q
Q 5962F95 63102VXC
-55 to +125
16 Ld Flatpack
K16.A
HS1-26CT32RH/PROTO
HS1-26CT32RH/PROTO
HS1- 26CT32RH /PROTO
-55 to +125
16 Ld SBDIP
D16.3
HS9-26CT32RH/PROTO
HS9-26CT32RH/PROTO
HS9- 26CT32RH /PROTO
-55 to +125
16 Ld Flatpack
K16.A
May 23, 2013
FN2930.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2000, 2008, 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-26CT32RH, HS-26CT32EH
Ordering Information (Continued)
ORDERING NUMBER
(Note 1)
INTERNAL
MKT. NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
5962F9563102VEC
HS1-26CT32EH-Q
Q 5962F95 63102VEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9563102VXC
HS9-26CT32EH-Q
Q 5962F95 63102VXC
-55 to +125
16 Ld Flatpack
K16.A
5962F9563102V9A
HS0-26CT32EH-Q
-55 to +125
Die
5962F9563101VYC
HS9G-26CT32RH-Q (Note2)
-55 to +125
16 Ld Flatpack
K16.A
HS9G-26CT32RH/PROTO
HS9G-26CT32RH/PROTO (Note 2) HS9G-26CT32RH/PROTO
-55 to +125
16 Ld Flatpack
K16.A
Q 5962F95 63101VYC
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. The lid of these packages are connected to the ground pin of the device.
Pin Configurations
HS9-26CT32RH, HS9-26CT32EH
(16 LD FLATPACK, CDFP4-F16)
TOP VIEW
HS1-26CT32RH
(16 LD SBDIP, CDIP2-T16)
TOP VIEW
16 VDD
AIN
1
16
VDD
AIN 2
15 BIN
AIN
2
15
BIN
AOUT 3
14 BIN
AIN 1
13 BOUT
ENABLE 4
COUT 5
12 ENABLE
CIN 6
11 DOUT
CIN 7
10 DIN
GND 8
9 DIN
AOUT
3
14
BIN
ENABLE
4
13
BOUT
COUT
5
12
ENABLE
CIN
6
11
DOUT
CIN
7
10
DIN
GND
8
9
DIN
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
2
FN2930.6
May 23, 2013
HS-26CT32RH, HS-26CT32EH
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
78 mils x 123 mils
(1970µm x 3120µm)
Silicon
ASSEMBLY RELATED INFORMATION:
INTERFACE MATERIALS:
Substrate Potential:
Glassivation:
VDD (When Powered Up)
Type: PSG (Phosphorus Silicon Glass)
Thickness: 10kÅ ±1kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
<2.0 x 105A/cm2
M1: Mo/Tiw
Thickness: 5800Å
M2: Al/Si/Cu
Thickness: 10kÅ ±1kÅ
Transistor Count:
240
Bond Pad Size:
Substrate:
110µm x 100µm
AVLSI1RA
Metallization Mask Layout
HS-26CT32RH, HS-26CT32EH
AIN
(1)
VDD
(16)
BIN
(15)
(14) BIN
AIN (2)
(13) BOUT
AOUT (3)
ENAB (4)
(12) ENAB
COUT (5)
(11) DOUT
(10) DIN
CIN (6)
(7)
CIN
3
(8)
GND
(9)
DIN
FN2930.6
May 23, 2013
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