PTHxx050Y —Series 6-A Non-Isolated DDR/QDR Memory Bus Termination Modules SLTS221 – MARCH 2004 Features • VTT Bus Termination Output (Output Tracks the System VREF) • 6 A Output Current (8 A Peak) • 3.3-V, 5-V or 12-V Input Voltage • DDR & QDR Compatible • On/Off Inhibit (for VTT Standby) • Under-Voltage Lockout • Operating Temp: –40 to +85 °C NOMINAL SIZE = • Efficiencies up to 88 % • 50 W/in³ Power Density • Output Over-Current Protection (Non-Latching, Auto-Reset) • Safety Agency Approvals (Pending): UL/cUL60950, EN60950, VDE • Point-of-Load Alliance (POLA) Compatible 0.87 in x 0.5 in (22,1 mm x 12,57 mm) Pin Configuration Description The PTHxx050Y are a series of readyto-use switching regulator modules from Texas Instruments designed specifically for bus termination in DDR and QDR memory applications. Operating from either a 3.3-V, 5-V or 12-V input, the modules generate a VTT output that will source or sink up to 6 A of current (8 A transient) to accurately track their VREF input. VTT is the required bus termination supply voltage, and VREF is the reference voltage for the memory and chipset bus receiver comparators. VREF is usually set to half the VDDQ power supply voltage. Both the PTHxx050Y series employs an actively switched synchronous rectifier output to provide state-of-the-art stepdown switching conversion. The products are small in size (0.87 in × 0.5 in), and are an ideal choice where space, performance, and high efficiency are desired, along with the convenience of a ready-to-use module. Operating features include an on/off inhibit and output over-current protection (source mode only). The on/off inhibit feature allows the VTT bus to be turned off to save power in a standby mode of operation. Package options include both throughhole and surface mount configurations. Pin 1 2 3 4 5 6 Function GND VREF VIN Inhibit * No Connect VTT * Denotes negative logic: Open = VTT Output On Ground = VTT Output Off Standard Application VIN VDDQ VREF 1k 1% 1 2 3 1k 1% 4 Standby PTHxx050Y (Top View) Con hf-Ceramic 5 Co1 Low-ESR (Required) Co2 Ceramic (Optional) Q1 BSS138 (Optional) GND Cin Co1 Co2 Co n = = = = Required electrolytic capacitor; 220 µF (3.3-/5-V input), 560 µF (12-V input). Required low-ESR electrolyitic capacitor; 470 µF (3.3-/5-V input), 940 µF (12-V input). Ceramic capacitance for optimum response to a 3-A (±1.5-A) load transient.; 200 µF (3.3-/5-V input), 400 µF (12-V input). Distributed hf-ceramic decoupling capacitors for V TT bus; as recommended for DDR memory appications. For technical support and further information, visit http://power.ti.com VTT Termination Island CIN (Required) VTT 6 SSTL-2 Data/ Address Bus PTHxx050Y —Series 6-A Non-Isolated DDR/QDR Memory Bus Termination Modules SLTS221 – MARCH 2004 Ordering Information Input Voltage (PTHHH050Yxx) Package Options (PTHxx050YHH) (1) Code 03 05 12 Code AH AS Input Voltage 3.3 V 5V 12 V Description Horiz. T/H SMD, Standard (3) Pkg Ref. (EUU) (EUV) (2) Notes: (1) Add “T” to end of part number for tape and reel on SMD packages only. (2) Reference the applicable package reference drawing for the dimensions and PC board layout (3) “Standard” option specifies 63/37, Sn/Pb pin solder material. Pin Descriptions VIN: The positive input voltage power node to the module, which is referenced to common GND. GND: This is the common ground connection for the VIN and VTT power connections. It is also the 0-VDC reference for the control inputs. VREF: The module senses the voltage at this input to regulate the output voltage, VTT. The voltage at VREF is also the reference voltage for the system bus receiver comparators. It is normally set to precisely half the bus driver supply voltage (VDDQ ÷ 2), using a resistor divider (see standard application). The Thevenin impedance of the network driving the VREF pin should not exceed 500 Ω. Environmental & Absolute Maximum Ratings Characteristics Symbols Control Input Voltage Operating Temperature Range Solder Reflow Temperature Storage Temperature Mechanical Shock VREF Ta Treflow Ts Mechanical Vibration Weight Flammability — — VTT: This is the regulated power output from the module with respect to the GND node, and the tracking termination supply for the application data and address buses. It is precisely regulated to the voltage applied to the module’s VREF input, and is active active about 20 ms after a valid input source is applied to the module. Once active it will track the voltage applied at VREF. Inhibit: The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a lowlevel ground signal to this input turns off the output voltage, VTT. When the Inhibit is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module will produce an output whenever a valid input source is applied. (Voltages are with respect to GND) Conditions Over Vin Range Surface temperature of module body or pins — Per Mil-STD-883D, Method 2002.3 1 msec, ½ Sine, mounted Mil-STD-883D, Method 2007.2 20-2000 Hz Min Typ –0.3 –40 (i) — — Max Vin + 0.3 85 235 (ii) 125 Units V °C °C °C –40 — — 500 — G’s — 20 — G’s — 2.9 — grams Meets UL 94V-O Notes: (i) For operation below 0 °C the external capacitors m ust bave stable characteristics. use either a low ESR tantalum, Os-Con, or ceramic capacitor. (ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum. For technical support and further information, visit http://power.ti.com PTHxx050Y —Series 6-A Non-Isolated DDR/QDR Memory Bus Termination Modules Specifications SLTS221 – MARCH 2004 (Unless otherwise stated, T a =25 °C; nominal Vin; V REF =1.25 V; C in, Co1, & Co 2 =typical values; and I o =Iomax) PTHxx050Y Characteristics Symbols Conditions Output Current Io Over ∆VREF range, Input Voltage Range Vin Over Io range Tracking Range for VREF Tracking Tolerance to VREF Efficiency ∆VREF VTT –VREF η Over line, load and temperature Io =4 A Vo Ripple (pk-pk) Over-Current Threshold Load Transient Response Vr Io trip Under-Voltage Lockout ttr ∆Vtr UVLO Inhibit Control (pin4) Input High Voltage Input Low Voltage Input Low Current Input Standby Current Switching Frequency VIH VIL IIL inhibit Iin inh ƒs External Input Capacitance Cin External Output Capacitance Co1, Co2 Reliability MTBF Continuous Repetitive pulse PTH03050Y PTH05050Y PTH12050Y PTH03050Y PTH05050Y PTH12050Y 20 MHz bandwidth Reset, followed by auto-recovery 15 A/µs load step, from –1.5 A to +1.5 A (See note 5) Recovery Time Vo over/undershoot PTH03050Y Vin increasing PTH05050Y PTH12050Y PTH03050Y Vin decreasing PTH05050Y PTH12050Y Referenced to GND Pin to GND Inhibit (pin 4) to GND Over Vin & Io ranges PTH03050Y/PTH05050Y PTH12050Y PTH03050Y/PTH05050Y PTH12050Y Capacitance value: non-ceramic PTH03050Y/PTH05050Y PTH12050Y ceramic PTH03050Y/PTH05050Y PTH12050Y Equiv. series resistance (non-ceramic) Per Bellcore TR-332 50 % stress, Ta =40 °C, ground benign Min Typ Max Units 0 — 2.95 4.5 10.8 0.55 –10 — — — — — — — — — — — — 88 87 84 20 12 ±6 (1) ±8 (2) 3.65 5.5 13.2 1.8 +10 — — — — — A A — — — — — 2.2 3.4 8.8 80 25 2.45 4.3 9.5 2.40 3.7 9 — 40 2.8 4.45 10.4 — — — Vin –0.5 –0.2 — — 550 200 220 (4) 560 (4) — — –130 10 600 250 — — Open 0.6 — — 650 300 — — (3) 0 — 0 0 4 6 470 940 200 400 — — 3,300 3,300 300 600 — — (6) (6) (7) (5) (5) (5) (5) V V mV % mVpp A µSec mV V V V µA mA kHz µF µF µF mΩ 106 Hrs Notes: (1) Rating is conditional on the module being directly soldered to a 4-layer PCB with 1 oz. copper. See the SOA curves or contact the factory for appropriate derating. The PTH03050Y and PTH05050Y require no derating up to 85 °C operating temperature and natural convection airflow. (2) Up to 10 ms pulse period at 10 % maximum duty. (3) This control pin has an internal pull-up to the input voltage Vin. If it is left open-circuit the module will operate when input power is applied. A small low-leakage (<100 nA) MOSFET is recommended for control. For further information, consult the related application note. (4) An input capacitor is required for proper operation. The capacitor must be rated for a minimum of 300 mA rms (750 mA rms for 12-V input) of ripple current. (5) The typical value of external output capacitance value ensures that V TT meets the specified transient performance requirements for the memory bus terminations. Lower values of capacitance may be possible when the measured peak change in output current is consistently less than 3 A. (6) This is the calculated maximum. The minimum ESR limitation will often result in a lower value. Consult the application notes for further guidance. (7) This is the typcial ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 mΩ as the minimum when using max-ESR values to calculate. For technical support and further information, visit http://power.ti.com PTHxx050Y —Series Typical Characteristics 6-A Non-Isolated DDR/QDR Memory Bus Termination Modules SLTS221 – MARCH 2004 Characteristic Data; VREF =1.25 V (See Note A) Safe Operating Area; VREF =1.25 V Efficiency vs Load Current (See Note B) PTH03050Y/PTH05050Y at nominal VIN 100 90 Efficiency - % VIN 80 3.3 V 5V 12 V 70 60 Ambient Temperature (°C) 80 90 70 Airflow 60 Nat Conv 50 40 30 50 20 0 1 2 3 4 5 6 0 1 2 Iout - Amps 3 4 5 6 Iout (A) Output Ripple vs Load Current (See Note 2 to Table) PTH12050Y only; VIN =12 V 50 90 Ripple - mV VIN 30 3.3 V 5V 12 V 20 10 Ambient Temperature (°C) 80 40 Airflow 70 400LFM 200LFM 100LFM Nat Conv 60 50 40 30 0 20 0 1 2 3 4 5 6 0 1 2 Iout - Amps 3 4 5 6 Iout (A) Power Dissipation vs Load Current 1.5 Transient Performance for ∆ 4-A Load Change 1.2 Pd - Watts VIN 0.9 PTH03050Y: Sink to Source Transient 3.3 V 5V 12 V 0.6 VTT – VREF (50 mV/Div) 0.3 0 0 1 2 3 4 5 6 Iout - Amps ±I TT (5 A/Div) HORIZ SCALE: 100 µs/Div Note A: Characteristic data has been developed from actual products tested at 25°C. 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