Application Note 1823 Low Dose Rate Total Dose Testing of the HS-1825AEH Current Mode PWM Controller Introduction This report summarizes the results of a low dose rate (LDR), total dose test of the HS-1825AEH current mode PWM controller. The test was specifically conducted in order to determine the total dose sensitivity under low dose rate conditions. Both the HS-1825ARH and HS-1825AEH are acceptance tested on a wafer-by-wafer basis to 300krad(Si) at high dose rate (50 to 300 rad(Si)/s). Only the HS-1825AEH is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate (0.01 rad(Si)/s). The LDR performance characterization beyond the 50krad(Si) assurance level is included in this report as indicative, but no assurance testing beyond 50krad(Si) is performed at LDR in production. Reference Documents Device features include a precision voltage reference, low power start-up circuit, high frequency oscillator, wide-band error amplifier, and fast current-limit comparator. The use of proprietary process capabilities and unique design techniques results in fast propagation delay times and high output current over a wide range of output voltages. Constructed with the Intersil Rad Hard Silicon Gate (RSG), Dielectric Isolation BiCMOS process, the HS-1825ARH, HS-1825AEH have been specifically designed to provide highly reliable performance when exposed to harsh radiation environments. • Electrically screened to DLA SMD 5962-99558 • QML qualified per MIL-PRF-38535 requirements • Maximum high dose rate total dose . . . . . . . . . . 300krad(Si) • Vertical architecture provides low dose rate immunity • Dielectric isolation process (RSG) provides latch-up immunity • MIL-STD-883G test method 1019.7 • MIL-PRF-38535 (QML) • Low start-up current. . . . . . . . . . . . . . . . . . . . . . . . 100µA (Typ) • HS-1825AEH data sheet • DLA Standard Microcircuit Drawing (SMD) 5962-99558 Part Description • Fast propagation delay . . . . . . . . . . . . . . . . . . . . . . 80ns (Typ) • 12V to 30V operation • 1A (peak-to-peak) dual output drive capability The HS-1825ARH, HS-1825AEH pulse width modulator is designed to be used in high frequency switched-mode power supplies and can be used in either current-mode or voltage-mode. It is well suited for single-ended boost converter applications. • 5.1V reference • Undervoltage lock-out (UVLO) • Programmable soft-start • Switching frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 500kHz • Latched overcurrent comparator with full cycle restart May 22, 2013 AN1823.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1823 FIGURE 1. HS-1825AEH CONCEPTUAL BLOCK DIAGRAM The HS-1825AEH is implemented in Intersil's dielectrically isolated radiation hardened silicon gate BiCMOS technology (RSG). Active devices include 30V CMOS and complementary bipolar transistors. The process in production is under MIL PRF 38535 certification and is used for a range of space qualified products. Test Fixturing Figure 2 on page 3 shows the configuration used for biased irradiation in conformance with Standard Microcircuit Drawing (SMD) 5962-99558. This configuration was used for the biased low dose rate irradiation. The unbiased low dose rate irradiation was carried out with all pins grounded. Test Description Irradiation Facilities Low dose rate testing was done at Intersil's low dose rate irradiation facility located in Palm Bay, FL. This facility was built expressly for supporting production (LDR assurance testing) of Intersil products. A description of the Intersil LDR facility can be found on the Intersil web site. The facility uses a 60Co source and maintains a 10mrad(Si)/s flux by device positioning relative to the source. Devices are packaged in PbAl boxes to shield them against low energy secondary gamma radiation, as required by MIL STD 883. 2 AN1823.0 May 22, 2013 Application Note 1823 1 1 INV VREF 16 R1 2 NON-INV +VIN 3 E/A OUT OUTPUT A 4 VC CLOCK 15 14 C1 13 R2 V2 +15V C3 R3 5 PGND RT 12 C1 C2 6 7 8 C4 CT OUTPUT B RAMP SOFT-START GND ILIM/SD 11 10 9 NOTE: V1 and V2 are separate supplies. V1, V2 = 15V, ±0.5V R1 = 6kΩ, ±5%, R2 = 10kΩ, ±5%, R3 = 10kΩ, ±1% C1 = 250pF, ±5%, C2 = 1000pF, ±5%, C3 = 1µF, ±10% C4 = 0.1µF, ±10% FIGURE 2. IRRADIATION BIAS CONFIGURATION FOR THE HS-1825AEH PER STANDARD MICROCIRCUIT DRAWING (SMD) 5962-99558, AS USED FOR BOTH LOW DOSE RATE IRRADIATION REPORTED IN THIS DOCUMENT Characterization Equipment and Procedures All electrical testing was performed outside the irradiator using the production automated test equipment (ATE) with data-logging of all parameters at each downpoint. Electrical testing was performed at room temperature. Experimental Matrix TABLE 1. NUMBER OF UNITS TESTED AT EACH CONDITION 0 krad 50 krad 100 krad 150 krad 200 krad Biased 18 18 18 18 -- Unbiased 18 18 10 10 10 NOTE: The dose downpoints are sequential on the units left to right. The experimental matrix consists of two irradiation groups; biased and unbiased, and a sequence of dose downpoints. Units were cumulatively dosed up to the maximum dose listed; Table 1 summarizes the test points and identifies the number of units tested for each condition. The number of samples in the unbiased condition changes from 18 to 10. This was due to electrical overstress damage incurred during testing the devices. 3 Samples of the HS-1825AEH were drawn from pre-production inventory for the HS-1825ARH and were packaged in the standard hermetic 16-pin ceramic flatpack (CFP) production package. Samples were processed through the standard burn-in cycle before irradiation, as required by MIL-STD-883 and were screened to the SMD 5962-99558 limits at room, low and high temperature before the radiation testing. AN1823.0 May 22, 2013 Application Note 1823 SMD Electrical Parameter Results Results for the key parameters are presented in Figures 3 through 37 for all downpoints. The plots show the median parameter values as connected points against total dose. The median values are augmented with markers at each of the extremes recorded. Table 2 lists the SMD parameters, limits, plus chart number and page. Some redundant test data and SMD parameters were omitted from the charts. These omitted charts added no information beyond those included. TABLE 2. SMD PARAMETERS, LIMITS PLUS CHART NUMBER AND PAGE PRE/POST RADIATION LIMITS +25ºC SYMBOL MIN MAX UNIT CHART NO. & PG. Reference Output Voltage VREF 5.05/5.00 5.15/5.20 V 3, 5 Reference Line Regulation VLINE -15/-20 15/20 mV 4, 5 Reference Load Regulation VLOAD -25/-50 25/50 mV 5, 6 Reference Total Output Variation VOM 5.00/4.95 5.20/5.25 mV Reference Short Circuit Current ISC 30/20 Oscillatory Initial Accuracy FO 350/300 Oscillatory Voltage Stability dFO/dV SMD ELECTRICAL PARAMETER mA 6, 6 425 kHz 7, 6 -2/-3 2/3 % 8, 6 FOM 350/300 425 kHz Clock Out High Voltage VCLKH 4.00/3.75 Clock Out Low Voltage VCLKL Oscillatory Total Variation V 9, 7 0.2 V 10, 7 E/A Input Offset Voltage VOS -10 10 mV 11, 7 E/A Input Bias Current IIB -1 1 µA 12, 7 E/A Amplifier Input Offset Current IOS -4 4 µA 13, 8 AVOL 60 dB 14, 8 E/A Common Mode Rejection Ratio CMRR 65 dB 15, 8 E/A Power Supply Rejection Ratio PSRR 80 dB 16, 8 E/A Output Sink Current IOSK 1 mA 17, 9 E/A Output Source Current IOSC -0.5 mA 18, 9 E/A Output High Voltage VOH1 4.0 V 19, 9 E/A Output Low Voltage VOL1 1.0 V 20, 9 PWM Ramp Bias Current IRAMP -8 µA 21, 10 PWM Duty Cycle Range DCRNG 40 % 22, 10 PWM E/A Out Zero DC Threshold V TH 0.89 V 23, 10 Soft-Start Charge Current ICHG 8 20/25 µA 24, 10 Soft-Start Discharge Current IDCHG 0.1 0.5 mA 25, 11 VRS 0.5 V 26, 11 ILIM Bias Current IBLIM 15 µA 27, 11 Current Limit Threshold VLIMIT 0.95/0.88 1.10 V 28, 11 Overcurrent Threshold VOVER 1.14/1.08 1.26 V 29, 12 Output Low Saturation 1 VSATL1 0.8 V Output Low Saturation 2 VSATL2 2.2 V Output High Saturation 1 VSATH1 10 V Output High Saturation 2 VSATH2 9 V 31, 12 V 32, 12 E/A Open Loop Gain Overcurrent Restart Threshold UVLO Output Low Saturation VOLS 4 1.2 30, 12 AN1823.0 May 22, 2013 Application Note 1823 TABLE 2. SMD PARAMETERS, LIMITS PLUS CHART NUMBER AND PAGE (Continued) PRE/POST RADIATION LIMITS +25ºC SYMBOL MIN MAX UNIT CHART NO. & PG. UVLO Start Threshold VSTART 8.4 9.6 V 33, 13 UVLO Stop Threshold VSTOP 9.6 V 34, 13 UVLO Hysteresis VHYS 1.2 V 35, 13 Start-Up Current ISU 300 µA 36, 13 Supply Current ICC 36 mA 37, 14 SMD ELECTRICAL PARAMETER 0.3 NOTE: Not all parameters have charts. Parameter Results FIGURE 3. REFERENCE OUTPUT VOLTAGE, VREF. THE REFERENCE TOTAL OUTPUT VARIATION, VOM, CLOSELY MATCHES VREF, SO IT IS NOT INCLUDED AS A SEPARATE CHART 5 FIGURE 4. REFERENCE VOLTAGE LINE REGULATION, V LINE AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 5. REFERENCE VOLTAGE LOAD REGULATION, V LOAD FIGURE 6. REFERENCE SHORT CIRCUIT CURRENT, I SC FIGURE 7. OSCILLATOR INITIAL FREQUENCY, F O FIGURE 8. OSCILLATOR FREQUENCY VOLTAGE STABILITY, dFO/dV 6 AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 9. CLOCK OUTPUT HIGH VOLTAGE, V CLKH FIGURE 10. CLOCK LOW OUTPUT VOLTAGE, VCLKL FIGURE 11. ERROR AMPLIFIER OFFSET VOLTAGE, VOS FIGURE 12. ERROR AMPLIFIER INPUT BIAS CURRENT, I IB 7 AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 13. ERROR AMPLIFIER INPUT OFFSET CURRENT, I OS FIGURE 14. ERROR AMPLIFIER OPEN LOOP GAIN, AVOL FIGURE 15. ERROR AMPLIFIER COMMON MODE REJECTION RATIO (CMRR) FIGURE 16. ERROR AMPLIFIER POWER SUPPLY REJECTION RATIO (PSRR) 8 AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 17. ERROR AMPLIFIER OUTPUT SINK CURRENT (I OSK) FIGURE 18. ERROR AMPLIFIER OUTPUT SOURCE CURRENT (I OSC) FIGURE 19. ERROR AMPLIFIER OUTPUT HIGH VOLTAGE (VOH1) FIGURE 20. ERROR AMPLIFIER OUTPUT LOW VOLTAGE (VOL1) 9 AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 21. PWM RAMP BIAS CURRENT (IRAMP) FIGURE 22. PWM DUTY CYCLE RANGE (D CRNG) FOR OUTPUT A FIGURE 23. PWM ERROR AMPLIFIER OUTPUT ZERO THRESHOLD VOLTAGE (V TH) FIGURE 24. SOFT START CHARGING CURRENT (ICHG ) 10 AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 25. SOFT-START DISCHARGING CURRENT (I DCHG ) FIGURE 26. OVERCURRENT RESTART THRESHOLD VOLTAGE (V RS) FIGURE 27. CURRENT LIMIT BIAS CURRENT AT 2V (IBLIM) FIGURE 28. CURRENT LIMIT THRESHOLD VOLTAGE (V LIMIT ) 11 AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 29. OVERCURRENT THRESHOLD VOLTAGE (VOVER) FIGURE 31. OUTPUT A HIGH SATURATION VOLTAGE AT IOUT = 200mA (VSATH2) 12 FIGURE 30. OUTPUT A LOW SATURATION VOLTAGE AT IOUT = 200mA (VSATL2) FIGURE 32. UNDERVOLTAGE LOCK-OUT (UVLO) OUTPUT SATURATION VOLTAGE (VOLS) AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 33. UNDERVOLTAGE LOCK-OUT START THRESHOLD (VSTART) FIGURE 34. UNDERVOLTAGE LOCK-OUT STOP THRESHOLD (VSTOP) FIGURE 35. UNDERVOLTAGE LOCK-OUT HYSTERESIS VOLTAGE (VHYS) FIGURE 36. START-UP SUPPLY CURRENT (I SU) 13 AN1823.0 May 22, 2013 Application Note 1823 Parameter Results (Continued) FIGURE 37. OPERATING SUPPLY CURRENT (I CC) Discussion and Conclusion The low dose rate downpoints of the HS-1825AEH were tested to the SMD post-irradiation limits. All parameters passed the post radiation limits at the 50krad(Si) low dose rate assurance level. The current limit (VLIMIT) and overcurrent (VOVER) threshold voltages (Figures 28 and 29), dropped just below the post radiation specifications at 150krad(Si) for the biased condition. The unbiased case for these parameters showed little movement through the 200krad(Si) dose point. The data clearly indicates that the part is capable of maintaining specified operation up to the 50krad(Si) level of radiation assurance testing for the "EH" version of the part. Further, the data indicates considerable margin with performance being maintained up to 100krad(Si). At 150krad(Si), two parameters for the biased configuration, the current limit threshold (VLIMIT) and the overcurrent threshold (VOVER) begin to drop just below specification. These two parameters in the biased condition are shown to be the most sensitive to the LDR environment. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 14 AN1823.0 May 22, 2013