DATASHEET

DATASHEET
500MHz Low Power Current Feedback Amplifiers with
Enable
EL5162, EL5163, EL5262,
EL5263, EL5362
Features
The EL5162, EL5163, EL5262, EL5263 and EL5362 are
current feedback amplifiers with a bandwidth of 500MHz. This
makes these amplifiers ideal for today’s high speed video and
monitor applications.
• 4000V/µs slew rate (EL5162 and EL5163)
With a supply current of just 1.5mA per amplifier and the
ability to run from a single supply voltage from 5V to 12V,
these amplifiers are also ideal for handheld, portable or
battery-powered equipment.
• Fast enable/disable (EL5162, EL5262 and EL5362 only)
The EL5162, EL5262 and EL5362 also incorporate an enable
and disable function to reduce the supply current to 14µA
typical per amplifier. Allowing the CE pin to float or applying a
low logic level enables the amplifier.
• High speed, 1.4GHz product available (EL5166 and EL5167)
The EL5162 is available in 6 Ld SOT-23 and 8 Ld SOIC
packages, the EL5163 in 5 Ld SOT-23 and SC-70 packages,
the EL5262 in the 10 Ld MSOP package, the EL5263 in 8 Ld
MSOP and SOIC packages, and the EL5362 in 16 Ld SOIC
(0.150”) and QSOP packages. All operate over the industrial
temperature range of -40°C to +85°C.
• 500MHz -3dB bandwidth
• 1.5mA supply current per amplifier
• Single and dual supply operation, from 5V to 12V supply
span
• Available in SOT-23 packages
• Pb-free (RoHS compliant)
• High speed, 4mA, 600MHz product available (EL5164,
EL5165 and EL5364)
Applications
• Battery-powered equipment
• Handheld portable devices
• Video amplifiers
• Cable drivers
• RGB amplifiers
• Test equipment
• Instrumentation
• Current to voltage converters
August 26, 2015
FN7388.13
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2004, 2005, 2007, 2008, 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
EL5162, EL5163, EL5262, EL5263, EL5362
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
EL5162ISZ
5162ISZ
8 Ld SOIC (150mil)
M8.15E
EL5162ISZ-T7 (Note 1)
5162ISZ
8 Ld SOIC (150mil)
M8.15E
EL5162ISZ-T13 (Note 1)
5162ISZ
8 Ld SOIC (150mil)
M8.15E
EL5162ISZ-T7A
5162ISZ
8 Ld SOIC (150mil)
M8.15E
EL5162IWZ-T7 (Note 1) (No longer available, recommended
replacement: EL5163IWZ-T7)
BAKA (Note 4)
6 Ld SOT-23
P6.064A
EL5162IWZ-T7A (Note 1) (No longer available, recommended
replacement: EL5163IWZ-T7A)
BAKA (Note 4)
6 Ld SOT-23
P6.064A
EL5163IWZ-T7 (Note 1)
BALA (Note 4)
5 Ld SOT-23
P5.064A
EL5163IWZ-T7A (Note 1)
BALA (Note 4)
5 Ld SOT-23
P5.064A
EL5163ICZ-T7 (Note 1) (No longer available, recommended
replacement: EL5163IWZ-T7)
BDA (Note 4)
5 Ld SC-70 (1.25mm)
P5.049
EL5163ICZ-T7A (Note 1) (No longer available, recommended
replacement: EL5163IWZ-T7)
BDA (Note 4)
5 Ld SC-70 (1.25mm)
P5.049
EL5262IYZ
BBTAA
10 Ld MSOP (3.0mm)
M10.118A
EL5262IYZ-T7 (Note 1)
BBTAA
10 Ld MSOP (3.0mm)
M10.118A
EL5262IYZ-T13 (Note 1)
BBTAA
10 Ld MSOP (3.0mm)
M10.118A
EL5263ISZ
5263ISZ
8 Ld SOIC (150mil)
M8.15E
EL5263ISZ-T7 (Note 1)
5263ISZ
8 Ld SOIC (150mil)
M8.15E
EL5263ISZ-T13 (Note 1)
5263ISZ
8 Ld SOIC (150mil)
M8.15E
EL5263IYZ
BBBJA
8 Ld MSOP (3.0mm)
M8.118A
EL5263IYZ-T7 (Note 1)
BBBJA
8 Ld MSOP (3.0mm)
M8.118A
EL5263IYZ-T13 (Note 1)
BBBJA
8 Ld MSOP (3.0mm)
M8.118A
EL5362ISZ
EL5362ISZ
16 Ld SOIC (150mil)
MDP0027
EL5362ISZ-T7 (Note 1)
EL5362ISZ
16 Ld SOIC (150mil)
MDP0027
EL5362ISZ-T13 (Note 1)
EL5362ISZ
16 Ld SOIC (150mil)
MDP0027
EL5362IUZ
5362IUZ
16 Ld QSOP
MDP0040
EL5362IUZ-T7 (Note 1)
5362IUZ
16 Ld QSOP
MDP0040
EL5362IUZ-T13 (Note 1)
5362IUZ
16 Ld QSOP
MDP0040
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for EL5162, EL5163, EL5262, EL5263, EL5362. For more information on
MSL, please see tech brief TB363.
4. The part marking is located on the bottom of the part.
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FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Pin Configurations
NC 1
IN- 2
+
IN+ 3
VS- 4
8 CE
OUT 1
7 VS+
VS- 2
6 OUT
IN+ 3
OUT 1
IN+ 3
VS- 4
+ -
6 VS+
OUT 1
5 CE
VS- 2
4 IN-
IN+ 3
5 VS+
+ -
4 IN-
5 NC
EL5263
(8 LD SOIC, MSOP)
TOP VIEW
EL5262
(10 LD MSOP)
TOP VIEW
IN- 2
EL5163
(5 LD SOT-23, SC-70)
TOP VIEW
EL5162
(6 LD SOT-23)
TOP VIEW
EL5162
(8 LD SOIC)
TOP VIEW
10 VS+
+
+
CE 5
OUT1 1
9 OUT
IN- 2
8 IN-
IN+ 3
7 IN+
6 CE
VS- 4
8 VS+
7 OUT2
+
+
6 IN5 IN+
EL5362
(16 LD SOIC, QSOP)
TOP VIEW
INA+ 1
CEA 2
16 INA+
VS- 3
CEB 4
14 VS+
+
-
INB+ 5
INC+ 8
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3
13 OUTB
12 INB-
NC 6
CEC 7
15 OUTA
11 NC
+
-
10 OUTC
9 INC-
FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Maximum Slew Rate of VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Maximum Voltage between IN+ and IN-, disabled . . . . . . . . . . . . . . . ±1.5V
Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS-) -0.5V to (VS+) +0.5V
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature Range . . . . . . . . . . . . . . -40°C to +85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . See Curves on page 8
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Electrical Specifications
VS+ = +5V, VS- = -5V, RF = 750Ω for AV = 1, RF = 400Ω for AV = 2, RL = 150Ω, CE = 0V, TA = +25°C unless
otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
BW1
0.1dB Bandwidth
SR
Slew Rate
tS
0.1% Settling Time
eN
AV = +1, RL = 500ΩRF = 598Ω
500
MHz
AV = +2, RL = 150ΩRF = 422Ω
233
MHz
30
MHz
VO = -2.5V to +2.5V, AV = +2, RL = 100Ω
(EL5262, EL5263, EL5362)
2000
2500
4000
V/µs
VO = -2.5V to +2.5V, AV = +2, RL = 100Ω
(EL5162, EL5163)
2800
4000
6000
V/µs
VOUT = -2.5V to +2.5V, AV = +1
25
ns
Input Voltage Noise
3
nV/Hz
iN-
IN- Input Current Noise
10
pA/Hz
iN+
IN+ Input Current Noise
6.5
pA/Hz
dG
Differential Gain Error (Note 5)
AV = +2
0.05
%
dP
Differential Phase Error (Note 5)
AV = +2
0.15
°
DC PERFORMANCE
VOS
Offset Voltage
TCVOS
Input Offset Voltage Temperature
Coefficient
ROL
Open Loop Transimpedance Gain
-5
Measured from TMIN to TMAX
1.5
+5
mV
6
µV/°C
500
1000
kΩ
V
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range
Guaranteed by CMRR test
±3
±3.3
CMRR
Common Mode Rejection Ratio
VIN = ±3V
50
62
75
dB
-ICMR
- Input Current Common Mode Rejection
-1
0.22
+1
µA/V
+IIN
+ Input Current
-8
0.5
+8
µA
-IIN
- Input Current
-10
2
+10
µA
RIN
Input Resistance
0.8
1.6
3
MΩ
CIN
Input Capacitance
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FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Electrical Specifications
VS+ = +5V, VS- = -5V, RF = 750Ω for AV = 1, RF = 400Ω for AV = 2, RL = 150Ω, CE = 0V, TA = +25°C unless
otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
RL = 150Ω to GND
±3.35
±3.6
±3.75
V
RL = 1kΩ to GND
±3.75
±3.9
±4.15
V
Output Current
RL = 10Ω to GND
60
100
ISON
Supply Current - Enabled, per Amplifier
No load, VIN = 0V
1.3
1.5
2.0
mA
ISOFF-
Supply Current - Disabled, per Amplifier
No load, VIN = 0V (EL5162, EL5262, EL5362
Only)
-25
-14
0
µA
0
10
+25
µA
PSRR
Power Supply Rejection Ratio
DC, VS = ±4.75V to ±5.25V
65
76
-IPSR
- Input Current Power Supply Rejection
DC, VS = ±4.75V to ±5.25V
-0.5
0.1
PARAMETER
DESCRIPTION
TEST CONDITIONS
OUTPUT CHARACTERISTICS
VO
IOUT
Output Voltage Swing
mA
SUPPLY
ISOFF+
dB
+0.5
µA/V
ENABLE (EL5162, EL5262, EL5362 ONLY)
tEN
Enable Time
380
ns
tDIS
Disable Time
800
ns
IIHCE
CE Pin Input High Current
CE = VS+
1
5
25
µA
IILCE
CE Pin Input Low Current
CE = (VS+) -5V
-1
0
+1
µA
VIHCE
CE Input High Voltage for Power-down
VILCE
CE Input Low Voltage for Power-up
(VS+) - 1
V
(VS+) - 3
V
NOTES:
5. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz.
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Typical Performance Curves
NORMALIZED GAIN (dB)
+3
+2
+1
+4
VS+ = +5V
VS- = -5V
RL = 500Ω
RF = 598Ω
+3
+2
NORMALIZED GAIN (dB)
+4
0
-1
-2
-3
-4
VS+ = +5V
VS-= -5V
RF = 375Ω
+1
0
-1
-2
-3
-4
-5
-5
-6
100k
1M
10M
100M
-6
100k
1G
1M
FREQUENCY (Hz)
+2
+3
+1
+2
0
-1
-2
-3
-4
-5
-6
-7
VS+= +5V
VS- = -5V
AV = +10
RL = 150Ω
RF = 375Ω
-8
100k
+1
0
-1
-2
-3
-4
-5
-6
1M
10M
100M
VS+ = +5V
VS- = -5V
RL = 150Ω
RF = 422Ω
-7
100k
1G
1M
FREQUENCY (Hz)
+4
+1
+3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
+5
+2
0
-1
-2
-3
-6
-7
100k
VS+ = +5V
VS- = -5V
RL = 150Ω
RF = 422Ω
10M
100M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE FOR AV = +4
6
1G
AV = +1
RL = 150Ω
RF = 698Ω
+2
±6V
+1
0
-1
VS+, VS- =
1G
±5V
±4V
-2
±3V
±2.5V
-3
-4
1M
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100M
FIGURE 4. FREQUENCY RESPONSE FOR AV = +2
+3
-5
10M
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE FOR AV = +10
-4
1G
FIGURE 2. FREQUENCY RESPONSE FOR AV = +4.6
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
FIGURE 1. FREQUENCY RESPONSE FOR AV = +1
10M
100M
FREQUENCY (Hz)
-5
100k
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS ±VS
FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Typical Performance Curves
(Continued)
OUTPUT IMPEDANCE (Ω)
100
VS+ = +5V
VS- = -5V
AV = +2
VS+= +5V
VS- = -5V
AV = +2
RL = 150Ω
10
1
1V/DIV
INPUT RISE TIME
1.028ns
OUTPUT RISE
TIME 2.218ns
2V/DIV
0.1
10k
100k
1M
10M
100M
4ns/DIV
FREQUENCY (Hz)
FIGURE 7. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY
1V/DIV
INPUT FALL
TIME 1.036ns
OUTPUT FALL
TIME 2.21ns
FIGURE 8. EL5262 OUTPUT RISE TIME
VS+ = +5V
VS- = -5V
AV = +2
RL = 150Ω
CE
2V/DIV
VOUT
CE = 5V / DIV
VOUT = 200mV / DIV
M = 100ns
4ns/DIV
100ns/DIV
FIGURE 9. EL5262 OUTPUT FALL TIME
FIGURE 10. TURN ON TIME (EL5162, EL5262, EL5362)
0
VS+ = +5V
-10 V = -5V
S-20 AV = +2
RL = 150Ω
-30
PSRR (dB)
CE
CE = 5V / DIV
VOUT = 200mV / DIV
M = 100ns
-40
-50
-60
-70
-80
VOUT
-90
-100
100
100ns/DIV
FIGURE 11. TURN OFF TIME (EL5162, EL5262, EL5362)
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1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. PSRR (VS+) vs FREQUENCY
FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Typical Performance Curves
(Continued)
0
1.4
POWER DISSIPATION (W)
PSRR (dB)
VS+ = +5V
-10 VS- = -5V
-20 AV = +2
RL = 150Ω
-30
-40
-50
-60
-70
-80
-90
-100
100
1k
10k
100k
1M
10M
1.2 1.250W
0.8 909mW
0.6
SO8
JA = +110°C/W
0.4
0.2
0
25
FREQUENCY (Hz)
0.50
0.8
QSOP16
JA = +112°C/W
0.6
0.4
0.2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.40
0.35
SOT23-5/6
JA = +230°C/W
0.30
0.25
0.20
0.15
0.10
0.05
0
25
75 85 100
50
125
0
150
0
25
1.0
125
150
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.9
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.9 870mW
0.8
MSOP8/10
JA = +115°C/W
0.6
75 85 100
FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.7
50
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
0.5
0.4
0.3
0.2
909mW
0.8
SO16 (0.15 0”)
JA = +110°C/W
0.7
0.6
625mW
0.5
0.4
SO8
JA = +160°C/W
0.3
0.2
0.1
0.1
0
150
125
0.45 435mW
POWER DISSIPATION (W)
POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.0 893mW
1.0
75 85 100
FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
1.2
0
50
AMBIENT TEMPERATURE (°C)
FIGURE 13. PSRR (VS-) vs FREQUENCY
1.4
SO16 (0.150”)
JA = +80°C/W
1.0
0
100M
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
25
75 85
50
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
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0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Typical Performance Curves
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.45
1.0
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.2
(Continued)
0.8
633mW
QSOP16
JA = +158°C/W
0.6
0.4
0.2
0
0
25
50
75 85 100
391mW
0.40
0.35
0.30
SOT23-5/6
JA = +256°C/W
0.25
0.20
0.15
0.10
0.05
0
150
125
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
25
AMBIENT TEMPERATURE (°C)
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
0.6
POWER DISSIPATION (W)
50
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
486mW
0.5
MSOP8/10
JA = +206°C/W
0.4
0.3
0.2
0.1
0
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
August 26, 2015
FN7388.13
Updated the Ordering Information table on page 2.
April 6, 2015
FN7388.12
Added Note 4 to the Ordering Information table on page 2.
Added Revision History and About Intersil.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7388.13
August 26, 2015
EL5162, EL5163, EL5262, EL5263, EL5362
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
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Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.95
D
0.08-0.20
A
5
6
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
1
(0.60)
3
2
0.20 C
2x
0.40 ±0.05
B
5
SEE DETAIL X
3
0.20 M C A-B
D
TOP VIEW
2.90
5
END VIEW
10° TYP
(2 PLCS)
0.15 C A-B
2x
H
1.14 ±0.15
C
SIDE VIEW
0.10 C
0.05-0.15
1.45 MAX
SEATING PLANE
DETAIL "X"
(0.25) GAUGE
PLANE
0.45±0.1
4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
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EL5162, EL5163, EL5262, EL5263, EL5362
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
D
A
0.08-0.20
5
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
2
5
(0.60)
0.20 C
2x
0.95
SEE DETAIL X
B
0.40 ±0.05
3
END VIEW
0.20 M C A-B D
TOP VIEW
10° TYP
(2 PLCS)
2.90
5
H
0.15 C A-B
2x
C
1.45 MAX
1.14 ±0.15
0.10 C
SIDE VIEW
SEATING PLANE
(0.25) GAUGE
PLANE
0.45±0.1
0.05-0.15
4
DETAIL "X"
(0.60)
(1.20)
NOTES:
(2.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
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Package Outline Drawing
M10.118A (JEDEC MO-187-BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0 ± 0.1
A
0.25
10
DETAIL "X"
CAB
0.18 ± 0.05
SIDE VIEW 2
4.9 ± 0.15
3.0 ± 0.1
1.10 Max
B
PIN# 1 ID
1
2
0.95 BSC
0.5 BSC
TOP VIEW
Gauge
Plane
0.86 ± 0.09
H
0.25
C
3°±3°
SEATING PLANE
0.10 ± 0.05
0.23 +0.07/ -0.08
0.08 C A B
0.55 ± 0.15
0.10 C
DETAIL "X"
SIDE VIEW 1
5.80
4.40
3.00
NOTES:
0.50
0.30
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
Plastic interlead protrusions of 0.25mm max per side are not
included.
4.
1.40
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
TYPICAL RECOMMENDED LAND PATTERN
6.
This replaces existing drawing # MDP0043 MSOP10L.
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Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0±0.1
8
A
0.25
CAB
3.0±0.1
4.9±0.15
DETAIL "X"
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
0.18 ± 0.05
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.33 +0.07/ -0.08
0.08 C A B
0.10 ± 0.05
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
4.40
3.00
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
4.
Plastic interlead protrusions of 0.25mm max per side are not
included.
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
6.
This replaces existing drawing # MDP0043 MSOP 8L.
0.65
0.40
1.40
TYPICAL RECOMMENDED LAND PATTERN
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Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
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Small Outline Transistor Plastic Packages (SC70-5)
P5.049
D
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
VIEW C
e1
INCHES
5
4
E
CL
1
2
CL
3
e
E1
b
CL
0.20 (0.008) M
C
C
CL
A
A2
SEATING
PLANE
A1
-C-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.031
0.043
0.80
1.10
-
A1
0.000
0.004
0.00
0.10
-
A2
0.031
0.039
0.80
1.00
-
b
0.006
0.012
0.15
0.30
b1
0.006
0.010
0.15
0.25
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.009
0.08
0.20
6
D
0.073
0.085
1.85
2.15
3
E
0.071
0.094
1.80
2.40
-
E1
0.045
0.053
1.15
1.35
3
e
e1
L
0.10 (0.004) C
WITH
PLATING
b1
0.0256 Ref
0.0512 Ref
0.010
c1
0.018
-
1.30 Ref
0.26
-
0.46
0.017 Ref.
0.420 Ref.
L2
0.006 BSC
0.15 BSC
0o
N
c
0.65 Ref
L1

b
MILLIMETERS
8o
0o
5
4
-
8o
-
5
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.15
0.25
Rev. 3 7/07
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1

L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
4X 1
VIEW C
0.4mm
0.75mm
2.1mm
0.65mm
TYPICAL RECOMMENDED LAND PATTERN
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Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
E
INCHES
PIN #1
I.D. MARK
E1
1
(N/2)
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
SYMBOL
QSOP16
QSOP24
QSOP28
TOLERANCE
NOTES
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
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