DATASHEET

ISL12028, ISL12028A
Data Sheet
Real Time Clock/Calendar with I2C Bus™
and EEPROM
The ISL12028 device is a low power real time clock with
clock/calendar, power-fail indicator, clock output and crystal
compensation, two periodic or polled alarms (CMOS output),
intelligent battery backup switching, CPU Supervisor,
integrated 512x8-bit EEPROM configured in 16 bytes per
page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12028 and ISL12028A Power Control Settings are
different. The ISL12028 uses the Legacy Mode Setting, and
the ISL12028A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12028A. Please refer to “Power Control Operation” on
page 14 for more details. Also, please refer to “I2C
Communications During Battery Backup and LVR Operation”
on page 25 for important details.
Pinout
ISL12028, ISL12028A
(14 LD TSSOP, SOIC)
TOP VIEW
X1
X2
NC
NC
NC
RESET
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
VBAT
IRQ/FOUT
NC
NC
SCL
SDA
NC = No internal connection
August 14, 2015
Features
• Real Time Clock/Calendar
- Tracks time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
- Power Failure Detection
- 800nA Battery Supply Current
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM:
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• CPU Supervisor Functions:
- Power On Reset, Low Voltage Sense
- Watchdog Timer (0.25s, 0.75s and 1.75s)
• I2C Interface
- 400kHz Data Transfer Rate
• 14 Ld SOIC and 14 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
FN8233.10
Utility Meters
HVAC Equipment
Audio/Video Components
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/Automotive
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas LLC 2005, 2006, 2008, 2010, 2015.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL12028, ISL12028A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL12028IB27Z
12028IB27Z
VBAT TRIP
POINT
(V)
BSW BIT
DEFAULT
SETTING
VRESET
VOLTAGE
(V)
TEMP. RANGE
(°C)
VDD < VBAT
BSW = 1
2.63
-40 to +85
14 Ld SOIC
PACKAGE
(Pb-free)
PKG.
DWG. #
M14.15
ISL12028IBZ
12028IBZ
VDD < VBAT
BSW = 1
4.38
-40 to +85
14 Ld SOIC
M14.15
ISL12028IV27Z
12028 IV27Z
VDD < VBAT
BSW = 1
2.63
-40 to +85
14 Ld TSSOP
M14.173
ISL12028IVZ
12028 IVZ
VDD < VBAT
BSW = 1
4.38
-40 to +85
14 Ld TSSOP
M14.173
12028AIB 27Z
ISL12028AIB27Z
(No longer available or
supported)
2.2
BSW = 0
2.63
-40 to +85
14 Ld SOIC
M14.15
2028A IV27Z
ISL12028AIV27Z
(No longer available or
supported)
2.2
BSW = 0
2.63
-40 to +85
14 Ld TSSOP
M14.173
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12028, ISL12028A. For more information on MSL please see
techbrief TB363
Block Diagram
OSC COMPENSATION
32.768kHZ
X1
OSCILLATOR
X2
SCL
SDA
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
VDD
VBACK
SELECT
CONTROL
SERIAL
INTERFACE DECODE
LOGIC
DECODER
CONTROL/
REGISTERS
(EEPROM)
STATUS
REGISTERS
8
WATCHDOG
TIMER
RESET
2
COMPARE
ALARM
(SRAM)
LOW VOLTAGE
RESET
MASK
IRQ/FOUT
TIMER
FREQUENCY 1Hz
CALENDAR
DIVIDER
LOGIC
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
2
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
6
RESET
RESET is a reset signal output. This signal notifies a host processor that the “Watchdog” time period has expired or
that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended
value for the pull-up resistor is 5k. If unused, connect to ground.
7
GND
Ground.
8
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
9
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is
always active (not gated).
12
IRQ/FOUT
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The
function is set via the configuration register. It is a CMOS push-pull output and does not require a pull-up resistor.
13
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the
VDD supply fails. This pin should be tied to ground if not used.
14
VDD
Power Supply.
3, 4, 5, 10,
11
NC
No Internal Connection.
3
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Absolute Maximum Ratings
Thermal Information
Voltage on VDD, VBAT, SCL, SDA, RESET and IRQ/FOUT Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model (MIL-STD-883, Method 3014) . . . . . . .>±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>175V
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
14 Ld SOIC Package (Notes 5, 6) . . . .
90
40
14 Ld TSSOP Package (Note 5, 6) . . .
110
35
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is taken at the package top center.
DC Operating Characteristics
SYMBOL
Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C
and VDD = 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNIT
VDD
Main Power Supply
2.7
5.5
V
VBAT
Backup Power Supply
1.8
5.5
V
Electrical Specifications
SYMBOL
NOTES
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
IDD1
Supply Current with I2C Active
IDD2
Supply Current for Non-Volatile
Programming
IDD3
Supply Current for Main
Timekeeping (Low Power Mode)
IBAT
Battery Supply Current
IBATLKG
Battery Input Leakage
VTRIP
VBAT Mode Threshold
MAX
(Note 16)
UNIT
NOTES
VDD = 2.7V
500
µA
7, 8, 9
VDD = 5.5V
800
µA
VDD = 2.7V
2.5
mA
VDD = 5.5V
3.5
mA
VDD = VSDA = VSCL = 2.7V
10
µA
CONDITIONS
MIN
(Note 16)
TYP
20
µA
VBAT = 1.8V,
VDD = VSDA = VSCL = VRESET = 0V
VDD = VSDA = VSCL = 5.5V
800
1000
nA
VBAT = 3.0V,
VDD = VSDA = VSCL = VRESET = 0V
850
1200
nA
100
nA
VDD = 5.5V, VBAT = 1.8V
1.8
2.2
VTRIPHYS
VTRIP Hysteresis
30
VBATHYS
VBAT Hysteresis
50
VDD SR-
VDD Negative Slew Rate
2.6
7, 8, 9
9
7, 10, 11
V
11
mV
11, 13
mV
11, 13
10
V/ms
12
VDD = 5.5V
IOL = 3mA
0.3*VDD
V
VDD = 2.7V
IOL = 1mA
0.3*VDD
V
IRQ/FOUT OUTPUT
VOL
VOH
Output Low Voltage
Output High Voltage
4
VDD = 5.5V
IOL = -1.0mA
VDD x 0.7
V
VDD = 2.7V
IOL = -0.4mA
VDD x 0.7
V
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Electrical Specifications
SYMBOL
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNIT
100
400
nA
NOTES
RESET OUTPUT
ILO
Output Leakage Current
VDD = 5.5V
VOUT = 5.5V
VOL
Output Low Voltage
VDD = 5.5V
IOL = 3mA
0.4
V
VDD = 2.7V
IOL = 1mA
0.4
V
Watchdog Timer/Low Voltage Reset Parameters Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
tRPD
PARAMETER
CONDITIONS
MIN
(Note 16)
VDD Detect to RESET LOW
TYP
(Note 5)
MAX
(Note 16)
UNITS
NOTES
ns
13
500
tPURST
Power-Up Reset Time-Out Delay
100
VRVALID
Minimum VDD for Valid RESET
Output
1.0
VRESET
ISL12028-4.5A Reset Voltage
Level
4.59
4.64
4.69
V
ISL12028 Reset Voltage Level
4.33
4.38
4.43
V
ISL12028-3 Reset Voltage Level
3.04
3.09
3.14
V
ISL12028-2.7A Reset Voltage
Level
2.87
2.92
2.97
V
ISL12028-2.7 Reset Voltage Level
2.58
2.63
2.68
V
1.70
1.75
1.801
s
725
750
775
ms
225
250
275
ms
225
250
275
ms
tWDO
Watchdog Timer Period
tRST
Watchdog Timer Reset Time-Out
Delay
tRSP
I2C Interface Minimum Restart
Time
32.768kHz crystal between X1 and
X2
32.768kHz crystal between X1 and
X2
250
400
ms
V
1.2
µs
>2,000,000
Cycles
50
Years
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature 75°C
Serial Interface (I2C) Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNITS
VIL
SDA, and SCL Input Buffer LOW
Voltage
SBIB = 1 (Under VDD mode)
-0.3
0.3 x VDD
V
VIH
SDA, and SCL Input Buffer HIGH
Voltage
SBIB = 1 (Under VDD mode)
0.7 x VDD
VDD + 0.3
V
SBIB = 1 (Under VDD mode)
0.05 x VDD
Hysteresis SDA and SCL Input Buffer
Hysteresis
VOL
NOTES
V
SDA Output Buffer LOW Voltage
IOL = 4mA
0.4
V
ILI
Input Leakage Current on SCL
VIN = 5.5V
0
0.1
10
µA
ILO
I/O Leakage Current on SDA
VIN = 5.5V
0.1
10
µA
400
kHz
50
ns
TIMING CHARACTERISTICS
fSCL
tIN
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
5
Any pulse narrower than the max spec
is suppressed.
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Serial Interface (I2C) Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNITS
900
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VDD,
until SDA exits the 30% to 70% of VDD
window.
tBUF
Time the bus must be free before
the start of a new transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30%
of VDD to SCL falling edge crossing
70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 70%
of VDD to SDA entering the 30% to
70% of VDD window.
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
0
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
Cpin
SDA, and SCL Pin Capacitance
tWC
Non-volatile Write Cycle Time
10
400
12
NOTES
pF
10
pF
20
ms
14
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 + 0.1 x Cb
250
ns
15
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 + 0.1 x Cb
250
ns
15
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
15
SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
Off-chip
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
1
k
15
Cb
RPU
NOTES:
7. IRQ/FOUT Inactive (no frequency output and no alarms).
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT  1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Timing Diagrams
tHIGH
tF
SCL
tLOW
tR
tHD:STO
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tDH
tAA
tBUF
SDA
(OUTPUT TIMING)
FIGURE 1. BUS TIMING
SCL
8TH BIT OF LAST BYTE
SDA
ACK
tWC
STOP
CONDITION
START
CONDITION
FIGURE 2. WRITE CYCLE TIMING
tRSP
tRSP>tWDO
tRSP>tWDO
tRSP<tWDO
tRST
tRST
SCL
SDA
RESET
START
STOP START
Note: All inputs are ignored during the active reset period (tRST).
FIGURE 3. WATCHDOG TIMING
VRESET
VDD
tPURST
tPURST
tRPD
tF
tR
RESET
VRVALID
FIGURE 4. RESET TIMING
7
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Typical Performance Curves
Temperature is +25°C unless otherwise specified.
0.9
4.0
BSW = 0 OR 1
3.5
0.7
SCL, SDA PULL-UPS = 0V
3.0
2.5
2.0
1.5
1.0
SCL, SDA PULL-UPS = VBAT
0.5
BSW = 0 OR 1
0.0
1.8
2.3
2.8
3.3
3.8
VBAT (V)
0.5
0.4
0.3
0.2
0.1
4.3
4.8
0.0
1.8
5.3
FIGURE 5. IBAT vs VBAT, SBIB = 0
3.3
3.8
VBAT(V)
4.3
4.8
5.3
1.2
VDD = 5.5V
4.0
VBAT = 3.0V
1.0
IBAT (µA)
3.5
IDD (µA)
2.8
1.4
4.5
VDD = 3.3V
3.0
2.5
2.0
0.8
0.6
0.4
1.5
1.0
0.2
0.5
0.0
-45 -35 -25 -15
-5
5 15 25 35 45
TEMPERATURE (°C)
55
65
75
0.0
-45 -35 -25 -15
85
-5
5 15 25 35 45
TEMPERATURE (°C)
55
65
75
85
FIGURE 8. IBAT vs TEMPERATURE
FIGURE 7. IDD3 vs TEMPERATURE
80
4.5
PPM CHANGE FROM ATR = 0
4.0
3.5
3.0
IDD (µA)
2.3
FIGURE 6. IBAT vs VBAT, SBIB = 1
5.0
2.5
2.0
1.5
1.0
0.5
0.0
SCL, SDA PULL-UPS = 0V
BSW = 0 OR 1
0.6
IBAT (µA)
IBAT (µA)
0.8
1.8
2.3
2.8
3.3
3.8
4.3
VDD (V)
FIGURE 9. IDD3 vs VDD
8
4.8
5.3
60
40
20
0
-20
-40
-32 -28 -24 -20 -16 -12 -8 -4
0
4
8
12 16 20 24 28
ATR SETTING
FIGURE 10. FOUT vs ATR SETTING
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Description
The ISL12028 device is a Real Time Clock with clock/calendar,
two polled alarms with integrated 512x8-bit EEPROM, oscillator
compensation, CPU Supervisor (Power-On-Reset, Low
Voltage Sensing and Watchdog Timer) and battery backup
switch.
The oscillator uses an external, low-cost 32.768kHz crystal.
All compensation and trim components are integrated on the
chip. This eliminates several external discrete components
and a trim capacitor, saving board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes and Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week.
The calendar is correct through 2099, with automatic leap
year correction.
The Dual Alarms can be set to any Clock/Calendar value for a
match. For instance, every minute, every Tuesday, or 5:23 AM
on March 21. The alarms can be polled in the Status Register
or can provide a hardware interrupt (IRQ/FOUT pin). There is a
repeat mode for the alarms allowing a periodic interrupt.
The IRQ/FOUT pin may be software selected to provide a
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
The ISL12028 device integrates CPU Supervisory functions
(POR, WDT) and Battery Switch. There is Power-On-Reset
(RESET) output with 250ms delay from power on when the
VDD supply crosses the VRESET threshold for the device. It
will also assert RESET when VDD goes below the specified
VRESET threshold for the device. The VRESET threshold is
selectable via VTS2/VTS1/VTS0 registers to five (5)
pre-selected levels. There is Watchdog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s and 1.75s) and
disabled setting. The Watchdog Timer activates the RESET
pin when it expires. Normally, the I2C Interface is disabled
when the RESET output is active, but this can be changed
by using a register bit to enable I2C operation in battery
backup mode.
The device offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or SuperCap.
The entire ISL12028 device is fully operational from 2.7 to
5.5V and the clock/calendar portion of the ISL12028 device
remains fully operational down to 1.8V (Standby Mode).
The ISL12028 device provides 4k bits of EEPROM with 8
modes of BlockLock™ control. The Block Lock allows a
safe, secure memory for critical user and configuration data,
while allowing a large user storage area.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not
9
gated). The pull-up resistor on this pin must use the same
voltage source as VDD.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. The
input buffer is always active (not gated).
This open drain output requires the use of a pull-up resistor.
The pull-up resistor on this pin must use the same voltage
source as VDD. The output circuitry controls the fall time of
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz I2C interface
speed.
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event the VDD
supply fails. This pin can be connected to a battery, a
SuperCap or tied to ground if not used.
Note that the device is not guaranteed to operate with
VBAT < 1.8V. If the battery voltage is expected to drop lower
than this minimum, correct operation of the device,
(especially after a VDD power-down cycle) is not
guaranteed.
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/FOUT mode is selected via
the frequency out control bits of the control/status register. It
has a CMOS push-pull output and can be used to clock
other devices and maintain low power dissipation.
• Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action.
• Frequency Output Mode. The pin outputs a clock signal,
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C.
RESET
The RESET signal output can be used to notify a host
processor that the Watchdog timer has expired or the VDD
voltage supply has dipped below the VRESET threshold. It is
an open drain, active LOW output. Recommended value for
the pull-up resistor is 5k. If unused, it can be tied to ground.
In battery mode, the Watchdog timer function is disabled.
The RESET signal output is asserted LOW when the VDD
voltage supply has dipped below the VRESET threshold but
the RESET signal output will not return HIGH until the device
is back to VDD mode (out of Batttery Backup mode) even if
the VDD voltage is above VRESET threshold.
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal is
FN8233.10
August 14, 2015
ISL12028, ISL12028A
used with the ISL12028 to supply a timebase for the real time
clock. Internal compensation circuitry provides high accuracy
over the operating temperature range from -40°C to +85°C.
This oscillator compensation network can be used to calibrate
the crystal timing accuracy over-temperature either during
manufacturing or with an external temperature sensor and
microcontroller for active compensation. X2 is intended to
drive a crystal only, and should not drive any external circuit.
Note: No external compensation resistors or capacitors are
needed or are recommended to be connected to the X1 and
X2 pins.
X1
X2
FIGURE 11. RECOMMENDED CRYSTAL CONNECTION
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of the second, minute, hour, day, date, month and year. The
RTC has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that controls
24 hour or AM/PM format. When the ISL12028 powers up
after the loss of both VDD and VBAT, the clock will not
operate until at least one byte is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of the
Real Time Clock. The RTC Registers can then be read in a
Sequential Read Mode. Since the clock runs continuously
and read takes a finite amount of time, there is a possibility
that the clock could change during the course of a read
operation. In this device, the time is latched by the read
command (falling edge of the clock on the ACK bit prior to
RTC data output) into a separate latch to avoid time changes
during the read operation. The clock continues to run.
Alarms occurring during a read are unaffected by the read
operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. RTC Register should be written ONLY with Page
Write. To avoid changing the current time by an incomplete
write operation, write to the all 8 bytes in one write operation.
When writing the RTC registers, the new time value is
loaded into a separate buffer at the falling edge of the clock
during the Acknowledge. This new RTC value is loaded into
the RTC Register by a stop bit at the end of a valid write
sequence. An invalid write operation aborts the time update
procedure and the contents of the buffer are discarded. After
a valid write operation the RTC will reflect the newly loaded
data beginning with the next “one second” clock cycle after
10
the stop bit is written. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any non-volatile write sequences.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
accuracy of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover-temperature of the
crystal from the crystal’s nominal frequency. For example, a
>20ppm frequency deviation translates into an accuracy of
>1 minute per month. These parameters are available from
the crystal manufacturer. Intersil’s RTC family provides
on-chip crystal compensation networks to adjust
load-capacitance to tune oscillator frequency from -34ppm to
+80ppm when using a 12.5pF load crystal. For more detailed
information, see “Application Section” on page 22.
Clock/Control Registers (CCR)
The Control/Clock Registers are located in an area separate
from the EEPROM array and are only accessible following a
slave byte of “1101111x” and reads or writes to addresses
[0000h:003Fh]. The clock/control memory map has memory
addresses from 0000h to 003Fh. The defined addresses are
described in the Table 2. Writing to and reading from the
undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by performing a
byte or a page write operation directly to any address in the
CCR. Prior to writing to the CCR (except the status register),
however, the WEL and RWEL bits must be set using a three
step process (see section “Writing to the Clock/Control
Registers” on page 14).
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (5 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The nonvolatile portion (or the counter portion of the RTC) is updated
only if RWEL is set and only after a valid write operation and
stop bit. A sequential read or page write operation provides
access to the contents of only one section of the CCR per
operation. Access to another section requires a new
operation. A read or write can begin at any address in the
CCR.
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 (status register) supports a single
byte read or write only. Continued reads or writes from this
section terminates the operation.
FN8233.10
August 14, 2015
ISL12028, ISL12028A
The state of the CCR can be read by performing a random
read at any address in the CCR at any time. This returns the
contents of that register location. Additional registers are
read by performing a sequential read. The read instruction
latches all Clock registers into a buffer, so an update of the
clock does not change the time being read. A sequential
read of the CCR will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read of the CCR, the address remains at the previous
address +1 so the user can execute a current address read
of the CCR and continue reading the next Register.
BAT: Battery Supply
This bit set to “1” indicates that the device is operating from
VBAT, not VDD. It is a read-only bit and is set/reset by
hardware (ISL12028 internally). Once the device begins
operating from VDD, the device sets this bit to “0”.
AL1, AL0: Alarm Bits
Real Time Clock Registers (Volatile)
These bits announce if either alarm 0 or alarm 1 match the
real time clock. If there is a match, the respective bit is set to
‘1’. The falling edge of the last data bit in a SR Read
operation resets the flags. Note: Only the AL bits that are set
when an SR read starts will be reset. An alarm bit that is set
by an alarm occurring during an SR read operation will
remain set after the read operation is complete.
SC, MN, HR, DT, MO, YR: Clock/Calendar Registers
OSCF: Oscillator Fail Indicator
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 00 to 59,
HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or
0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1
to 12, YR (Year) is 0 to 99.
This bit is set to "1" if the oscillator is not operating or is
operating but has clock jitter, which does not affect the
accuracy of RTC counting. The bit is set to "0" if the oscillator
is functioning and does not have clock jitter. This bit is read
only, and is set/reset by hardware.
DW: Day of the Week Register
RWEL: Register Write Enable Latch
This register provides a Day of the Week status and uses
three bits DY2 to DY0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as ‘0’.
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior to any
writes to the Clock/Control Registers. Writes to RWEL bit do
not cause a non-volatile write cycle, so the device is ready
for the next operation immediately after the stop condition. A
write to the CCR requires both the RWEL and WEL bits to be
set in a specific sequence.
Y2K: Year 2000 Register
Can have value 19 or 20. As of the date of the introduction of
this device, there would be no real use for the value 19 in a
true real time clock, however.
24-Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour
format. If the MIL bit is 0, the RTC uses a 12-hour format and
H21 bit functions as an AM/PM indicator with a ‘1’,
representing PM. The clock defaults to standard time with
H21 = 0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4.
The Status Register is located in the CCR memory map at
address 003Fh. This is a volatile register only and is used to
control the WEL and RWEL write enable latches, read power
status and two alarm bits. This register is separate from both
the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR)
7
6
003Fh
BAT
AL1
Default
0
0
5
4
AL0 OSCF
0
0
11
The WEL bit controls the access to the CCR during a write
operation. This bit is a volatile latch that powers up in the
LOW (disabled) state. While the WEL bit is LOW, writes to
the CCR address will be ignored, although acknowledgment
is still issued. The WEL bit is set by writing a “1” to the WEL
bit and zeroes to the other bits of the Status Register. Once
set, WEL remains set until either reset to 0 (by writing a “0”
to the WEL bit and zeroes to the other bits of the Status
Register) or until the part powers up again. Writes to WEL bit
do not cause a non-volatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit
Status Register (SR) (Volatile)
ADDR
WEL: Write Enable Latch
3
2
1
0
0
RWEL
WEL
RTCF
0
0
0
1
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12028 internally) when
the device powers up after having lost all power to the device
(both VDD and VBAT go to 0V). The bit is set regardless of
whether VDD or VBAT is applied first. The loss of only one of
the supplies does not set the RTCF bit to “1”. On power-up
after a total power failure, all registers are set to their default
states and the clock will not increment until at least one byte
is written to the clock register. The first valid write to the RTC
section after a complete power failure resets the RTCF bit to
“0” (writing one byte is sufficient).
FN8233.10
August 14, 2015
ISL12028, ISL12028A
TABLE 2. CLOCK/CONTROL MEMORY MAP
ISL12028
DEFAULT
ISL12028A
DEFAULT
BIT
01h
01h
19/20
20h
20h
0 to 6
00h
00h
0 to 99
00h
00h
1 to 12
00h
00h
1 to 31
01h
01h
ADDR.
TYPE
REG
NAME
7
6
5
4
3
2
1
0
003F
Status
SR
BAT
AL1
AL0
OSCF
0
RWEL
WEL
RTCF
0037
RTC
(SRAM)
Y2K
0
0
Y2K21
Y2K20
Y2K13
0
0
Y2K10
DW
0
0
0
0
0
DY2
DY1
DY0
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0034
MO
0
0
0
G20
G13
G12
G11
G10
0033
DT
0
0
D21
D20
D13
D12
D11
D10
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0 to 23
00h
00h
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0 to 59
00h
00h
0 to 59
0036
0030
0014
0013
0012
Control
(EEPROM
)
RANG
E
SC
0
S22
S21
S20
S13
S12
S11
S10
00h
00h
PWR
SBIB
BSW
0
0
0
VTS2
VTS1
VTS0
4Xh
0Xh
DTR
0
0
0
0
0
DTR2
DTR1
DTR0
00h
00h
ATR
0
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
00h
00h
0011
INT
IM
AL1E
AL0E
FO1
FO0
0
0
0
00h
00h
0010
BL
BP2
BP1
BP0
WD1
WD0
0
0
0
18h
18h
Y2K1
0
0
0
0
A1Y2K10
19/20
20h
20h
DWA1
EDW1
0
DY2
DY1
DY0
0 to 6
00h
00h
000F
000E
000D
Alarm1
(EEPROM
)
YRA1
A1Y2K21 A1Y2K20 A1Y2K13
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
000C
MOA1
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
1 to 12
00h
00h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1 to 31
00h
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0 to 23
00h
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0 to 59
00h
00h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0 to 59
00h
00h
Y2K0
0
0
0
0
A0Y2K10
19/20
20h
20h
DWA0
EDW0
0
DY2
DY1
DY0
0 to 6
00h
00h
0007
0006
0005
Alarm0
(EEPROM
)
YRA0
A0Y2K21 A0Y2K20 A0Y2K13
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0004
MOA0
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1 to 12
00h
00h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1 to 31
00h
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0 to 23
00h
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0 to 59
00h
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0 to 59
00h
00h
NOTE: Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device
“Ordering Information on page 2).
Unused Bits
Bit 3 in the SR is not used, but must be zero. The Data Byte
output during a SR read will contain a zero in this bit
location.
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
12
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 14
and “Application Section” on page 22 for more information.
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following are
non-volatile.
FOUT output pin. Table 4 shows the selection bits for this
output. When using this function, the Alarm output function is
disabled.
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
BL Register
FO1
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
BP2
BP1
BP0
TABLE 3. BLOCK PROTECT PARTITIONS
PROTECTED ADDRESSES
ISL12028
0
0
0
None (Default)
None
0
0
1
180h – 1FFh
Upper 1/4
0
1
0
100h – 1FFh
Upper 1/2
0
1
1
000h – 1FFh
Full Array
1
0
0
000h – 03Fh
First 4 Pages
1
0
1
000h – 07Fh
First 8 Pages
1
1
0
000h – 0FFh
First 16 Pages
1
1
1
000h – 1FFh
Full Array
ARRAY LOCK
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits; Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output (IRQ/
FOUT). The interrupts are enabled when either the AL1E or
AL0E or both bits are set to ‘1’ and both the FO1 and FO0
bits are set to 0 (FOUT disabled).
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/FOUT output will now be pulsed each time an
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
In the case that both Alarm 0 and Alarm 1 are enabled, the
IRQ/FOUT pin will be pulsed each time either alarm matches
the RTC (both alarms can provide hardware interrupt). If the
IM bit is also set to "1", the IRQ/FOUT will be pulsed for each
of the alarms as well.
FO0
OUTPUT FREQUENCY
0
0
Alarm output (FOUT disabled)
0
1
32.768kHz
1
0
4096Hz
1
1
1Hz
Oscillator Compensation Registers
There are two trimming options.
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
X1
CX1
CRYSTAL
OSCILLATOR
X2
CX2
FIGURE 12. DIAGRAM OF ATR
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
and X2 pins to ground (see Figure 12). The value of CX1 and
CX2 is given by Equation 1:
C X =  16  b5 + 8  b4 + 4  b3 + 2  b2 + 1  b1 + 0.5  b0 + 9 pF
(EQ. 1)
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the IRQ/
13
FN8233.10
August 14, 2015
ISL12028, ISL12028A
The effective series load capacitance is the combination of
CX1 and CX2 as shown in Equation 2:
C
LOAD
1
1
1
 ---------- + -----------
C
C 
= ----------------------------------X1
C
LOAD
(EQ. 2)
X2
16  b5 + 8  b4 + 4  b3 + 2  b2 + 1  b1 + 0.5  b0 + 9
=  ----------------------------------------------------------------------------------------------------------------------------- pF


2
For example, CLOAD(ATR = 00000) = 12.5pF, CLOAD
(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) = 20.25pF.
The entire range for the series combination of load capacitance
goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these
are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using the three DTR bits.
Option 1 Standard Mode: Set “BSW = 0” (default for
ISL12028A)
Option 2 Legacy/Default Mode: Set “BSW = 1” (default for
ISL12028)
See “Power Control Operation” on page 15 for more details.
Also see “I2C Communications During Battery backup and
LVR Operation” in the “Application Section” on page 22 for
important details.
VTS2, VTS1, VTS0: VRESET Select Bits
The ISL12028 is shipped with a default VDD threshold
(VRESET) per the “Ordering Information” table on page 2.
This register is a non-volatile with no protection, therefore
any writes to this location can change the default value from
that marked on the package. If not changed with a
non-volatile write, this value will not change over normal
operating and storage conditions. However, ISL12028 has
four (4) additional selectable levels to fit the customers
application. Levels are: 4.64V(default), 4.38V, 3.09V, 2.92V
and 2.63V. The VRESET selection is via 3 bits (VTS2, VTS1
and VTS0) (see Table 6).
Care should be taken when changing the VRESET select bits.
If the VRESET voltage selected is higher than VDD, then the
device will go into RESET and unless VDD is increased, the
device will no longer be able to communicate using the I2C.
TABLE 6. VRESET SELECTION
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
DTR2
DTR1
DTR0
ESTIMATED FREQUENCY
PPM
0
0
0
0
0
1
0
+10
0
0
1
+20
0
1
1
+30
1
0
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30
VTS2
VTS1
VTS0
VRESET (V)
0
0
0
4.64
0
0
1
4.38
0
1
0
3.09
0
1
1
2.92
1
0
0
2.63
In battery mode, the RESET signal output is asserted LOW
when the VDD voltage supply has dipped below the VRESET
threshold, but the RESET signal output will not return HIGH
until the device is back to VDD mode even the VDD voltage is
above VRESET threshold.
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
Device Operation
SBIB: - Serial Bus Interface (Enable)
Writing to the Clock/Control Registers
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
“RESET” on page 9 and “Power Control Operation” on
page 15.
Changing any of the bits of the clock/control registers
requires the following steps:
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between VDD and Back Up Battery. There are two
options.
14
1. Write a 02h to the Status Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
2. Write a 06h to the Status Register to set both the Register
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a non-volatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
much shorter cycle time (t = tBUF). Writes to undefined areas
have no effect. The RWEL bit is reset by the completion of a
write to the CCR, so the sequence must be repeated to
again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an
incorrect number of bits or sending a start instead of a stop,
for example) the RWEL bit is not reset and the device
remains in an active mode. Writing all zeros to the status
register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event and trigger some action
as a result. The host can be notified by either a hardware
interrupt (the IRQ/FOUT pin) or by polling the Status Register
(SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and
AL0 for Alarm 0), indicate if an alarm has happened. The bits
are set on an alarm condition regardless of whether the IRQ/
FOUT interrupt is enabled. The AL1 and AL0 bits in the status
register are reset by the falling edge of the eighth clock of
status register read.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
1. Single Event Mode is enabled by setting the AL0E or
AL1E bit to “1”, the IM bit to “0”, and disabling the
frequency output. This mode permits a one-time match
between the alarm registers and the RTC registers. Once
this match occurs, the AL0 or AL1 bit is set to “1” and the
IRQ/FOUT output will be pulled low and will remain low
until the AL0 or AL1 bit is read, which will automatically
resets it. Both Alarm registers can be set at the same time
to trigger alarms. The IRQ/FOUT output will be set by
either alarm, and will need to be cleared to enable
triggering by a subsequent alarm. Polling the SR will
reveal which alarm has been set.
2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is
enabled by setting the AL0E or AL1E bit to “1” the IM bit
to “1”, and disabling the frequency output. If both AL0E
and AL1E bits are set to "1", then both AL0E and AL1E
PIM alarms will function. The IRQ/FOUT output will now
be pulsed each time each of the alarms occurs. This
means that once the interrupt mode alarm is set, it will
continue to alarm for each occurring match of the alarm
and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications
such as security cameras or utility meter reading.
Interrupt Mode CANNOT be used for general periodic
15
alarms, however, since a specific time period cannot be
programmed for interrupt, only matches to a specific time
of day. The interrupt mode is only stopped by disabling
the IM bit or the Alarm Enable bits.
Writing to the Alarm Registers
The Alarm Registers are non-volatile but require special
attention to insure a proper non-volatile write takes place.
Specifically, byte writes to individual registers are good for all
but registers 0006h and 0000Eh, which are the DWA0 and
DWA1 registers, respectively. Those registers will require a
special page write for non-volatile storage. The
recommended page write sequences are as follows:
1. 16-byte page writes: The best way to write or update the
Alarm Registers is to perform a 16-byte write beginning at
address 0001h (MNA0) and wrapping around and ending
at address 0000h (SCA0). This will insure that
non-volatile storage takes place. This means that the
code must be designed so that the Alarm0 data is written
starting with Minutes register, and then all the Alarm1
data, with the last byte being the Alarm0 Seconds (the
page ends at the Alarm1 Y2k register and then wraps
around to address 0000h).
Alternatively, the 16-byte page write could start with
address 0009h, wrap around and finish with address
0008h. Note that any page write ending at address
0007h or 000Fh (the highest byte in each Alarm) will not
trigger a non-volatile write, so wrapping around or
overlapping to the following Alarm's Seconds register is
advised.
2. Other non-volatile writes: It is possible to do writes of
less than an entire page, but the final byte must always
be addresses 0000h through 0004h or 0008h though
000Ch to trigger a non-volatile write. Writing to those
blocks of 5 bytes sequentially, or individually, will trigger a
non-volatile write. If the DWA0 or DWA1 registers need to
be set, then enough bytes will need to be written to
overlap with the other Alarm register and trigger the
non-volatile write. For Example, if the DWA0 register is
being set, then the code can start with a multiple byte
write beginning at address 0006h, and then write 3 bytes
ending with the SCA1 register as follows:
Addr
0006h
0007h
0008h
Name
DWA0
Y2K0
SCA1
If the Alarm1 is used, SCA1 would need to have the
correct data written.
Power Control Operation
The power control circuit accepts a VDD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
an Intersil RTC device for up to 10 years. Another option is
to use a SuperCap for applications where VDD is interrupted
FN8233.10
August 14, 2015
ISL12028, ISL12028A
for up to a month. See “Application Section” on page 22 for
more information.
There are two options for setting the change-over conditions
from VDD to Battery back-up mode. The BSW bit in the PWR
register controls this operation.
There are two discrete situations that are possible when
using Standard Mode: VBAT < VTRIP and VBAT > VTRIP.
These two power control situations are illustrated in
Figures 13 and 14.
BATTERY
BACKUP
MODE
Option 1 - Standard Mode (Default for ISL12028A)
Option 2 - Legacy Mode (Default for ISL12028)
TABLE 7. VBAT TRIP POINT WITH DIFFERENT BSW SETTING
BSW BIT
VBAT TRIP POINT
(V)
0
2.2
1
VDD < VBAT
POWER CONTROL SETTING
Standard Mode (ISL12028A)
Legacy Mode (ISL12028)
VDD
VTRIP
2.2V
VBAT
1.8V
VBAT + VBATHYS
VBAT - VBATHYS
FIGURE 13. BATTERY SWITCHOVER WHEN VBAT < VTRIP
Note that applications that have VBAT > VDD will require the
ISL12028A (standard mode) for proper start-up. Note that
the I2C may or may not be operational during battery
backup, that function is controlled by the SBIB bit. That
operation is covered after the power control section.
OPTION 1 - STANDARD POWER CONTROL MODE
(DEFAULT FOR ISL12028A)
In the Standard mode, the supply will switch over to the
battery when VDD drops below VTRIP or VBAT, whichever is
lower. In this mode, accidental operation from the battery is
prevented since the battery backup input will only be used
when the VDD supply is shut off.
To select Option 1, BSW bit in the Power Register must be
set to “BSW = 0”. Following is a description of power
switchover.
Standard Mode Power Switchover
• Normal Operating Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the
following conditions must be met:
- Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS  50mV
- Condition 2:
VDD < VTRIP
where VTRIP  2.2V
• Battery Backup Mode (VBAT) to Normal Mode (VDD)
The ISL12028 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
- Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS  50mV
- Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS  30mV
16
BATTERY BACKUP
MODE
VDD
VBAT
3.0V
VTRIP
2.2V
VTRIP
VTRIP + VTRIPHYS
FIGURE 14. BATTERY SWITCHOVER WHEN VBAT > VTRIP
OPTION 2 - LEGACY POWER CONTROL MODE
(DEFAULT FOR ISL12028)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from VDD to VBAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the VBAT voltage is
higher than VDD, then the device will enter battery backup and
unless the battery is disconnected or the voltage decreases,
the device will no longer operate from VDD. If that is the
situation on initial power-up, then I2C communication may not
be possible. For these applications, the ISL12028A should be
used.
To select Option 2, BSW bit in the Power Register must be
set to “BSW = 1”
• Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, the following
conditions must be met:
VDD < VBAT - VBATHYS
• Battery Backup Mode (VBAT) to Normal Mode (VDD)
The device will switch from the VBAT to VDD mode when the
following condition occurs:
FN8233.10
August 14, 2015
ISL12028, ISL12028A
VDD > VBAT +VBATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15.
VDD
VOLTAGE
ON
VBAT
IN
OFF
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
In battery mode, the Watchdog timer function is disabled.
Low Voltage Reset (LVR) Operation
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
Power On Reset
Application of power to the ISL12028 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VDD exceeds the device VRESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
When a power failure occurs, a voltage comparator
compares the level of the VDD line versus a preset threshold
voltage (VRESET), then generates a RESET pulse if it is
below VRESET. The reset pulse will time-out 250ms after the
VDD line rises above VRESET. If the VDD remains below
VRESET, then the RESET output will remain asserted low.
Power-up and power-down waveforms are shown in
Figure 4 on page 7. The LVR circuit is to be designed so the
RESET signal is valid down to VDD = 1.0V.
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I2C Communications During Battery
Backup and LVR Operation” on page 25.
NOTE: If the VBAT voltage drops below the data sheet
minimum of 1.8V and the VDD power cycles to 0V then back
to VDD voltage, then the RESET output may stay low and the
I2C communications will not operate. The VBAT and VDD
power will need to be cycled to 0V together to allow normal
operation again.
In battery mode, the RESET signal output is asserted LOW
when the VDD voltage supply has dipped below the VRESET
threshold. The RESET signal output will not return HIGH
until the device is back to VDD mode even the VDD voltage is
above VRESET threshold.
Watchdog Timer Operation
The device supports the I2C bidirectional serial bus protocol.
The watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set
to 3 different time-out periods or off. When the Watchdog
timer is set to off, the Watchdog circuit is configured for low
power operation. See Table 8.
TABLE 8. WATCHDOG TIMER OPERATION
Serial Communication
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
START CONDITION
WD1
WD0
DURATION
1
1
disabled
1
0
250ms
0
1
750ms
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
0
0
1.75s
STOP CONDITION
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
17
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
FN8233.10
August 14, 2015
ISL12028, ISL12028A
condition can only be issued after the transmitting device
has released the bus (see Figure 17).
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
ACKNOWLEDGE
Device Addressing
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8 bits of data
(see Figure 18).
Following a start condition, the master must output a Slave
Address Byte. The first four bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
8-bit word. The device will not acknowledge if the slave
address byte is incorrect.
In the read mode, the device will transmit 8-bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
operation is selected. A zero selects a write operation. Refer
to Figure 19.
After loading the entire Slave Address Byte from the SDA
bus, the ISL12028 compares the device identifier and device
select bits with ‘1010111’ or ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the SDA
line.
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 17. VALID START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
18
FN8233.10
August 14, 2015
ISL12028, ISL12028A
DEVICE IDENTIFIER
Array
CCR
SLAVE ADDRESS BYTE
BYTE 0
1
1
0
1
1
0
0
1
1
1
1
R/W
0
0
0
0
0
0
0
A8
WORD ADDRESS 1
BYTE 1
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS 0
BYTE 2
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
BYTE 3
FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)
Following the Slave Byte is a two byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up the internal
address counter is set to address 0h, so a current address
read of the EEPROM array starts at address 0. When
required, as part of a random read, the master must supply
the 2 Word Address Bytes as shown in Figure 19.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. That is if the random read is from the array the slave
byte must be 1010111x in both instances. Similarly, for a
random read of the Clock/Control Registers, the slave byte
must be 1101111x in both places.
Write Operations
BYTE WRITE
For a write operation, the device requires the Slave Address
Byte and the Word Address Bytes. This gives the master
access to any one of the words in the array or CCR. (Note:
Prior to writing to the CCR, the master must write a 02h, then
06h to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/Control
Registers” on page 14). Upon receipt of each address byte,
the ISL12028 responds with an acknowledge. After receiving
both address bytes the ISL12028 awaits the 8 bits of data.
After receiving the 8 data bits, the ISL12028 again responds
with an acknowledge. The master then terminates the
transfer by generating a stop condition. The ISL12028 then
begins an internal write cycle of the data to the non-volatile
memory. During the internal write cycle, the device inputs
are disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance. See
Figure 20.
19
A write to a protected block of memory is ignored, but will still
receive an acknowledge. At the end of the write command,
the ISL12028 will not initiate an internal write cycle, and will
continue to ACK commands.
Byte writes to all of the non-volatile registers are allowed,
except the DWAn registers which require multiple byte writes
or page writes to trigger non-volatile writes. See “Device
Operation” on page 14 for more information.
PAGE WRITE
The ISL12028 has a page write operation. It is initiated in the
same manner as the byte write operation; but instead of
terminating the write cycle after the first data byte is
transferred, the master can transmit up to 15 more bytes to
the memory array and up to 7 more bytes to the clock/control
registers. The RTC registers require a page write (8 bytes),
individual register writes are not allowed. (Note: Prior to
writing to the CCR, the master must write a 02h, then 06h to
the status register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Registers”
on page 14.)
After the receipt of each byte, the ISL12028 responds with
an acknowledge, and the address is internally incremented
by one. The address pointer remains at the last address byte
written. When the counter reaches the end of the page, it
“rolls over” and goes back to the first address on the same
page. This means that the master can write 16 bytes to a
memory array page or 8 bytes to a CCR section starting at
any location on that page. For example, if the master begins
writing at location 10 of the memory and loads 15 bytes, then
the first 6 bytes are written to addresses 10 through 15, and
the last 6 bytes are written to columns 0 through 5.
FN8233.10
August 14, 2015
ISL12028, ISL12028A
S
T
A
R
T
SIGNALS FROM
THE MASTER
SDA BUS
1
S
T
O
P
DATA
0000000
1 110
A
C
K
SIGNALS FROM
THE SLAVE
WORD
ADDRESS 0
WORD
ADDRESS 1
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
FIGURE 20. BYTE WRITE SEQUENCE
SIGNALS FROM
THE MASTER
1  n  16 fOR EEPROM ARRAY
1  n  8 FOR CCR
S
T
A
R
T
SDA BUS
WORD
ADDRESS 1
SLAVE
ADDRESS
1
DATA
(1)
S
T
O
P
DATA
(n)
0 0 0 00 0 0
1 1 1 0
A
C
K
SIGNALS FROM
THE SLAVE
WORD
ADDRESS 0
A
C
K
A
C
K
A
C
K
FIGURE 21. PAGE WRITE SEQUENCE
6 BYTES
6 BYTES
ADDRESS = 5
ADDRESS
ADDRESS
ADDRESS POINTER ENDS
AT ADDR = 5
10
15
FIGURE 22. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
Afterwards, the address counter would point to location 6 on
the page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over-written by the new data, one byte at a
time (refer to Figure 22).The master terminates the Data
Byte loading by issuing a stop condition, which causes the
ISL12028 to begin the non-volatile write cycle. As with the
byte write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 21 for the address,
acknowledge, and data transfer sequence.
STOPS AND WRITE MODES
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12028 resets itself without performing the write. The
contents of the array are not affected.
.
ACKNOWLEDGE POLLING
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the typical 5mS write cycle
20
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the ISL12028 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12028 is
still busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12028 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the ISL12028 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next read
operation would access data from address n + 1. On power-up,
FN8233.10
August 14, 2015
ISL12028, ISL12028A
the sixteen bit address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the first
location. Upon receipt of the Slave Address Byte with the R/W
bit set to one, the ISL12028 issues an acknowledge, then
transmits eight data bits. The master terminates the read
operation by not responding with an acknowledge during the
ninth clock and issuing a stop condition. Refer to Figure 23 for
the address, acknowledge, and data transfer sequence.
SIGNALS FROM
THE MASTER
SDA BUS
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
1
1 1 1 1
A
C
K
SIGNALS FROM
THE SLAVE
DATA
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
ISSUE START
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
RANDOM READ
Random read operations allow the master to access any
location in the ISL12028. Prior to issuing the Slave Address
Byte with the R/W bit set to zero, the master must first
perform a “dummy” write operation.
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word
address bytes. After acknowledging receipt of each word
address byte, the master immediately issues another start
condition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the 8-bit data word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. Refer to Figure 25 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 25. The ISL12028 then goes
into standby mode after the stop and all bus activity will be
ignored until a start is detected. This operation loads the new
address into the address counter. The next Current Address
Read operation will read from the newly loaded address.
This operation could be useful if the master knows the next
address it needs to read, but is not ready for the data.
SEQUENTIAL READ
ISSUE MEMORY ARRAY SLAVE
ADDRESS BYTE
AFH (READ) OR AEH (WRITE)
ISSUE STOP
NO
ACK
RETURNED?
YES
NO
NON-VOLATILE WRITE
CYCLE COMPLETE. CONTINUE
COMMAND SEQUENCE?
ISSUE STOP
YES
CONTINUE
NORMAL READ OR
WRITE COMMAND
SEQUENCE
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space, the counter “rolls over” to the start of the
address space and the ISL12028 continues to output data
for each acknowledge received. Refer to Figure 26 for the
acknowledge and data transfer sequence.
PROCEED
FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
21
FN8233.10
August 14, 2015
ISL12028, ISL12028A
S
T
A
R
T
SIGNALS FROM
THE MASTER
SDA BUS
SLAVE
ADDRESS
1
A
C
K
S
T
O
P
SLAVE
ADDRESS
1 1 11
1
00 00000
A
C
K
SIGNALS FROM
THE SLAVE
WORD
ADDRESS 0
WORD
ADDRESS 1
1 1 1 0
S
T
A
R
T
A
C
K
A
C
K
DATA
FIGURE 25. RANDOM ADDRESS READ SEQUENCE
SLAVE
ADDRESS
SIGNALS FROM
THE MASTER
SDA BUS
S
T
O
P
A
C
K
A
C
K
A
C
K
1
A
C
K
SIGNALS FROM
THE SLAVE
DATA
(1)
DATA
(2)
DATA
(n - 1)
DATA
(n)
(n IS ANY INTEGER GREATER THAN 1)
FIGURE 26. SEQUENTIAL READ SEQUENCE
Application Section
Crystal Oscillator and Temperature Compensation
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external
components and adjust for crystal drift over-temperature and
enable very high accuracy time keeping (<5ppm drift).
The Intersil RTC family uses an oscillator circuit with on-chip
crystal compensation network, including adjustable
load-capacitance. The only external component required is
the crystal. The compensation network is optimized for
operation with certain crystal parameters which are common
in many of the surface mount or tuning-fork crystals available
today. Table 9 summarizes these parameters.
Table 10 contains some crystal manufacturers and part
numbers that meet the requirements for the Intersil RTC
products.
has 6-bits of control. The load capacitance range covered by
the ATR circuit is approximately 3.25pF to 18.75pF, in
0.25pF increments. Note that actual capacitance would also
include about 2pF of package related capacitance. In-circuit
tests with commercially available crystals demonstrate that
this range of capacitance allows frequency control from
+116ppm to -37ppm, using a 12.5pF load crystal.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation feature
is available for the Intersil RTC family. There are three bits
known as the Digital Trimming Register or DTR, and they
operate by adding or skipping pulses in the clock signal. The
range provided is ±30ppm in increments of 10ppm. The
default setting is 0ppm. The DTR control can be used for
coarse adjustments of frequency drift over-temperature or
for crystal initial accuracy correction.
The turnover-temperature in Table 9 describes the
temperature where the apex of the of the drift vs temperature
curve occurs. This curve is parabolic with the drift increasing
as (T-T0)2. For an Epson MC-405 device, for example, the
turnover-temperature is typically +25°C, and a peak drift of
>110ppm occurs at the temperature extremes of -40 and
+85°C. It is possible to address this variable drift by adjusting
the load capacitance of the crystal, which will result in
predictable change to the crystal frequency. The Intersil RTC
family allows this adjustment over-temperature since the
devices include on-chip load capacitor trimming. This control
is handled by the Analog Trimming Register, or ATR, which
22
FN8233.10
August 14, 2015
ISL12028, ISL12028A
TABLE 9. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC
PARAMETER
MIN
Frequency
TYP
MAX
32.768
Frequency Tolerance
Turnover-Temperature
20
25
Operating Temperature Range
-40
Parallel Load Capacitance
NOTES
kHz
±100
ppm
30
°C
85
°C
12.5
Equivalent Series Resistance
UNITS
Down to 20ppm if desired
Typically the value used for most crystals
pF
50
k
For best oscillator performance
TABLE 10. CRYSTAL MANUFACTURERS
MANUFACTURER
PART NUMBER
TEMP RANGE
(°C)
+25°C FREQUENCY
TOLERANCE
(ppm)
Citizen
CM201, CM202, CM200S
-40 to +85
±20
Epson
MC-405, MC-406
-40 to +85
±20
Raltron
RSM-200S-A or B
-40 to +85
±20
SaRonix
32S12A or B
-40 to +85
±20
Ecliptek
ECPSM29T-32.768K
-10 to +60
±20
ECS
ECX-306/ECX-306I
-10 to +60
±20
Fox
FSM-327
-40 to +85
±20
A final application for the ATR control is in-circuit calibration
for high accuracy applications, along with a temperature
sensor chip. Once the RTC circuit is powered up with battery
backup, the IRQ/FOUT output is set at 32.768kHz and
frequency drift is measured. The ATR control is then
adjusted to a setting which minimizes drift. Once adjusted at
a particular temperature, it is possible to adjust at other
discrete temperatures for minimal overall drift, and store the
resulting settings in the EEPROM. Extremely low overall
temperature drift is possible with this method. The Intersil
evaluation board contains the circuitry necessary to
implement this control.
.
C1
C1
0.1µF
0.1µF
XTAL1
XTAL1
32.768kHz
32.768kGz
R1
10k
R1 10k
U1
U1
ISL12028
X1228
FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-14
Layout Considerations
The crystal input at X1 has a very high impedance and will
pick up high frequency signals from other circuits on the
board. Since the X2 pin is tied to the other side of the crystal,
it is also a sensitive node. These signals can couple into the
oscillator circuit and produce double clocking or misclocking,
seriously affecting the accuracy of the RTC. Care needs to
be taken in layout of the RTC circuit to avoid noise pickup.
Figure 27 shows a suggested layout for the ISL12029 or
ISL12028 devices (R1 is not needed for the ISL12028).
23
FN8233.10
August 14, 2015
ISL12028, ISL12028A
The X1 and X2 connections to the crystal are to be kept as
short as possible. A thick ground trace around the crystal is
advised to minimize noise intrusion, but ground near the X1
and X2 pins should be avoided as it will add to the load
capacitance at those pins. Keep in mind these guidelines for
other PCB layers in the vicinity of the RTC device. A small
decoupling capacitor at the VDD pin of the chip is mandatory,
with a solid connection to ground.
For other RTC products, the same rules stated previously
should be observed, but adjusted slightly since the packages
and pinouts are slightly different.
Oscillator Measurements
When a proper crystal is selected and the layout guidelines
above are observed, the oscillator should start up in most
circuits in less than one second. Some circuits may take
slightly longer, but startup should definitely occur in less than
5 seconds. When testing RTC circuits, the most common
impulse is to apply a scope probe to the circuit at the X2 pin
(oscillator output) and observe the waveform. DO NOT DO
THIS! Although in some cases you may see a usable
waveform, due to the parasitics (usually 10pF to ground)
applied with the scope probe, there will be no useful
information in that waveform other than the fact that the
circuit is oscillating. The X2 output is sensitive to capacitive
impedance so the voltage levels and the frequency will be
affected by the parasitic elements in the scope probe.
Applying a scope probe can possibly cause a faulty oscillator
to start up, hiding other issues (although in the Intersil
RTC’s, the internal circuitry assures startup when using the
proper crystal and layout).
The best way to analyze the RTC circuit is to power it up and
read the real time clock as time advances, or if the chip has
the IRQ/FOUT output, look at the output of that pin on an
oscilloscope (after enabling it with the control register, and
using a pull-up resistor for the open-drain output).
Alternatively, the ISL12028 IRQ/FOUT- output can be
checked by setting an alarm for each minute. Using the
pulse interrupt mode setting, the once-per-minute interrupt
functions as an indication of proper oscillation.
TABLE 11. I2C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (SHADED ROW IS SAME AS X1228 OPERATION)
VBAT
SWITCHOVER
VOLTAGE
I2C ACTIVE IN
BATTERY
BACKUP?
EE PROM WRITE/
READ IN BATTERY
BACKUP?
IRQ/FREQ
ACTIVE?
0
Standard Mode,
VTRIP = 2.2V typ,
Default for
ISL12028A
NO
NO
YES
Operation of I2C bus down to
VDD = VRESET, then below that no
communications. Battery switchover
at VTRIP.
0
1
Legacy Mode,
VDD < VBAT
Default for
ISL12028,
YES, only if
VBAT > VRESET
YES, read only
YES
Operation of I2C bus into battery
backup mode, but only for
VBAT>VDD>VRESET.
Bus must have pull-ups to VBAT. No
nonvolatile writes with VBAT>VDD
C
1
0
Standard Mode,
VTRIP = 2.2V typ
NO
NO
YES
Operation of I2C bus down to
VDD = VRESET, then below that no
communications. Battery switchover
at VTRIP.
D
1
1
Legacy Mode,
VDD < VBAT
NO
NO
YES
Operation of I2C bus down to VRESET
or VBAT, whichever is higher.
MODE
SBIB
BIT
BSW
BIT
A
0
B
(X1228
mode)
24
NOTES
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Backup Battery Operation
Many types of batteries can be used with the Intersil RTC
products. 3.0V or 3.6V Lithium batteries are appropriate, and
sizes are available that can power a Intersil RTC device for up
to 10 years. Another option is to use a supercapacitor for
applications where VDD may disappear intermittently for short
periods of time. Depending on the value of supercapacitor
used, backup time can last from a few days to two weeks (with
>1F). A simple silicon or Schottky barrier diode can be used in
series with VDD to charge the supercapacitor, which is
connected to the VBAT pin. Try to use Schottky diodes with
very low leakages, <1µA desirable. Do not use the diode to
charge a battery (especially lithium batteries!).
Note that whether a battery or supercap is used, if the VBAT
voltage drops below the data sheet minimum of 1.8V and the
VDD power cycles to 0V then back to VDD voltage, then the
RESET output may stay low and the I2C communications will
not operate. The VBAT and VDD power will need to be cycled
to 0V together to allow normal operation again.
There are two possible modes for battery backup operation,
Standard and Legacy mode. In Standard mode, there are no
operational concerns when switching over to battery backup
since all other devices functions are disabled. Battery drain
is minimal in Standard mode, and return to Normal VDD
powered operations predictable. In Legacy modes the VBAT
pin can power the chip if the voltage is above VDD and
VTRIP. This makes it possible to generate alarms and
communicate with the device under battery backup, but the
supply current drain is much higher than the Standard mode
and backup time is reduced. In this case if alarms are used
in backup mode, the IRQ/FOUT pull up resistor must be
connected to VBAT voltage source..
2.7V TO 5.5V
VDD
VBAT
SUPERCAPACITOR
VSS
FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT
25
I2C Communications During Battery Backup and
LVR Operation
Operation in Battery Backup mode and LVR is affected by
the BSW and SBIB bits as described earlier. These bits allow
flexible operation of the serial bus and EEPROM in battery
backup mode, but certain operational details need to be
clear before utilizing the different modes. The most
significant detail is that once VDD goes below VRESET, then
I2C communications cease regardless of whether the device
is programmed for I2C operation in battery backup mode.
Table 11 describes 4 different modes possible with using the
BSW and SBIB bits, and how they are affect LVR and battery
backup operation.
• Mode A - In this mode, selection bits indicate a low VDD
switchover combined with I2C operation in battery backup
mode. In actuality the VDD will go below VRESET before
switching to battery backup, which will disable I2C
ANYTIME the device goes into battery backup mode.
Regardless of the battery voltage, the I2C will work down
to the VRESET voltage (see Figure 29).
• Mode B - In this mode, the selection bits indicate
switchover to battery backup at VDD<VBAT, and I2C
communications in battery backup. In order to
communicate in battery backup mode, the VRESET voltage
must be less than the VBAT voltage AND VDD must be
greater than VRESET. Also, pull-ups on the I2C-bus pins
must go to VBAT to communicate. This mode is the same
as the normal operating mode of the X1228 device
• Mode C - In this mode, the selection bits indicate a low
VDD switchover combined with no communications in
battery backup. Operation is actually identical to Mode A
with I2C communications down to VDD = VRESET, then no
communications (see Figure 29).
• Mode D - In this mode, the selection bits indicate
switchover to battery backup at VDD<VBAT, and no I2C
communications in battery backup. This mode is unique in
that there is I2C communication as long as VDD is higher
than VRESET or VBAT, whichever is greater. This mode is
the safest for guaranteeing I2C communications only when
there is a Valid VDD (see Figure 30).
Note that the IRQ/FOUT CMOS output pin is active in battery
backup for all modes. This should be considered if the load
on this pin is powered down, and could draw current from
the PMOS transistor and drain the battery. If that is the case,
the designer should consider the ISL12029 device which has
an open-drain output and avoids excessive current draw in
battery backup.
FN8233.10
August 14, 2015
ISL12028, ISL12028A
.
VBAT(3.0V)
VDD
VRESET(2.63V)
VTRIP
(2.2V)
tPURST
RESET
I2C-BUS ACTIVE
IBAT
(BATTERY BACKUP MODE)
(VDD POWER, VBAT NOT CONNECTED)
FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C
VBAT (3.0V)
VDD
VRESET (2.63V)
VTRIP
(2.2V)
tPURST
RESET
I2C-BUS ACTIVE
IBAT
(BATTERY BACKUP MODE)
FIGURE 30. RESET OPERATION IN MODE D
Alarm Operation Examples
Following, are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm 0 set with single interrupt (IM = ”0”)
ALARM0
REGISTER 7
BIT
6
5
4
3
2
1
0
HEX
MOA0
1
0
0
0
0
0
0
1
81h Month set to 1,
enabled
DWA0
0
0
0
0
0
0
0
0
00h Day of week
disabled
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm 0 registers as follows:
ALARM0
REGISTER 7
B. Also the AL0E bit must be set as follows:
BIT
6
5
4
3
2
1
0
HEX
DESCRIPTION
SCA0
0
0
0
0
0
0
0
0
00h Seconds disabled
MNA0
1
0
1
1
0
0
0
0
B0h Minutes set to 30,
enabled
HRA0
1
0
0
1
0
0
0
1
91h Hours set to 11,
enabled
DTA0
1
0
0
0
0
0
0
1
81h Date set to 1,
enabled
26
DESCRIPTION
CONTROL
REGISTER 7
INT
0
BIT
6
5
4
3
2
1
0
HEX
0
1
0
0
0
0
0
x0h
DESCRIPTION
Enable Alarm
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/FOUT output
low.
FN8233.10
August 14, 2015
ISL12028, ISL12028A
EXAMPLE 2
B. Set the Interrupt register as follows:
Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30s.
A. Set Alarm 0 registers as follows:
BIT
ALARM0
REGISTER 7 6 5 4 3 2 1 0 HEX
BIT
CONTROL
REGISTER 7 6 5 4 3 2 1 0 HEX
INT
DESCRIPTION
1 0 1 x x 0 0 0 x0h Enable Alarm and Int
Mode
XX indicate other control bits.
DESCRIPTION
SCA0
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA0
0 0 0 0 0 0 0 0 00h Minutes disabled
HRA0
0 0 0 0 0 0 0 0 00h Hours disabled
DTA0
0 0 0 0 0 0 0 0 00h Date disabled
MOA0
0 0 0 0 0 0 0 0 00h Month disabled
DWA0
0 0 0 0 0 0 0 0 00h Day of week disabled
Once the registers are set, the following waveform will be
seen at IRQ/FOUT-:
RTC AND ALARM REGISTERS ARE BOTH 30s
60s
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 14, 2015
FN8233.10
CHANGE
Added Revision History beginning with Rev 10.
Added About Intersil Verbiage.
Updated Ordering Information Table on page 2
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
27
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 identifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
28
FN8233.10
August 14, 2015
ISL12028, ISL12028A
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
29
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN8233.10
August 14, 2015