DATASHEET

EL7535
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December 9, 2015
FN7003.7
Monolithic 350mA Step-Down Regulator
Features
The EL7535 is a synchronous, integrated FET 350mA
step-down regulator in a 10 Ld MSOP package. The regulator
is internally compensated, which makes it possible to use just
five tiny external components to form a complete DC/DC
converter. The regulator operates with an input voltage range
from 2.5V to 6V, which accommodates supplies of 3.3V, 5V, or
a Li-Ion battery source. The output can be externally set from
0.8V to VIN with a resistive divider.
• Extremely Small 350mA DC/DC Converter
• Pb-free Available (RoHS compliant)
Applications
• PDA and Pocket PC Computers
• Bar Code Readers
PACKAGE
BAACA
• Internally-Compensated Voltage Mode Controller
• Overcurrent and Over-Temperature Protection
Ordering Information
EL7535IYZ*
(Note)
• Power-On-Reset Output (POR)
• <1µA Shut-Down Current
The EL7535 is available in the 10 Ld MSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.
PART
MARKING
• Possibly Uses Only Five Tiny External Components with
Fixed Output
• Up to 94% Efficiency
The EL7535 features PWM mode control. The operating
frequency is typically 1.4MHz. Additional features include
<1µA shut-down current, short-circuit protection, and
over-temperature protection.
PART
NUMBER
• Max Height 1.1mm 10 Ld MSOP Package
10 Ld MSOP
(Pb-free)
PKG.
DWG. #
• Cellular Phones
• Portable Test Equipment
MDP0043
• Li-Ion Battery Powered Devices
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
• Small Form Factor (SFP) Modules
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Typical Application Diagram
VS
VIN
R3 100
C2
10µF
LX
1.8µH
C1
10µF
VDD
C3
0.1µF
VO
L1
(2.5V TO 5.5V)
EL7535
Pinout
EL7535
(10 LD MSOP)
TOP VIEW
1 SGND
FB 10
2 PGND
VO 9
3 LX
R5 100k
R1*
124k
POR
EN
R4 100k
R6
100k
FB
RSI
PGND
SGND
R2*
100k
VO
C4
470pF
(1.8V @ 350mA)
POR 8
4 VIN
EN 7
5 VDD
RSI 6
1
*VO = 0.8V*(1 + R1/R2)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2004-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7535
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VIN, VDD, POR to SGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
RSI, EN, VO, FB to SGND . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
780
800
820
mV
250
nA
2.5
6
V
VIN rising
2.19
2.42
V
Hysterisis
100
300
mV
DC CHARACTERISTICS
VFB
Feedback Input Voltage
IFB
Feedback Input Current
VIN, VDD
Input Voltage
VIN,ON
Maximum Voltage for Startup
IDD
Supply Current
PWM, VIN = VDD = 5V
400
850
µA
EN = 0, VIN = VDD = 5V
0.1
1.5
µA
rDS(ON)-PMOS
PMOS FET Resistance
VDD = 5V, wafer test only
70
100
m
rDS(ON)-NMOS
NMOS FET Resistance
VDD = 5V, wafer test only
45
75
m
ILMAX
Current Limit
TOT,OFF
Over-temperature Threshold
TOT,ON
1.5
A
T rising
145
°C
Over-temperature Hysteresis
T falling
130
°C
IEN, IRSI
EN, RSI Current
VEN, VRSI = 0V and 3.3V
VEN1, VRSI1
EN, RSI Rising Threshold
VDD = 3.3V
VEN2, VRSI2
EN, RSI Falling Threshold
VDD = 3.3V
VPOR
Minimum VFB for POR, WRT Targeted
VFB Value
VFB rising
POR Voltage Drop
ISINK = 5mA
VOLPOR
VFB falling
-1
1
µA
2.4
V
0.8
V
97
86
%
%
35
70
mV
1.4
1.6
MHz
25
50
ns
AC CHARACTERISTICS
fPWM
PWM Switching Frequency
tRSI
Minimum RSI Pulse Width
tSS
Soft-start Time
650
µs
tPOR
Power-On Reset Delay Time
100
ms
2
1.1
Limits established by characterization and
are not production tested
FN7003.7
December 9, 2015
EL7535
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
SGND
Negative supply for the controller stage
2
PGND
Negative supply for the power stage
3
LX
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
5
VDD
Power supply for the controller stage
6
RSI
Resets POR timer
7
EN
Enable
8
POR
9
VO
Output voltage sense
10
FB
Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output
Power on reset open drain output
Timing Diagram
VO
MIN
25ns
RSI
100ms
100ms
POR
3
FN7003.7
December 9, 2015
EL7535
Block Diagram
VDD
VO
+
-
10pF
124k
FB
5M
+
CURRENT
LIMIT
PWM
COMPENSATION
100k
CLOCK
1.4MHz
VIN
+
PWM
COMPARATOR
P-DRIVER
LX
CONTROL
LOGIC
RAMP
GENERATOR
1.8µH
1.8V
350mA
EN
EN
SOFTSTART
10µF
10µF
N-DRIVER
5V
+
–
BANDGAP
REFERENCE
UNDERVOLTAGE
LOCKOUT
PGND
100k
TEMPERATURE
SENSE
SGND
POR
PG
POR
RSI
4
FN7003.7
December 9, 2015
EL7535
Typical Performance Curves
100
100
VIN = 5V
95
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 350mA with component values shown on
page 1, unless otherwise noted.
VO = 3.3V
VO = 2.5V
90
EFFICIENCY (%)
90
EFFICIENCY (%)
VIN = 3.3V
95
85
80
VO = 1.8V
VO = 2.5V
75
VO = 1.2V
70
85
VO = 1.8V
80
75
VO = 1V
70
65
65
60
60
100
0
300
200
400
100
0
IO (mA)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.5
100
125
150
0.50
/W
°C
75 85
50
0
25
15
0
+1
0
P1
0.1
=
0.2
0.70
0.60
SO
0.3
SO
P1
+2
0
06
°C
/W
0.80
M
M
=
0.90
A
JA
1.00
J
ALLOWABLE POWER DISSIPATION (W)
0.6

0.40
0.30
0.20
0.10
0
0
25
50
75 85
100
FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
VIN
(2V/DIV)
VO
(2V/DIV)
IIN
(0.2A/DIV)
POR
(2V/DIV)
VO
(1V/DIV)
0.5ms/DIV
150
FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
VIN
(1V/DIV)
FIGURE 5. START-UP 1
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
5
400
FIGURE 2. EFFICIENCY
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.4
300
200
IO (mA)
FIGURE 1. EFFICIENCY
ALLOWABLE POWER DISSIPATION (W)
VO = 1.2V
50ms/DIV
FIGURE 6. START-UP 2
FN7003.7
December 9, 2015
EL7535
Typical Performance Curves
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 350mA with component values shown on
page 1, unless otherwise noted. (Continued)
VIN
(2V/DIV)
VO
(2V/DIV)
350mA
100mA
IO
RSI
(2V/DIV)
VO
20mV/DIV
POR
(2V/DIV)
0.2ms/DIV
50ms/DIV
FIGURE 7. POR FUNCTION
FIGURE 8. TRANSIENT RESPONSE
VIN
100mV/DIV
0.5A/DIV
iL
VLX
2V/DIV
VO
10mV/DIV
1µs/DIV
FIGURE 9. STEADY-STATE
6
FN7003.7
December 9, 2015
EL7535
Applications Information
Product Description
The EL7535 is a synchronous, integrated FET 350mA
step-down regulator which operates from an input of 2.5V to
6V. The output voltage is user-adjustable with a pair of
external resistors.
The internally-compensated controller makes it possible to
use only two ceramic capacitors and one inductor to form a
complete, very small footprint 350mA DC/DC converter.
The POR output also serves as a 100ms delayed Power
Good signal when the pull-up resistor R4 is installed. The
RSI pin needs to be directly (or indirectly through a resistor
R6) connected to Ground for this to function properly.
Output Voltage Selection
Users can set the output voltage of the converter with a
resistor divider, which can be chosen based on Equation 1:
R 1

V O = 0.8   1 + -------
R 2

(EQ. 1)
PWM Operation
Component Selection
In the PWM mode, the P-Channel MOSFET and N-Channel
MOSFET always operate complementary. When the
PMOSFET is on and the NMOSFET off, the inductor current
increases linearly. The input energy is transferred to the
output and also stored in the inductor. When the P-Channel
MOSFET is off and the N-Channel MOSFET on, the inductor
current decreases linearly and energy is transferred from the
inductor to the output. Hence, the average current through
the inductor is the output current. Since the inductor and the
output capacitor act as a low pass filter, the duty cycle ratio
is approximately equal to VO divided by VIN.
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
We recommend 10µF to 22µF multi-layer ceramic capacitors
with X5R or X7R rating for both the input and output
capacitors, and 1.5µH to 2.2µH inductance for the inductor.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 22µF ceramic. The
inductor is nominally 1.8µH, though 1.5µA to 2.2µH can be
used.
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The RMS current present at the input capacitor is decided by
Equation 2:
V IN   V IN - V O 
I INRMS = -------------------------------------------------  I O
V IN
(EQ. 2)
The inductor peak-to-peak ripple current is given as
Equation 3:
 V IN - V O   V O
I IL = -------------------------------------------L  V IN  f S
(EQ. 3)
• L is the inductance
Start-Up and Shut-Down
When the EN pin is tied to VIN, and VIN reaches
approximately 2.4V, the regulator begins to switch. The
output voltage is gradually increased to ensure proper
soft-start operation.
When the EN pin is connected to a logic low, the EL7535 is
in the shut-down mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 1µA.
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
RSI/POR Function
When powering up, the open-collector Power-On-Reset
output holds low for about 100ms after VO reaches the
preset voltage. When the active-HI reset signal RSI is
issued, POR goes to low immediately and holds for the
same period of time after RSI comes back to LOW. The
output voltage is unaffected. (Please refer to “Timing
Diagram” on page 3). When the function is not used, connect
RSI to ground and leave open the pull-up resistor R4 at POR
pin.
7
• fS is the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 1.5A surge current that can occur during a
current limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow Equation 4:
1
f Z = ---------------------2R 2 C 4
(EQ. 4)
Over a normal range of R2 (~10k to100k), C4 will range
from ~470pF to 4700pF. The pole frequency cannot be set
once the zero frequency is chosen as it is dictated by the
ratio of R1 and R2, which is solely determined by the desired
FN7003.7
December 9, 2015
EL7535
output set point. Equation 5 shows the pole frequency
relationship:
1
f P = --------------------------------------2  R 1 R 2 C 4
(EQ. 5)
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
Thermal Shut-Down
Once the junction reaches about +145°C, the regulator shuts
down. Both the P-Channel and the N-Channel MOSFETs
turn off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about +130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
• Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the pins
• Place the input capacitor as close to VIN and PGND pins
as possible
• Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
• If used, connect the trace from the FB pin to R1 and R2 as
close as possible
• Maximize the copper area around the PGND pin
• Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7535 Application Note.
Thermal Performance
The EL7535 is in a fused-lead 10 Ld MSOP package.
Compared with regular 10 Ld MSOP package, the fused-lead
package provides lower thermal resistance. The JA is
+100°C/W on a 4-layer board and +125°C/W on 2-layer
board. Maximizing the copper area around the pins will further
improve the thermal performance.
8
FN7003.7
December 9, 2015
EL7535
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
December 9, 2015
FN7003.7
CHANGE
Updated the Ordering Information table on page 1.
Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
9
FN7003.7
December 9, 2015
EL7535
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
0.08 M C A B
b
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN7003.7
December 9, 2015
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