DATASHEET

EL7530
I GNS
D ES
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UCT
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E D F E P ROD
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106
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COM SUBSTI IN) ISL9 Data Sheet
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July 12, 2006
Monolithic 600mA Step-Down Regulator
with Low Quiescent Current
FN7434.6
Features
The EL7530 is a synchronous, integrated FET 600mA stepdown regulator with internal compensation. It operates with an
input voltage range from 2.5V to 5.5V, which accommodates
supplies of 3.3V, 5V, or a Li-Ion battery source. The output can
be externally set from 0.8V to VIN with a resistive divider.
The EL7530 features automatic PFM/PWM mode control, or
PWM mode only. The PWM frequency is typically 1.4MHz
and can be synchronized up to 12MHz. The typical no load
quiescent current is only 120µA. Additional features include
a Power-Good output, <1µA shut-down current, short-circuit
protection, and over-temperature protection.
• Less than 0.18in2 footprint for the complete 600mA
converter
• Components on one side of PCB
• Max height 1.1mm MSOP10
• Power-Good (PG) output
• Internally-compensated voltage mode controller
• Up to 95% efficiency
• <1µA shut-down current
• 120µA quiescent current
• Overcurrent and over-temperature protection
The EL7530 is available in the 10 Ld MSOP package,
making the entire converter occupy less than 0.18n2 of PCB
area with components on one side only. The 10 Ld MSOP
package is specified for operation over the full -40°C to
+85°C temperature range.
Ordering Information
• External synchronizable up to 12MHz
• Pb-free plus anneal available (RoHS compliant)
Applications
• PDA and pocket PC computers
PART
TAPE &
PART NUMBER MARKING REEL
PACKAGE
PKG.
DWG. #
• Bar code readers
• Cellular phones
EL7530IY
BYAAA
-
10 Ld MSOP
MDP0043
EL7530IY-T7
BYAAA
7”
10 Ld MSOP
MDP0043
• Portable test equipment
EL7530IY-T13
BYAAA
13”
10 Ld MSOP
MDP0043
• Li-Ion battery powered devices
EL7530IYZ
(Note)
BAADA
-
10 Ld MSOP
(Pb-free)
MDP0043
• Small form factor (SFP) modules
EL7530IYZ-T7
(Note)
BAADA
7”
10 Ld MSOP
(Pb-free)
MDP0043
Typical Application Diagram
EL7530IYZ-T13
(Note)
BAADA
13”
10 Ld MSOP
(Pb-free)
MDP0043
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
EL7530
TOP VIEW
VS
VIN
LX
R3 100Ω
C3
0.1µF
EL7530
R5 100kΩ
R1
124kΩ
PG
Pinout
EN
EL7530 (10 LD MSOP)
TOP VIEW
1 SGND
FB 10
2 PGND
VO 9
3 LX
PG 8
4 VIN
EN 7
5 VDD
R4 100kΩ
R6
100kΩ
1.8µH
C1
10µF
VDD
C2
10µF
VO
L1
(2.5V to 5.5V)
FB
SYNC
PGND
SGND
C4
470pF
R2*
100kΩ
VO
(1.8V @ 600mA)
* VO = 0.8V * (1 + R1 / R2)
SYNC 6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
Absolute Maximum Ratings (TA = 25°C)
Thermal Information
VIN, VDD, PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
SYNC, EN, VO, FB to SGND . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mA
Thermal Resistance (Typical)
θJA (°C/W)
MSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . . .
115
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
PARAMETER
VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V (as shown in Typical Application Diagram),
unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
790
800
810
mV
100
nA
2.5
5.5
V
DC CHARACTERISTICS
VFB
Feedback Input Voltage
IFB
Feedback Input Current
VIN, VDD
Input Voltage
VIN,OFF
Minimum Voltage for Shutdown
VIN falling
2
2.2
V
VIN,ON
Maximum Voltage for Startup
VIN rising
2.2
2.4
V
IS
Input Supply Quiescent Current
PWM Mode
Active - PFM Mode
VSYNC = 0V
120
145
µA
Active - PWM Mode
VSYNC = 3.3V
6.5
7.5
mA
Supply Current
PWM, VIN = VDD = 5V
400
500
µA
EN = 0, VIN = VDD = 5V
0.1
1
µA
PMOS FET Resistance
VDD = 5V, wafer test only
70
100
mΩ
RDS(ON)-NMOS NMOS FET Resistance
VDD = 5V, wafer test only
45
75
mΩ
IDD
RDS(ON)-PMOS
ILMAX
Current Limit
TOT,OFF
Over-temperature Threshold
TOT,ON
1.2
A
T rising
145
°C
Over-temperature Hysteresis
T falling
130
°C
IEN, ISYNC
EN, SYNC Current
VEN, VRSI = 0V and 3.3V
VEN1, VSYNC1
EN, SYNC Rising Threshold
VDD = 3.3V
VEN2, VSYNC2
EN, SYNC Falling Threshold
VDD = 3.3V
VPG
Minimum VFB for PG, WRT Targeted
VFB Value
VFB rising
PG Voltage Drop
ISINK = 3.3mA
VOLPG
VFB falling
-1
1
µA
2.4
V
0.8
V
95
86
%
%
35
70
mV
1.4
1.6
MHz
AC CHARACTERISTICS
FPWM
PWM Switching Frequency
tSYNC
Minimum SYNC Pulse Width
tSS
Soft-start Time
1.25
Guaranteed by design
25
ns
650
2
µs
FN7434.6
July 12, 2006
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
SGND
Negative supply for the controller stage
2
PGND
Negative supply for the power stage
3
LX
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
5
VDD
Power supply for the controller stage
6
SYNC
7
EN
Enable
8
PG
Power-Good open drain output
9
VO
Output voltage sense
10
FB
Voltage feedback input; connected to an external resistor divider between VO and SGND for variable
output
SYNC input pin; when connected to HI, regulator runs at forced PWM mode; when connected to Low, auto
PFM/PWM mode; when connected to external sync signal, at external PWM frequency up to 12MHz
Block Diagram
100Ω
0.1µF
VDD
INDUCTOR SHORT
VO
+
CURRENT
SENSE
10pF
C4 124K
470pF
FB
5M
+
PWM
COMPENSATION
100K
SYNC
SYNC
CLOCK
RAMP
GENERATOR
EN
EN
SOFTSTART
10µF
BANDGAP
REFERENCE
5V +
–
SGND
+
PWM
COMPARATOR
PFM
ON-TIME
CONTROL
+
PWM
COMPARATOR
UNDERVOLTAGE
LOCKOUT
VIN
P-DRIVER
LX
CONTROL
LOGIC
1.8µH
1.8V
0 TO 600mA
10µF
N-DRIVER
PGND
TEMPERATURE
SENSE
+
SYNCHRONOUS
RECTIFIER
100K
PG
PG
POWER
GOOD
3
FN7434.6
July 12, 2006
Performance Curves and Waveforms
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
100
90
VO=2.5V
90
85
80
75
VO=1.8V
VO=1.5V
70
VO=1.0V
65
VO=0.8V
60
VO=2.5V
70
VO=1.8V
60
VO=1.5V
50
VO=1.2V
40
VO=1.0V
30
VO=1.2V
55
VO=3.3V
80
EFFICIENCY (%)
EFFICIENCY (%)
100
VO=3.3V
95
VO=0.8V
20
50
45
10
VIN=5V
40
1
10
100
VIN=5V
0
600
1
10
100
IO (mA)
FIGURE 1. EFFICIENCY vs IO (PFM/PWM MODE)
FIGURE 2. EFFICIENCY vs IO (PWM MODE)
100
100
VO=2.5V
VO=1.8V
95
VO=2.5V
90
VO=1.8V
80
85
80
EFFICIENCY (%)
EFFICIENCY (%)
90
VO=1.5V
VO=1.2V
VO=1.0V
75
70
65
VO=0.8V
60
55
VO=1.5V
70
VO=1.2V
60
VO=1.0V
50
40
30
20
50
VO=0.8V
10
45
VIN=3.3V
1
10
100
VIN=3.3V
0
40
1
600
10
FIGURE 3. EFFICIENCY vs IO (PFM/FWM MODE)
1.44
0.1%
VIN=5V IO=0A
0.0%
VO CHANGES
1.42
1.4
VIN=3.3V IO=0A
1.38
1.36
1.34
1.32
-50
600
FIGURE 4. EFFICIENCY vs IO (PWM MODE)
VIN=3.3V IO=600mA
VIN=5V IO=600mA
100
IO (mA)
IO (mA)
FS (MHz)
600
IO (mA)
-0.1%
VIN=3.3V
-0.2%
VIN=5V
-0.3%
-0.4%
-0.5%
0
50
100
150
TA (°C)
FIGURE 5. FS vs JUNCTION TEMPERATURE (PWM MODE)
4
0
0.2
0.4
0.6
0.8
1
IO (A)
FIGURE 6. LOAD REGULATIONS (PWM MODE)
FN7434.6
July 12, 2006
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
0.1%
12
0.0%
VIN=5V IO=0A
-0.1%
8
-0.2%
IS (mA)
VO CHANGES
10
VIN=3.3V IO=0A
VIN=3.3V IO=600mA
-0.3%
-0.4%
6
4
-0.5%
-0.6%
2
VIN=5V IO=600mA
-0.7%
-50
0
50
100
0
150
2.5
3
3.5
TJ (°C)
4
4.5
5
VS (V)
FIGURE 7. PWM MODE LOAD/LINE REGULATIONS vs
JUNCTION TEMPERATURE
FIGURE 8. NO LOAD QUIESCENT CURRENT (PWM MODE)
140
130
VO=1.8V
VO=3.3V
120
IS (µA)
110
100
90
VO=1.5V
VO=1.2V VO=1.0V
VO=0.8V
80
70
60
50
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VS (V)
FIGURE 9. NO LOAD QUIESCENT CURRENT (PFM MODE)
2
1
VIN
(2V/DIV
EN
IIN
(0.25A/DIV)
IIN
(0.25A/DIV)
VO
(2V/DIV
VO
(2V/DIV)
PG
PG
200µs/DIV
FIGURE 10. START-UP AT IO = 600mA
5
500µs/DIV
FIGURE 11. ENABLE AND SHUT-DOWN
FN7434.6
July 12, 2006
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
LX
(2V/DIV
LX
(2V/DIV
IL
(0.5A/DIV)
IL
(0.5A/DIV)
ΔVO
(10mV/DIV)
ΔVO
(50mV/DIV)
0.5µs/DIV
2µs/DIV
FIGURE 12. PFM STEADY-STATE OPERATION WAVEFORM
(IO = 100mA)
FIGURE 13. PWM STEADY-STATE OPERATION (IO = 600mA)
SYNC
(2V/DIV
SYNC
(2V/DIV
LX
(2V/DIV)
IL
(0.5A/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
20ns/DIV
0.2µs/DIV
FIGURE 14. EXTERNAL SYNCHRONIZATION TO 2MHz
FIGURE 15. EXTERNAL SYNCHRONIZATION TO 12MHz
IO
(200mA/DIV)
IO
(200mA/DIV)
ΔVO
(100mV/DIV)
ΔVO
(100mV/DIV)
100µs/DIV
FIGURE 16. LOAD TRANSIENT RESPONSE (22mA TO 600mA)
6
50µs/DIV
FIGURE 17. PWM LOAD TRANSIENT RESPONSE (30mA TO
600mA)
FN7434.6
July 12, 2006
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
100
1.4MHz
IO
(200mA/DIV)
EFFICIENCY (%)
80
ΔVO
(50mV/DIV)
5MHz
12MHz
60
40
20
0
0
200
400
50µs/DIV
600
800
1K
1.2K
IO (mA)
FIGURE 19. EFFICIENCY vs IO (PWM MODE)
FIGURE 18. PWM LOAD TRANSIENT RESPONSE (100mA TO
500mA)
1
0.5
12MHz
0.3
VO CHANGES (%)
VO CHANGES (%)
0.6
1.4MHz
0.2
5MHz
0
-0.2
12MHz
0.1
1.4MHz
-0.1
5MHz
-0.3
-0.6
-0.5
0
200
400
600
800
1K
1.2K
0
200
IO (mA)
400
600
800
1K
1.2K
VIN (V)
FIGURE 20. LOAD REGULATION (PWM MODE)
FIGURE 21. LINE REGULATION @ 500mA (PWM MODE)
IO=50mA
IO=150mA
2µs/DIV
FIGURE 22. PFM-PWM TRANSITION TIME
7
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
(2V/DIV)
LX
(2V/DIV)
2µs/DIV
FIGURE 23. PFM-PWM TRANSITION TIME
FN7434.6
July 12, 2006
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
3
VO CHANGES (%)
2
1
0
-1
PFM
PWM
-2
-3
0
200
400
600
800
1000
1200
IOUT (mA)
FIGURE 24. PFM-PWM LOAD REGULATION
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
870mW
0.9
486mW
0.5
0.4
θ
M
JA
=
0.3
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.6
SO
P8
/1
20
0
6°
C/
W
0.2
0.1
0.8
0.7
θ
M
SO
P8
/1
11
0
5°
C/
W
JA
=
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0
25
75 85
50
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
8
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7434.6
July 12, 2006
Applications Information
Product Description
The EL7530 is a synchronous, integrated FET 600mA stepdown regulator which operates from an input of 2.5V to 5.5V.
The output voltage is user-adjustable with a pair of external
resistors.
When the load is very light, the regulator automatically
operates in the PFM mode, thus achieving high efficiency at
light load (>70% for 1mA load). When the load increases,
the regulator automatically switches over to a voltage-mode
PWM operating at nominal 1.4MHz switching frequency. The
efficiency is up to 95%.
It can also operate in a fixed PWM mode or be synchronized
to an external clock up to 12MHz for improved EMI
performance.
PFM Operation
The heart of the EL7530 regulator is the automatic
PFM/PWM controller.
If the SYNC pin is connected to ground, the regulator
operates automatically in either the PFM or PWM mode,
depending on load. When the SYNC pin is connected to VIN,
the regulator operates in the fixed PWM mode. When the pin
is connected to an external clock ranging from 1.6MHz to
12MHz, the regulator is in the fixed PWM mode and
synchronized to the external clock frequency.
In the automatic PFM/PWM operation, when the load is light,
the regulator operates in the PFM mode to achieve high
efficiency. The top P channel MOSFET is turned on first. The
inductor current increases linearly to a preset value before it
is turned off. Then the bottom N channel MOSFET turns on,
and the inductor current linearly decreases to zero current.
The N channel MOSFET is then turned off, and an antiringing MOSFET is turned on to clamp the VLX pin to VO.
The inductor current looks like triangular pulses. The
frequency of the pulses is mainly a function of output current.
The higher the load, the higher the frequency of the pulses
until the inductor current becomes continuous. At this point,
the controller automatically changes to PWM operation.
When the controller transitions to PWM mode, there can be
a perturbation to the output voltage. This perturbation is due
to the inherent behavior of switching converters when
transitioning between two control loops. To reduce this
effect, it is recommended to use the phase-lead capacitor
(C4) shown in the Typical Application Diagram on page 1.
This capacitor allows the PWM loop to respond more quickly
to this type of perturbation. To properly size C4, refer to the
Component Selection section.
PWM Operation
The regulator operates the same way in the forced PWM or
synchronized PWM mode. In this mode, the inductor current
is always continuous and does not stay at zero.
9
In this mode, the P channel MOSFET and N channel
MOSFET always operate complementary. When the
PMOSFET is on and the NMOSFET off, the inductor current
increases linearly. The input energy is transferred to the
output and also stored in the inductor. When the P channel
MOSFET is off and the N channel MOSFET on, the inductor
current decreases linearly, and energy is transferred from
the inductor to the output. Hence, the average current
through the inductor is the output current. Since the inductor
and the output capacitor act as a low pass filter, the duty
cycle ratio is approximately equal to VO divided by VIN.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 22µF ceramic and
inductor is 1.5µH to 2.2µH.
Forced PWM Mode/SYNC Input
Pulling the SYNC pin HI (>2.5V) forces the converter into
PWM mode in the next switching cycle regardless of output
current. The duration of the transition varies depending on the
output current. Figures 22 and 23 (under two different loading
conditions) show the device goes from PFM to PWM mode.
Note: In Forced PWM mode, the IC will continue to start-up
in PFM mode to support pre-biased load applications.
Start-Up and Shut-Down
When the EN pin is tied to VIN, and VIN reaches
approximately 2.4V, the regulator begins to switch. The
inductor current limit is gradually increased to ensure proper
soft-start operation.
When the EN pin is connected to a logic low, the EL7530 is
in the shut-down mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 1µA.
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
Current Limit and Short-Circuit Protection
The current limit is set at about 1.2A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
FN7434.6
July 12, 2006
Thermal Performance
The EL7530 is available in a fused-lead MSOP10.
Compared with regular MSOP10 package, the fused- lead
package provides lower thermal resistance. The θJA is
100°C/W on a 4-layer board and 125°C/W on 2-layer board.
Maximizing the copper area around the pins will further
improve the thermal performance.
Power Good Output
The PG (pin 8) output is used to indicate when the output
voltage is properly regulating at the desired set point. It is an
open-drain output that should be tied to VIN or VCC through
a 100kΩ resistor. If no faults are detected, EN is high, and
the output voltage is within ~5% of regulation, the PG pin will
be allowed to go high. Otherwise, the open-drain NMOS will
pull PG low.
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
1
f Z = ---------------------2πR 2 C 4
Over a normal range of R2 (~10-100k), C4 will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R1
and R2, which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
1
f P = --------------------------------------2π ( R 1 R 2 )C 4
Output Voltage Selection
Users can set the output voltage of the variable version with
a resister divider, which can be chosen based on the
following formula:
R 2⎞
⎛
V O = 0.8 × ⎜ 1 + -------⎟
R
⎝
1⎠
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
1. Separate the Power Ground ( ) and Signal Ground
( i); connect them only at one point right at the pins
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
We recommend 10µF to 22µF multi-layer ceramic capacitors
with X5R or X7R rating for both the input and output
capacitors, and 1.5µH to 2.2µH for the inductor.
The RMS current present at the input capacitor is decided by
the following formula:
V O × ( V IN – V O )
I INRMS = ----------------------------------------------- × I O
V IN
2. Place the input capacitor as close to VIN and PGND pins
as possible
3. Make the following PC traces as small as possible:
from LX pin to L
from CO to PGND
4. If used, connect the trace from the FB pin to R1 and R2
as close as possible
5. Maximize the copper area around the PGND pin
6. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7530 Application Brief.
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
( V IN – V O ) × V O
ΔI IL = -------------------------------------------L × V IN × f S
L is the inductance
fS the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
10
FN7434.6
July 12, 2006
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. C 6/99
0.10 C
N LEADS
0.08 M C A B
b
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
L1
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
A
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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11
FN7434.6
July 12, 2006
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