DATASHEET

EL7532
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December 9, 2015
FN7435.9
Monolithic 2A Step-Down Regulator
Features
The EL7532 is a synchronous, integrated FET 2A step-down
regulator with internal compensation. It operates with an
input voltage range from 2.5V to 5.5V, which accommodates
supplies of 3.3V, 5V, or a single Li-Ion battery source. The
output can be externally set from 0.8V to VIN with a resistive
divider.
• 2A continuous current (from -40°C to +85°C)
The EL7532 features PWM mode control. The operating
frequency is typically 1.5MHz. Additional features include a
100ms Power-On-Reset output, <1µA shut-down current
and over-temperature protection.
The EL7532 is available in the 10-pin MSOP package,
making the entire converter occupy less than 0.18 in2 of
PCB area with components on one side only. The package is
specified for operation over the full -40°C to +85°C
temperature range.
EL7532IYZ
(Note)
BAARA
• 1.5MHz (typ.) switching frequency
• 100ms Power-On-Reset output (POR)
• Internally-compensated voltage mode controller
• Up to 94% efficiency
• <1µA shut-down current
• Over-temperature protection
• Pb-free available (RoHS compliant)
Applications
• Bar code readers
TEMP.
RANGE
(°C)
PART
MARKING
• Max height 1.1mm MSOP10
• PDA and pocket PC computers
Ordering Information
PART
NUMBER
• Less than 0.18 in2 footprint for the complete 2A converter
PACKAGE
PKG.
DWG. #
-40 to +85 10 Ld MSOP MDP0043
(Pb-free)
*Add -T7 suffix for 1k unit or -T13 suffix for 2.5k unit tape and reel
options. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• ADSL modems
• Portable instruments
• Li-Ion battery powered devices
• ASIC/FPGA/DSP supplies
• Set top boxes
Typical Application Schematic
VS
(2.5V to 5.5V)
R3 100
C2
10µF
Pinout
EL7532
(10 LD MSOP)
TOP VIEW
LX
VDD
C3
0.1µF
FB 10
R5 100k
2 PGND
VO 9
3 LX
POR 8
4 VIN
R1*
124k
POR
R4 100k
1.8µH
C1
10µF
EL7532
EN
1 SGND
FB
RSI
R2 *
100k
R6
100k
PGND
SGND
VO
EN 7
5 VDD
RSI 6
1
VO
L1
VIN
VO = 0.8V * (1 + R2 / R1)
*C4 is optional. Make sure that loop response are
measured in actual application.
C4
470pF
(1.8V @ 2A)
SIGNAL
GROUND
POWER
GROUND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC.
Copyright © Intersil Americas LLC. 2004-2007, 2015. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7532
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VIN, VDD, POR to SGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
RSI, EN, VO, FB to SGND . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4A
ESD Classification
Human Body Model (Per JESD22-A114-B) . . . . . . . . . . . . Class 2
Thermal Resistance (Typical)
JA (°C/W)
MSOP10 Package (Note 1) . . . . . . . . . . . . . . . . . . .
115
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
790
800
810
mV
250
nA
2.5
5.5
V
DC CHARACTERISTICS
VFB
Feedback Input Voltage
IFB
Feedback Input Current
VIN, VDD
Input Voltage
VIN,OFF
Minimum Voltage for Shut-down
VIN falling
2
2.2
V
VIN,ON
Maximum Voltage for Start-up
VIN rising
2.2
2.4
V
IDD
Supply Current
PWM, VIN = VDD = 5V
400
500
µA
EN = 0, VIN = VDD = 5V
0.1
1
µA
PMOS FET Resistance
VDD = 5V, wafer test only
52
80
m
RDS(ON)-NMOS NMOS FET Resistance
VDD = 5V, wafer test only
35
65
m
TOT,OFF
Over-temperature Threshold (Note 2)
T rising
145
°C
TOT,ON
Over-temperature Hysteresis (Note 2)
T falling
130
°C
IEN, IRSI
EN, RSI Current
VEN, VRSI = 0V and 3.3V
VEN1, VRSI1
EN, RSI Rising Threshold
VDD = 3.3V
VEN2, VRSI2
EN, RSI Falling Threshold
VDD = 3.3V
VPOR
Minimum VFB for POR, WRT Targeted
VFB Value
VFB rising
VOLPOR
POR Voltage Drop
ISINK = 5mA
35
VLINEREG
Line Regulation (Note 2)
VIN = 2.5V to 6V, IOUT = 2A, VOUT = 1.8V
0.1
%/V
VLOADREG
Load Regulation (Note 2)
VIN = 3.3V, VOUT = 1.8V, IOUT = 0 to 2A
0.5
%
RDS(ON)-PMOS
VFB falling
-1
1
µA
2.4
V
0.8
V
95
86
%
%
70
mV
AC CHARACTERISTICS
FPWM
PWM Switching Frequency
tRSI
1.35
1.5
1.65
MHz
Minimum RSI Pulse Width (Note 2)
25
50
ns
tSS
Soft-start Time (Note 2)
650
tPOR
Power On Reset Delay Time (Note 2)
80
100
µs
120
ms
NOTE:
2. Not production tested.
2
FN7435.9
December 9, 2015
EL7532
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
SGND
Negative supply for the controller stage
2
PGND
Negative supply for the power stage
3
LX
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
5
VDD
Power supply for the controller stage
6
RSI
Resets POR timer; Connect to ground if not used
7
EN
Enable; Can be connected directly to the VIN for enable
8
POR
9
VO
Output voltage sense pin
10
FB
Voltage feedback input; connected to an external resistor divider between VO and SGND for variable
output
Power on reset open drain output; Leave open if not used
Block Diagram
5
9
VDD
VO
10pF
VIN
124k
10
FB
5M
+
PWM
COMPENSATION
100k
CLOCK
1.5MHz
7
EN
P-DRIVER
1.8µ
LX
CONTROL
LOGIC
RAMP
GENERATOR
SOFTSTART
10µF
N-DRIVER
+
–
BANDGAP
REFERENCE
1
6
1.8V
2A
3
EN
10µF
2.5V
TO 5V
+
PWM
COMPARATOR
4
UNDERVOLTAGE
LOCKOUT
PGND
100k
TEMPERATURE
SENSE
SGND
2
POR
PG
8
POR
RSI
3
FN7435.9
December 9, 2015
EL7532
100
100
80
80
60
VO = 1.2V
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
VO = 3.3V
40
VO = 1.8V
20
0
60
VO = 1.2V
VO = 2.5V
40
VO = 1.8V
20
MAXIMUM EFFICIENCY, = 95%
0
0.5
1.0
1.5
2.0
0
2.5
MAXIMUM EFFICIENCY, = 95%
0
0.5
1.0
IOUT (A)
80
0.6
VO CHANGES (%)
EFFICIENCY (%)
1.0
60
VO = 1.8V
VO = 1.2V
20
IO = 2A
VO = 0.8V
0.2
VO = 2.5V
-0.2
VO = 3.3V
-0.6
MAXIMUM EFFICIENCY, = 94%
0
0.5
1.0
1.5
2.0
-1.0
2.5
2.5
3.0
IOUT (A)
1.0
0.6
0.6
VO CHANGES (%)
VO CHANGES (%)
4.0
4.5
5.0
5.5
6.0
FIGURE 4. LINE REGULATION
1.0
0.2 VO = 0.8V
VO = 3.3V
-0.2
3.5
VIN (V)
FIGURE 3. EFFICIENCY vs IOUT @ VIN = 2.5V
-0.6
-1.0
2.5
FIGURE 2. EFFICIENCY vs IOUT @ VIN = 3.3V
100
0
2.0
IOUT (A)
FIGURE 1. EFFICIENCY vs IOUT @ VIN = 5V
40
1.5
0.2
VO = 0.8V
-0.2 VO = 2.5V
-0.6
0
0.5
1.0
1.5
2.0
IOUT (A)
FIGURE 5. LOAD REGULATION @ VIN = 5V
4
2.5
-1.0
0
0.5
1.0
1.5
2.0
2.5
IOUT (A)
FIGURE 6. LOAD REGULATION @ VIN = 3.3V
FN7435.9
December 9, 2015
EL7532
Typical Performance Curves
(Continued)
1.0
VO CHANGES (%)
VIN
100mV/d
VO = 0.8V
0.5
0.5A/d
iL
0
VO = 1.8V
VLX
2V/d
VO
10mV/d
-0.5
-1.0
0
0.5
1.0
1.5
2.0
2.5
1µs/d
IOUT (A)
FIGURE 7. LOAD REGULATION @ VIN = 2.5V
FIGURE 8. LOAD REGULATION @ VIN = 2.5V
VIN
(1V/d)
VIN
(2V/d)
VO
(2V/d)
IIN
(0.5A/d)
POR
(2V/d)
VO
(1V/d)
50ms/d
0.5ms/d
FIGURE 9. START-UP 1
FIGURE 10. START-UP 2
VIN
(2V/d)
VO
(2V/d)
RSI
(2V/d)
VO
50mV/d
2A
IO
POR
(2V/d)
0.1A
50ms/d
0.5ms/d
FIGURE 11. POR FUNCTION
FIGURE 12. TRANSIENT RESPONSE
5
FN7435.9
December 9, 2015
EL7532
Where RL is the DC resistance on the inductor and rDS(ON1)
the PFET on-resistance, nominal 70m at room temperature
with tempco of 0.2m/°C.
Applications Information
Product Description
The EL7532 is a synchronous, integrated FET 2A step-down
regulator which operates from an input of 2.5V to 5.5V. The
output voltage is user-adjustable with a pair of external
resistors.
The internally-compensated controller makes it possible to
use only two ceramic capacitors and one inductor to form a
complete, very small footprint 2A DC/DC converter.
Start-Up and Shut-Down
When the EN pin is tied to VIN, and VIN reaches
approximately 2.4V, the regulator begins to switch. The
output voltage is gradually increased to ensure proper
soft-start operation.
When the EN pin is connected to a logic low, the EL7532 is
in the shut-down mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 1µA.
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
PWM Operation
In the PWM mode, the P-Channel MOSFET and N-Channel
MOSFET always operate complementary. When the
PMOSFET is on and the NMOSFET off, the inductor current
increases linearly. The input energy is transferred to the
output and also stored in the inductor. When the P-Channel
MOSFET is off and the N-Channel MOSFET on, the inductor
current decreases linearly, and energy is transferred from
the inductor to the output. Hence, the average current
through the inductor is the output current. Since the inductor
and the output capacitor act as a low pass filter, the duty
cycle ratio is approximately equal to VO divided by VIN.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 22µF ceramic. The
inductor is nominally 1.8µH, though 1.5µH to 2.2µH can be
used.
100% Duty Ratio Operation
EL7532 utilizes CMOS power FET's as the internal
synchronous power switches. The upper switch is a PMOS
and lower switch a NMOS. This not only saves a boot
capacitor, it also allows 100% turn-on of the upper PFET
switch, achieving VO close to VIN. The maximum achievable
VO is:
V O = V IN –  R L + r DS  ON1    I O
(EQ. 1)
As the input voltage drops gradually close or even below the
preset VO, the converter gets into 100% duty ratio. At this
condition, the upper PFET needs some minimum turn-off
time if it is turned off. This off-time is related to input/output
conditions. This makes the duty ratio appear randomly and
increases the output ripple somewhat until the 100% duty
ratio is reached. A larger output capacitor could reduce the
random-looking ripple. Users need to verify if this condition
has an adverse effect on the overall circuit if close to 100%
duty ratio is expected.
RSI/POR Function
When powering up, the open-collector Power-On-Reset
output holds low for about 100ms after VO reaches the
preset voltage. When the active-HI reset signal RSI is
issued, POR goes to low immediately and holds for the
same period of time after RSI comes back to LOW. The
output voltage is unaffected. (Please refer to the timing
diagram). When the function is not used, connect RSI to
ground and leave open the pull-up resister R4 at POR pin.
The POR output also serves as a 100ms delayed Power
Good signal when the pull-up resister R4 is installed. The
RSI pin needs to be directly (or indirectly through a resister
R5) connected to Ground for this to function properly.
VO
MIN
25ns
RSI
100ms
100ms
POR
FIGURE 13. RSI AND POR TIMING DIAGRAM
Output Voltage Selection
Users can set the output voltage of the converter with a
resister divider, which can be chosen based on Equation 2:
R 1

V O = 0.8   1 + -------
R

2
(EQ. 2)
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. We recommend 10µF to 22µF
multi-layer ceramic capacitors with X5R or X7R rating for
both the input and output capacitors, and 1.5µH to 2.2µH
inductance for the inductor.
At extreme conditions (VIN < 3V, IO > 0.7A, and junction
temperature higher than +75°C), input cap C1 is
6
FN7435.9
December 9, 2015
EL7532
recommended to be 22µF. Otherwise, if any of the above 3
conditions is not true, C1 can remain as low as 10µF.
The RMS current present at the input capacitor is decided by
Equation 3:
V O   V IN - V O 
I INRMS = ------------------------------------------------  I O
V IN
(EQ. 3)
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
 V IN - V O   V O
I IL = -------------------------------------------L  V IN  f S
(EQ. 4)
• L is the inductance
• fS the switching frequency (nominally 1.5MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 3A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow Equation 5:
1
f Z = ---------------------2R 2 C 4
(EQ. 5)
Over a normal range of R2 (~10k to 100k), C4 will range
from ~470pF to 4700pF. The pole frequency cannot be set
once the zero frequency is chosen as it is dictated by the
ratio of R1 and R2, which is solely determined by the desired
output set point. Equation 6 shows the pole frequency
relationship:
1
f P = --------------------------------------2  R 1 R 2 C 4
Thermal Shut-Down
Once the junction reaches about +145°C, the regulator shuts
down. Both the P-Channel and the N-Channel MOSFETs
turn off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about +130°C, the
regulator will restart again in the same manner as the EN pin
connects to logic HI.
Thermal Performance
The EL7532 is in a fused-lead MSOP10 package. Compared
to the regular MSOP10 package, the fused-lead package
provides lower thermal resistance. The typical JA of
+115°C/W (See Thermal Information section in spec table)
can be improved by maximizing the copper area around the
pins. A JA of +100°C/W can be achieved on a 4-layer board
and +125°C/W on a 2-layer board. Refer to Intersil’s Tech
Brief, TB379, for more information on thermal resistance.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
• Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the pins
• Place the input capacitor as close to VIN and PGND pins
as possible
• Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
• If used, connect the trace from the FB pin to R1 and R2 as
close as possible
• Maximize the copper area around the PGND pin
• Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7532 Application Brief.
(EQ. 6)
7
FN7435.9
December 9, 2015
EL7532
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
December 09, 2015
FN7435.9
CHANGE
Updated the Ordering Information table on page 1.
Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
8
FN7435.9
December 9, 2015
EL7532
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
0.08 M C A B
b
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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9
FN7435.9
December 9, 2015
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