DATASHEET

ISL43L210
®
Data Sheet
March 15, 2005
Ultra Low ON-Resistance, +1.1V to +4.5V
Single Supply, SPDT Analog Switch
The Intersil ISL43L210 device is a low ON-resistance, low
voltage, bidirectional, single pole/double throw (SPDT)
analog switch designed to operate from a single +1.1V to
+4.5V supply. Targeted applications include battery powered
equipment that benefit from low on-resistance and fast
switching speeds (tON = 7ns, tOFF = 3ns). The digital logic
input is 1.8V CMOS compatible when using a single +3V
supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL43L210 is offered in a 6 lead SC70 package, alleviating
board space limitations.
The ISL43L210 is a committed SPDT that consist of one
normally open (NO) and one normally closed (NC) switch.
This configuration can also be used as a 2-to-1 multiplexer.
TABLE 1. FEATURES AT A GLANCE
Number of Switches
1
SW
SPDT or 2-1 MUX
1.8V RON
0.75Ω
1.8V tON/tOFF
16ns/5ns
3V RON
0.38Ω
3V tON/tOFF
8ns/4ns
4.3V RON
0.34Ω
4.3V tON/tOFF
7ns/3ns
Package
6 Ld SC70
1
FN6131.0
Features
• Pb-free available (RoHS compliant)
• Drop In replacement for the MAX4714
• ON resistance (RON)
- VCC = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.34Ω
- VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.38Ω
- VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75Ω
• RON matching between channels . . . . . . . . . . . . . . . 0.002Ω
• RON flatness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.06Ω
• Single supply operation . . . . . . . . . . . . . . . . . +1.1V to +4.5V
• Fast switching action (+3.9V Supply)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ns
• Guaranteed break-before-make
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV
• 1.8V CMOS logic compatible (+3V supply)
• 6 lead SC70 package
Applications
• Battery powered, handheld, and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Portable test and measurement
• Medical equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL43L210
Pinout
Ordering Information
(Note 1)
ISL43L210 (SC70)
TOP VIEW
PART NO.
(BRAND)
IN 1
6 NO
V+ 2
5 COM
4 NC
GND 3
PACKAGE
PKG.
DWG. #
ISL43L210IH-T
(CMA)
-40 to 85
6 Ld SC70
Tape and Reel
P6.049
ISL43L210IHZ-T
(CMA)
(See Note)
-40 to 85
6 Ld SC70
P6.049
Tape and Reel (Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
NOTE:
TEMP.
RANGE (°C)
LOGIC
PIN NC
PIN NO
0
On
Off
1
Off
On
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
PIN
V+
FUNCTION
System Power Supply Input (+1.1V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
2
FN6131.0
March 15, 2005
ISL43L210
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±150mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±300mA
ESD Rating:
HBM > . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1000V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
6 Ld SC70 Package . . . . . . . . . . . . . . . . . . . . . . . . .
590
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.36
-
Ω
Full
-
0.4
-
Ω
25
-
0.002
-
Ω
Full
-
0.003
-
Ω
25
-
0.06
-
Ω
Full
-
0.08
-
Ω
25
-30
-
30
nA
Full
-100
-
100
nA
25
-30
-
30
nA
Full
-100
-
-100
nA
25
-
7
15
ns
Full
-
-
20
ns
25
-
3
10
ns
Full
-
-
15
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 2.2V
(See Figure 5)
RON Matching Between Channels,
∆RON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 2.2V
RON Flatness, RFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0.8V, 2.2V,
3.5V, (Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Break-Before-Make Time Delay, tD
V+ = 4.5V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 3, Note 8)
Full
1
3
-
ns
Charge Injection, Q
VG = V+/2, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
25
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
-
-70
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-
-70
-
dB
3
FN6131.0
March 15, 2005
ISL43L210
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEMP
(°C)
(NOTE 5)
MIN
TYP
25
-
0.006
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
-
40
-
pF
COM ON Capacitance, CCOM(ON)
25
-
100
-
pF
Full
1.1
-
4.5
V
25
-
-
0.05
µA
Full
-
-
0.4
µA
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.6
-
-
V
Full
-0.5
-
0.5
µA
PARAMETER
TEST CONDITIONS
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
(NOTE 5)
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ =+4.5V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+ (Note 8)
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed but not tested.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.44
0.6
Ω
Full
-
-
0.7
Ω
25
-
0.005
0.03
Ω
Full
-
-
0.05
Ω
25
-
0.06
0.1
Ω
Full
-
-
0.12
Ω
25
-
0.9
-
nA
Full
-
8
-
nA
25
-
0.9
-
nA
Full
-
17
-
nA
25
-
8
15
ns
Full
-
-
20
ns
25
-
4
10
ns
Full
-
-
15
ns
Full
1
4
-
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 1.5V
(See Figure 5)
RON Matching Between Channels,
∆RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 1.5V
RON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0.6V, 1.5V,
2.1V (Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Break-Before-Make Time Delay, tD
4
V+ = 3.0V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 3, Note 8)
FN6131.0
March 15, 2005
ISL43L210
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Charge Injection, Q
VG = V+/2, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
22
-
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 4)
25
-
-70
-
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 6)
25
-
-70
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32Ω
25
-
0.006
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
40
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25
-
100
-
pF
25
-
0.018
-
µA
Full
-
0.13
-
µA
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
µA
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+ (Note 8)
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.75
0.9
Ω
Full
-
-
1
Ω
25
-
0.3
-
nA
Full
-
7
-
nA
25
-
0.9
-
nA
Full
-
18
-
nA
25
-
16
22
ns
Full
-
-
25
ns
25
-
5
12
ns
Full
-
-
15
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0.9V
(See Figure 5)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 1.8V, VCOM = 0.3V, 1.5V, VNO or VNC = 1.5V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 1.8V, VCOM = 0.3V, 1.5V, or VNO or VNC = 0.3V,
1.5V, or Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1, Note 8)
Break-Before-Make Time Delay, tD
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 3, Note 8)
Full
2
5
-
ns
Charge Injection, Q
VG = V+/2, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
15
-
pC
25
-
0.018
-
µA
Full
-
0.13
-
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 1.8V, VIN = 0V or V+
5
FN6131.0
March 15, 2005
ISL43L210
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEMP
(°C)
(NOTE 5)
MIN
TYP
Input Voltage Low, VINL
Full
-
-
0.4
V
Input Voltage High, VINH
Full
1
-
-
V
Full
-0.5
-
0.5
µA
PARAMETER
TEST CONDITIONS
(NOTE 5)
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 1.1V, VIN = 0V or V+ (Note 8)
Electrical Specifications - 1.1V Supply
Test Conditions: V+ = +1.1V, GND = 0V, VINH = 1.0V, VINL = 0.3V (Note 4, 6),
Unless Otherwise Specified
TEMP
(°C)
(NOTE 5)
MIN
TYP
Full
0
-
V+
V
25
-
2.8
-
Ω
Full
-
3.5
-
Ω
25
-
25
-
ns
Full
-
28
-
ns
25
-
7
-
ns
Full
-
10
-
ns
Full
-
9
-
ns
Input Voltage Low, VINL
Full
-
0.4
-
V
Input Voltage High, VINH
Full
-
0.58
-
V
PARAMETER
TEST CONDITIONS
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.1V, ICOM = 100mA, VNO or VNC = 0.6
(See Figure 5)
ON Resistance, RON
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.1V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 1.1V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF,
(See Figure 1)
Break-Before-Make Time Delay, tD
V+ = 1.1V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF,
(See Figure 3)
DIGITAL INPUT CHARACTERISTICS
Test Circuits and Waveforms
V+
tr < 5ns
tf < 5ns
V+
LOGIC
INPUT
50%
0V
SWITCH
INPUT
tOFF
SWITCH
INPUT VNO
VOUT
NO or NC
COM
IN
VOUT
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
-----------------------------V OUT = V
(NO or NC) R + R
L
( ON )
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
6
FN6131.0
March 15, 2005
ISL43L210
Test Circuits and Waveforms (Continued)
V+
SWITCH
OUTPUT
VOUT
RG
∆VOUT
V+
ON
ON
LOGIC
INPUT
OFF
C
VG
VOUT
COM
NO or NC
GND
IN
CL
0V
LOGIC
INPUT
Q = ∆VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
V+
NO
VNX
LOGIC
INPUT
C
VOUT
COM
NC
IN
90%
SWITCH
OUTPUT
VOUT
0V
tD
CL
35pF
RL
50Ω
0V
GND
LOGIC
INPUT
CL includes fixture and stray capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
V+
C
C
RON = V1/100mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
IN
0V or V+
COM
ANALYZER
100mA
IN
V1
0V or V+
COM
GND
GND
RL
FIGURE 4. OFF ISOLATION TEST CIRCUIT
7
FIGURE 5. RON TEST CIRCUIT
FN6131.0
March 15, 2005
ISL43L210
Test Circuits and Waveforms (Continued)
V+
C
V+
C
50Ω
NO or NC
COM
NO or NC
IN1
SIGNAL
GENERATOR
0V or V+
IN
NC or NO
ANALYZER
0V or V+
IMPEDANCE
ANALYZER
COM
GND
GND
RL
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL43L210 is a bidirectional, single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single +1.1V to +4.5V supply with low on-resistance
(0.34Ω) and high speed operation (tON = 7ns, tOFF = 3ns). The
device is especially well suited for portable battery powered
equipment due to its low operating supply voltage (1.1V), low
power consumption (1.8µW max), low leakage currents
(100nA max), and the tiny SC70 packaging. The ultra low onresistance and Ron flatness provide very low insertion loss
and distortion to application that require signal reproduction.
FIGURE 7. CAPACITANCE TEST CIRCUIT
purpose of using a low RON switch. Connecting schottky
diodes to the signal pins as shown in Figure 8 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the input (see Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
8
INX
VNX
OPTIONAL
SCHOTTKY
DIODE
VCOM
GND
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43L210 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL43L210 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.2V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.1V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
curves for details.
FN6131.0
March 15, 2005
ISL43L210
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2V to 3.6V (See Figure 17). At 3.6V
the VIH level is about 1.1V. This is still below the 1.8V CMOS
guaranteed high output minimum level of 1.4V, but noise
margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
90MHz (See Figure 18). The frequency response is very
consistent over a wide V+ range, and for varying analog
signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 19 details the high Off Isolation and Crosstalk
rejection provided by this family. At 100kHz, Off Isolation is
about 70dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
9
FN6131.0
March 15, 2005
ISL43L210
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
3
0.5
ICOM = 100mA
ICOM = 100mA
2.5
0.45
2
0.4
RON (Ω)
RON (W)
V+ = 2.7V
V+ = 3V
0.5
V+ = 4.3V
0.3
0
0
1
V+ = 1.5V
1
V+ = 3.6V
0.35
V+ = 1.1V
1.5
2
3
4
5
V+ = 1.62V
0
V+ = 1.8V
0.5
1
VCOM (V)
VCOM (V)
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
2
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.65
0.55
V+ = 4.3V
ICOM = 100mA
0.5
V+ = 2.7V
ICOM = 100mA
0.6
0.55
0.4
RON (Ω)
0.45
RON (Ω)
1.5
85°C
0.5
85°C
0.45
25°C
0.35
0.4
25°C
0.3
-40°C
0.35
-40°C
0.25
0
1
2
3
4
0.3
5
0
0.5
1
1.5
VCOM (V)
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
0.8
2.5
3
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
100
V+ = 1.8V
ICOM = 10mA
85°C
2
VCOM (V)
0.7
50
RON (Ω)
Q (pC)
25°C
0.6
-40°C
0.5
0
V+ = 1.8V
V+ = 3V
-50
0.4
V+ = 4.2V
0.3
0
0.5
1
1.5
VCOM (V)
FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
10
2
-100
0
1
2
3
4
5
VCOM (V)
FIGURE 14. CHARGE INJECTION vs SWITCH VOLTAGE
FN6131.0
March 15, 2005
ISL43L210
30
7
25
6
20
5
tOFF (ns)
tON (ns)
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
15
85°C
4
85°C
25°C
10
-40°C
3
25°C
-40°C
5
1
1.5
2
2.5
3
3.5
4
2
4.5
1.5
1
2
2.5
V+ (V)
FIGURE 15. TURN-ON TIME vs SUPPLY VOLTAGE
3.5
1
VINH
0.9
0.8
0.7
GAIN
0
-20
PHASE
0
20
VINL
0.6
40
0.5
60
0.4
80
RL = 50Ω
VIN = 0.2VP-P to 2.8VP-P (V+ = 3.0V)
1
1.5
2
2.5
3
3.5
4
4.5
1
10
V+ (V)
0
0
10
-20
20
-30
30
40
ISOLATION
-50
50
-60
60
CROSSTALK
-70
70
-80
80
-90
90
10K
100K
1M
10M
SUBSTRATE POTENTIAL (POWERED UP):
GND
OFF ISOLATION (dB)
-10
FIGURE 18. FREQUENCY RESPONSE
Die Characteristics
V+ = 1.1V to 4.5V
-100
1K
300
FREQUENCY (MHz)
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
-40
100
PHASE (DEGREES)
NORMALIZED GAIN (dB)
1.1
CROSSTALK (dB)
4.5
V+ = 1.1V to 4.5V
1.2
0.3
4
FIGURE 16. TURN-OFF TIME vs SUPPLY VOLTAGE
1.3
VINH AND VINL (V)
3
V+ (V)
TRANSISTOR COUNT:
57
PROCESS:
Submicron CMOS
100
100M 500M
FREQUENCY (Hz)
FIGURE 19. CROSSTALK AND OFF ISOLATION
11
FN6131.0
March 15, 2005
ISL43L210
Small Outline Transistor Plastic Packages (SC70-6)
0.20 (0.008) M
P6.049
VIEW C
C
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
CL
INCHES
e
b
SYMBOL
6
5
4
CL
CL
E1
E
1
2
3
e1
C
D
CL
A
A2
SEATING
PLANE
A1
-C-
WITH
b
PLATING
b1
c
c1
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.031
0.043
0.80
1.10
-
A1
0.000
0.004
0.00
0.10
-
A2
0.031
0.039
0.00
1.00
-
b
0.006
0.012
0.15
0.30
-
b1
0.006
0.010
0.15
0.25
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.009
0.08
0.20
6
D
0.073
0.085
1.85
2.15
3
E
0.071
0.094
1.80
2.40
-
E1
0.045
0.053
1.15
1.35
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0512 Ref
1.30 Ref
-
L
0.10 (0.004) C
MIN
0.010
0.018
0.26
4
0.46
L1
0.017 Ref.
0.420 Ref.
L2
0.006 BSC
0.15 BSC
N
6
6
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.15
0.25
α
0o
8o
0o
8o
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO203AB.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
4X θ1
VIEW C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN6131.0
March 15, 2005
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