Application Note 1658 ISL28208SOICEVAL2Z Evaluation Board User’s Guide Introduction Power Supplies (Figure 1) The ISL28208SOICEVAL2Z evaluation board is designed to evaluate the performance of the ISL28208 dual Operational Amplifier. The ISL28208 is a dual low power precision amplifier that features a common mode input voltage range extending to 0.5V below the V- rail, a rail-to-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which makes it ideal for single supply applications where input operation at ground is important. With a wide operating range from 3V to 40V, in combination with its precision, low power, and small footprint, ISL28208 provides the user with outstanding value and flexibility relative to similar competitive parts. External power connections are made through the V+, V-, VREF, and GND connections on the evaluation board. The circuit can operate from a single supply or from dual supplies. For single supply operation, the V- and GND pins are tied together to the negative or ground reference of the power supply. For split supplies, V+ and V- terminals connect to their respective supply terminals. De-coupling capacitors C2 and C4 provide low-frequency power-supply filtering, while additional capacitors, C3 and C5, which are connected close to the part, filter out high frequency noise. Anti-reverse diode D1 (optional) protects the circuit in the momentary case of accidentally reversing the power supplies to the evaluation board. The VREF pin can be connected to ground to establish a ground referenced input for split supply operation, or can be externally set to any reference level for single supply operation. C4 1µF 2 1 • Banana Jack Connectors for Power Supply and VREF Inputs 1 1 1 2 1 R16 0 • External VREF input 3 C2 1µF 1 • Singled-Ended or Differential Input Operation VREF J14 • Dual Supply Operation: ±4.5V to ±20V J8 • Single Supply Operation: +9V to +40V 3 2 J12 V+ V3 2 J13 J11 J6 Evaluation Board Key Features 1 • ISL28208 Data Sheet, FN6935 1 R31 2 1 0 Reference Documents • BNC Connectors for Op Amp Input and Output Terminals D1 CLOSE TO DUT • Convenient PCB Pads for Op Amp Input/Output Impedance Loading C3 0.01µF C5 0.01µF FIGURE 1. POWER SUPPLY CIRCUIT R13/R23 100kΩ INA- 2 INB- 6 R11/R24 10kΩ INA+ 3 INB+ 5 R14/R21 PRECISION SENSOR 10kΩ 8 - V+ ISL28208 V- 1/7 VOUT + 4 R18/R19 100kΩ +4.5V TO +20V GAIN = -10V/V -4.5V TO -20V VREF FIGURE 2. PRECISION AMPLIFIER WITH G = -10V/V July 26, 2011 AN1658.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2011. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1658 Amplifier Configuration (Figure 3) The schematic of the op amp input stage with the components supplied is shown in Figure 3, with a closed loop gain of 10V/V. The differential amplifier gain is expressed in Equation 1: NOTE: Operational amplifiers are sensitive to output capacitance and may oscillate. In the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. C1 (EQ. 1) J1 R1 R4 R11 0 10k 100k DNP R5 IN-A DNP For single-ended input with an inverting gain G = -10V/V, the IN+ input is grounded and the signal is supplied to the IN- input. VREF can be connected to a reference voltage between the V+ and Vsupply rails. For non-inverting operation with G = 11V/V, the INinput is grounded and the signal is supplied to the IN+ input. The non-inverting gain is strongly dependent on any resistance from IN- to GND. For good gain accuracy, a 0Ω resistor should be installed on the empty R5 pad. OPEN R13 FROM VOUTA TO INA IN+A R14 J2 R2 TO INA + 10k DNP User-selectable Options (Figures 3 and 4) R15 R18 DNP 100k VREF FIGURE 3. INPUT STAGE VOUT_A R26 J15 0 C6 OUT A DNP A voltage divider (Figure 3, R18 and R15) can be added to establish a power supply-tracking common mode reference using the VREF input. The inverting and non-inverting inputs have additional resistor placements for adding input attenuation, or to establish input DC offsets through the VREF pin. C8 Component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, the VREF input, outputs and the amplifier feedback loops. OPEN R28 V OUT = ( V IN+ – V IN- ) • ( R F ⁄ R IN ) + V REF OPEN The output (Figure 4) also has additional resistor and capacitor placements for filtering and loading. FIGURE 4. OUTPUT STAGE TABLE 1. ISL28208SOICEVAL2Z COMPONENTS PARTS LIST DEVICE # DESCRIPTION COMMENTS C2, C4 CAP, SMD, 1206, 1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling C3, C5 CAP, SMD, 0603, 0.01µF, 50V, 10%, X7R, ROHS Power Supply Decoupling C1, C6, C7, C8, C9, C10 CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable capacitors - not populated D1 40V DUAL SERIES SCHOTTKY BARRIER DIODE Reverse Power Protection R11, R14, R21, R24 RESISTOR, SMD, 0603, 10kΩ, 1%, 1/16W, ROHS Gain Setting Resistor R13, R23 RESISTOR, SMD, 0603, 100kΩ, 1%, 1/16W, ROHS Gain Setting Feedback Resistor R1-R3, R5-R8, R10, R12, R15, RESISTOR, SMD, 0603, DNP-PLACE HOLDER, ROHS R17, R20, R22, R28-R30, R32, R34-R36 U1 (ISL28208FBZ) User selectable resistors - not populated ISL28208FBZ, IC PRECISION LOW NOSIE JFET OP AMP, SOIC, ROHS 2 AN1658.0 July 26, 2011 Application Note 1658 ISL28208SOICEVAL2Z Top View Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1658.0 July 26, 2011 ISL28208SOICEVAL2Z Schematic Diagram J11 J6 J14 2 VREF J13 3 J12 V+ J8 V3 C2 C4 3 4 1µF 1 1 0 1 R31 2 1 1 1 1 R16 2 1 0 2 1µF 1 2 D1 CLOSE TO DUT C3 C5 0.01µF R8 2 DNP 3 4 1 OPEN 1 R28 2 DNP C8 2 J24 0 1 2 OUT B 3 4 1 OPEN R29 1 2 DNP 2 C7 1 OPEN 1 R27 2 C9 DNP 1 R36 2 DNP R35 1 R25 2 1 2 0 DNP 1 R20 2 2 DNP R30 J23 J21 J20 J19 J18 J17 R6 2 DNP 1 2 1 DNP R5 1 DNP R3 2 1 4 3 4 3 4 3 4 3 IN+B 1 J4 2 1 5 R7 2 DNP OPEN 1 R26 2 0 2 1 R15 2 1 R18 2 1 R19 2 1 R22 2 100k DNP DNP 100k 1 2 1 1 IN-B 2 R24 2 1 R23 2 1 10k 100k C10 1 1 8 8 2 U1 OPEN 2 2 SOIC8 7 7 OPEN 1 R14 2 3 3 GENERIC 6 6 PACK. R21 2 10k 4 4 5 51 10k R4 2 1 R11 2 1 R13 2 0 10k 100k 2 C1 1 1 IN- 1 R32 2 1 R34 2 DNP DNP VREF J3 5 1 2 DNP 2 R2 2 DNP R12 1 1 2 1 2 1 2 1 1 J2 5 1 R1 2 DNP 2 IN+A 1 2 R10 DNP 1 J1 5 2 2 2 IN-A 1 1 1 1 OUT NODE IN+ J22 IN+ NODE OUT 1 R17 2 DNP IN- OUT A 1 J15 2 5 1 J16 5 Application Note 1658 2 C6 2 0.01µF AN1658.0 July 26, 2011