DATASHEET

Integrated Digital Light Sensor with Interrupt
ISL29023
Features
The ISL29023 is an integrated ambient and infrared light to
digital converter with I2C (SMBus Compatible) Interface. Its
advanced self-calibrated photodiode array emulates human eye
response with excellent IR rejection. The on-chip ADC is capable
of rejecting 50Hz and 60Hz flicker caused by artificial light
sources. The lux range select feature allows users to program the
lux range for optimized counts/lux.
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-bits ADC
For ambient light sensing, an internal 16-bit ADC has been
designed based upon the charge-balancing technique. The
ADC conversion time is nominally 90ms and is user adjustable
from 11µs to 90ms, depending on oscillator frequency and
ADC resolution. In normal operation, typical current
consumption is 70µA. In order to further minimize power
consumption, two power-down modes have been provided. If
polling is chosen over continuous measurement of light, the
auto-power-down function shuts down the whole chip after
each ADC conversion for the measurement. The other
power-down mode is controlled by software via the I2C
interface. The power consumption can be reduced to less than
0.3µA when powered down.
• Integrated noise reduction . . . . . . . . . . . . . . . . . . . . . 50/60Hz
• Light sensor close to human eye response
• Excellent light sensor IR and UV rejection
• Range selection via I2C
- Range1 = 0.015 to 1,000 Lux
- Range2 = 0.06 to 4,000 Lux
- Range3 = 0.24 to 16,000 Lux
- Range4 = 0.96 to 64,000 Lux
• Shutdown modes . . . . . . . . . . . . . . . .Software and Automatic
• Supply current (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85µA
• Shutdown current (Max) . . . . . . . . . . . . . . . . . . . . . . . . . .0.3µA
• Control interface . . . . . . . . . . . . . . . I2C and SMB Compatible
• I2C power supply . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 3.63V
• Sensor power supply . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.63V
• Operating temperature range. . . . . . . . . . . . . -40°C to +85°C
• Small form factor package . . . . . . . . .6 Ld 2.0x2.1x0.7 ODFN
The ISL29023 supports a software and hardware interrupt that
remains asserted until the host clears it through I2C interface.
Function of ADC conversion continues without stopping after
interrupt is asserted.
Related Literature
Designed to operate on supplies from 2.25V to 3.63V with an I2C
supply from 1.7V to 3.63V, the ISL29023 is specified for
operation over the -40°C to +85°C ambient temperature range.
• AN1591 “Evaluation Hardware/Software Manual for ALS
and Proximity Sensor”
• AN1534 “VDD Power-Up and Power Supply Considerations
for Intersil Ambient Light Sensors”
• AN1757 “I2C Fundamentals”
Applications
• AN1782 “Ambient Light Sensor (ISL29023)
Opto-Mechanical Reference Design”
• Mobile devices: smart phone, PDA, GPS
• Computing devices: Notebook PC, Webpad
• Consumer devices: LCD-TV, digital picture frame, digital camera
• Industrial and medical light sensing
1.2
HUMAN EYE
VBUS
1.0
10µF
R
R
0.1µF
R
1
VDD
MCU
SDA
6
SDA
SCL
5
SCL
GPIO
4
ISL29023
SENSOR
3
500k
INT
VSS
NORMALIZED RESPONSE
VDD
0.8
0.6
0.4
IR SENSING
0.2
0
2
AMBIENT LIGHT SENSING
-0.2
300
400
500
600
700
800
900
1000
1100
WAVELENGTH (nm)
FIGURE 1. ISL29023 TYPICAL APPLICATION DIAGRAM
May 1, 2014
FN6691.4
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FIGURE 2. NORMALIZED SPECTRAL RESPONSE FOR AMBIENT
LIGHT SENSING AND IR SENSING
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2012-2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL29023
Block Diagram
VDD
REXT
1
3
IREF
fOSC
PHOTODIODE
ARRAY
COMMAND
REGISTER
5 SCL
I2C/SMB
LIGHT DATA
PROCESS
6 SDA
DATA
CMD
Register
REGISTER
INTEGRATING
ADC
INTERRUPT
2
4
INT
GND
Pin Configuration
Pin Descriptions
ISL29023
(6 LD ODFN)
TOP VIEW
1
VDD
2
GND
3
REXT
PAD
PIN NUMBER PIN NAME
DESCRIPTION
1
VDD
Positive supply; connect this pin to a 2.25V to
3.63V supply
SDA
6
2
GND
Ground pin
SCL
5
3
REXT
INT
4
External resistor pin for ADC reference;
connect this pin to ground through a (nominal)
499kΩ resistor.
4
INT
Interrupt pin; low for interrupt alarming. INT
pin is open drain. INT remains asserted until
the interrupt flag status bit is reset.
5
SCL
I2C serial clock. This line can be pulled from
1.7V to above VDD, 3.63V max.
6
SDA
I2C serial data. This line can be pulled from
1.7V to above VDD, 3.63V max.
PAD
Exposed pad connected to ground or
electrically isolated
*EXPOSED PAD CAN BE CONNECTED TO GND OR
ELECTRICALLY ISOLATED
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP RANGE
(°C)
ISL29023IROZ-T7
ISL29023IROZ-EVALZ
-40 to +85
PACKAGE
(RoHS Compliant)
6 Ld ODFN
PKG.
DWG. #
L6.2x2.1
Evaluation Board (Pb-free)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL29023. For more information on MSL please see tech brief TB477.
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May 1, 2014
ISL29023
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V
I2C Bus (SCL, SDA) and INT Pin Voltage. . . . . . . . . . . . . . . . . . -0.2V to 4.0V
I2C Bus (SCL, SDA) and INT Pin Current. . . . . . . . . . . . . . . . . . . . . . . <10mA
REXT Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to VDD+0.5V
ESD Ratings
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical). . . . . . . . . . . . . . . . . . . . . . . JA (°C/W)
6 Ld ODFN Package (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . . . +90°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile (*) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB477
*Peak temperature during solder reflow +235°C max
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
Electrical Specifications
PARAMETER
VDD = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance, 16-bit ADC operation, unless otherwise specified.
DESCRIPTION
CONDITION
VDD
Power Supply Range
IDD
Supply Current
IDD1
Supply Current when Powered Down
MIN
(Note 7)
MAX
(Note 7)
UNIT
3.63
V
70
85
µA
0.01
0.3
µA
TYP
2.25
VI2C
Supply Voltage Range for
fOSC
Internal Oscillator Frequency
tint
ADC Integration/Conversion Time
FI2C
I2C Clock Rate Range
I2C
Software disabled or auto power-down
Interface
1.7
675
16-bit ADC data
3.63
V
825
kHz
90
ms
1 to 400
kHz
DATA_0
Count Output When Dark
DATA_F
Full Scale ADC Code
DDATA
DATA
Count Output Variation Over Three Light Ambient light sensing
Sources: Fluorescent, Incandescent and
Sunlight
DATA_1
Light Count Output With LSB of
0.015 lux/count
E = 300 lux, Fluorescent light (Note 5), ALS Range
1 (1k lux)
DATA_2
Light Count Output With LSB of
0.06 lux/count
E = 300 lux, Fluorescent light (Note 5), ALS Range
2 (4k lux)
5000
Counts
DATA_3
Light Count Output With LSB of
0.24 lux/count
E = 300 lux, Fluorescent light (Note 5), ALS Range
3 (16k lux)
1250
Counts
DATA_4
Light Count Output With LSB of
0.96 lux/count
E = 300 lux, Fluorescent light (Note 5), ALS Range
4 (64k lux)
312
Counts
Infrared Count Output
E = 210 lux, Sunlight (Note 6), IR sensing, Range 1
DATA_IR1
E = 0 lux, Range 1 (1k lux)
750
1
Counts
Counts
±10
15000
15000
20000
20000
DATA_IR2
Infrared Count Output
E = 210 lux, Sunlight (Note 6), IR sensing, Range 2
5000
DATA_IR3
Infrared Count Output
E = 210 lux, Sunlight (Note 6), IR sensing, Range 3
1250
DATA_IR4
Infrared Count Output
E = 210 lux, Sunlight (Note 6), IR sensing, Range 4
VREF
5
65535
%
25000
Counts
25000
312
Voltage of REXT Pin
0.52
V
VIL
SCL and SDA Input Low Voltage
VIH
SCL and SDA Input High Voltage
0.55
ISDA
SDA Current Sinking Capability
4
5
mA
IINT
INT Current Sinking Capability
4
5
mA
1.25
V
V
NOTES:
5. 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count against an illuminance level of
300 lux fluorescent light.
6. 850nm IR LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count against an illuminance level of
210 lux sunlight at sea level.
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ISL29023
Typical Performance Curves
1.2
HUMAN EYE
1.0
NORMALIZED RESPONSE
1.0
SUN
0.8
HALOGEN
0.6
INCANDESCENT
FLUORESCENT
0.4
0.2
400
500
600
700
800
900
0.6
0.4
IR SENSING
0.2
0
AMBIENT LIGHT SENSING
-0.2
300 400 500 600 700
0
300
0.8
1000 1100
FIGURE 3. NORMALIZED SPECTRAL RESPONSE OF LIGHT SOURCES
30°
30°
40°
40°
50°
50°
60°
60°
70°
70°
80°
80°
90°
0.2 0.4
0.6
0.8
RELATIVE SENSITIVITY
90°
1.0
800
700
65535
INCANDESCENT
HALOGEN
600
500
32768
400
FLUORESCENT
300
200
Ecal =
100
1000 LUX
216
x DATA
0
100 200 300 400 500 600 700 800 900 1000
LUX METER READING (LUX)
0
FIGURE 6. SENSITIVITY TO THREE LIGHT SOURCES
1.10
NORMALIZED OUTPUT CODE
10
OUTPUT CODE (COUNTS)
ALS SENSING
RANGE 1 (1k Lux)
16-BIT ADC
NO COVER GLASS
900
0
FIGURE 5. RADIATION PATTERN
8
6
4
2
0
-60
1000 1100
FIGURE 4. NORMALIZED SPECTRAL RESPONSE FOR AMBIENT
LIGHT SENSING AND IR SENSING
CALCULATED ALS READING (LUX)
ANGLE
900
1000
RADIATION PATTERN
10°
10° 0°
20°
20°
LUMINOSITY
800
WAVELENGTH (nm)
WAVELENGTH (nm)
ADC OUTPUT (COUNT)
NORMALIZED LIGHT INTENSITY
1.2
-20
20
60
100
TEMPERATURE (°C)
FIGURE 7. OUTPUT CODE FOR 0 LUX vs TEMPERATURE
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1.05
300 Lux FLUORESCENT LIGHT
ALS SENSING
RANGE 1 (1k Lux)
1.00
0.95
0.90
-60
-20
20
60
100
TEMPERATURE (°C)
FIGURE 8. OUTPUT CODE vs TEMPERATURE
FN6691.4
May 1, 2014
ISL29023
Typical Performance Curves (Continued)
90
SUPPLY CURRENT (µA)
85
ALS SENSING
10,000 Lux
80
75
70
65
60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE IN ALS SENSING
Principles of Operation
Photodiodes and ADC
The ISL29023 contains two photodiode arrays, which convert light
into current. The spectral response for ambient light sensing and IR
sensing is shown in Figure 4, on page 4. After light is converted to
current during the light signal process, the current output is
converted to digital by a built-in 16-bit Analog-to-Digital Converter
(ADC). An I2C command reads the ambient light or IR intensity in
counts.
The converter is a charge-balancing integrating type 16-bit ADC. The
chosen method for conversion is best for converting small current
signals in the presence of an AC periodic noise. A 100ms integration
time, for instance, highly rejects 50Hz and 60Hz power line noise
simultaneously.
The built-in ADC offers user flexibility in integration time or
conversion time. There are two timing modes: Internal Timing Mode
and External Timing Mode. In Internal Timing Mode, integration time
is determined by an internal oscillator (fOSC), and the n-bit (n = 4, 8,
12, 16) counter inside the ADC. In External Timing Mode, integration
time is determined by the time between two consecutive I2C
External Timing Mode commands. A good balancing act of
integration time and resolution (depending on the application) is
required for optimal results.
The ADC has I2C programmable range select to dynamically
accommodate various lighting conditions. For very dim
conditions, the ADC can be configured at its lowest range
(Range 1) in the ambient light sensing.
Low-Power Operation
The ISL29023 initial operation is at the power-down mode after a
supply voltage is provided. The data registers contain the default
value of 0. When the ISL29023 receives an I2C command to do a
one-time measurement from an I2C master, it will start the ADC
conversion with light sensing. It will go into power-down mode
automatically after one conversion is finished and keep the
conversion data available for the master to fetch anytime
afterwards. The ISL29023 will continuously do ADC conversion
with light sensing if it receives an I2C command of continuous
measurement. It will continuously update the data registers with
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5
the latest conversion data. It will go into power-down mode after
it receives the I2C command.
Ambient Light and IR Sensing
There are four operational modes in ISL29023: Programmable ALS
once with auto power-down, programmable IR sensing once with
auto power-down, programmable continuous ALS sensing and
programmable continuous IR sensing. These four modes can be
programmed in series to fulfill the application needs. The detailed
program configuration is listed in “Command-I Register (Address:
0x00)” on page 8.
When the part is programmed for ambient light sensing, the
ambient light with wavelength within the “Ambient Light
Sensing” spectral response curve in Figure 4 is converted into
current. With ADC, the current is converted to an unsigned n-bit
(up to 16 bits) digital output.
When the part is programmed for infrared (IR) sensing, the IR
light with wavelength within the “IR Sensing” spectral response
curve in Figure 4 is converted into current. With ADC, the current
is converted to an unsigned n-bit (up to 16-bits) digital output.
Interrupt Function
The active low interrupt pin is an open drain pull-down
configuration. The interrupt pin serves as an alarm or monitoring
function to determine whether the ambient light level exceeds
the upper threshold or goes below the lower threshold. It should
be noted that the function of ADC conversion continues without
stopping after interrupt is asserted. If the user needs to read the
ADC count that triggers the interrupt, the reading should be done
before the data registers are refreshed by the following
conversions. The user can also configure the persistency of the
interrupt pin. This reduces the possibility of false triggers, such as
noise or sudden spikes in ambient light conditions. An
unexpected camera flash, for example, can be ignored by setting
the persistency to 8 integration cycles.
FN6691.4
May 1, 2014
ISL29023
Serial Interface
The ISL29023 supports the Inter-Integrated Circuit (I2C) bus data
transmission protocol. The I2C bus is a two-wire serial
bidirectional interface consisting of SCL (clock) and SDA (data).
Both the wires are connected to the device supply via pull-up
resistors. The I2C protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and the
device being controlled is the slave. The transmitting device pulls
down the SDA line to transmit a “0” and releases it to transmit a
“1”. The master always initiates the data transfer, only when the
bus is not busy, and provides the clock for both transmit and
receive operations. The ISL29023 operates as a slave device in
all applications. The serial communication over the I2C interface
is conducted by sending the most significant bit (MSB) of each
byte of data first.
ISL29023 compares it with the internal device identifier. Upon a
correct comparison, the device outputs an acknowledge (LOW) on
the SDA line (See Figure 12).
1
0
0
0
1
0
0
R/W
DEVICE
ADDRESS BYTE
A7
A6
A5
A4
A3
A2
A1
A0
REGISTER
ADDRESS BYTE
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
FIGURE 10. DEVICE ADDDRESS, REGISTER ADDRESS, and DATA BYTE
Write Operation
Start Condition
BYTE WRITE
During data transfer, the SDA line must remain stable while the
SCL line is HIGH. All I2C interface operations must begin with a
START condition, which is a HIGH-to-LOW transition of SDA while
SCL is HIGH (see Figure 12, on page 7). The ISL29023
continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition is met (see Figure 12). A START condition is ignored
during the power-up sequence.
In a byte write operation, ISL29023 requires the Device Address
byte, Register Address byte, and the Data byte. The master starts
the communication with a START condition. Upon receipt of the
Device Address byte, Register Address byte, and the Data byte,
the ISL29023 responds with an acknowledge (ACK). Following
the ISL29023 data acknowledge response, the master
terminates the transfer by generating a STOP condition.
ISL29023 then begins an internal write cycle of the data to the
volatile memory. During the internal write cycle, the device inputs
are disabled and the SDA line is in a high impedance state, so the
device will not respond to any requests from the master (see
Figure 11).
Stop Condition
All I2C interface operations must be terminated by a STOP
condition, which is a LOW-to-HIGH transition of SDA while SCL is
HIGH (see Figure 12). A STOP condition at the end of a read/write
operation places the device in its standby mode. If a stop is
issued in the middle of a Data byte, or before one full Data byte +
ACK is sent, then the serial communication of ISL29023 resets
itself without performing the read/write. The contents of the
array are not affected.
S
T
DEVICE ADDRESS
A
BYTE
R
T
An acknowledge (ACK) is a software convention used to indicate
a successful data transfer. The transmitting device releases the
SDA bus after transmitting 8-bits. During the ninth clock cycle,
the receiver pulls the SDA line LOW to acknowledge the reception
of the eight bits of data (see Figure 12). The ISL29023 responds
with an ACK after recognition of a START condition followed by a
valid Identification Byte, and once again, after successful receipt
of an Address Byte. The ISL29023 also responds with an ACK
after receiving a Data byte of a write operation. The master must
respond with an ACK after receiving a Data byte of a read
operation.
Device Addressing
Following a START condition, the master must output a Device
Address byte. The 7 MSBs of the Device Address byte are known as
the device identifier. The device identifier bits of ISL29023 are
internally hard-wired as “1000100”. The LSB of the Device Address
byte is defined as a read or write (R/W) bit. When this R/W bit is a
“1”, a read operation is selected and when “0”, a write operation is
selected (see Figure 10). The master generates a START condition
followed by Device Address byte 1000100x (x as R/W) and the
6
ADDRESS BYTE
S
T
O
P
DATA BYTE
1 0 0 0 1 0 0 0
SIGNAL AT SDA
A
C
K
SIGNALS FROM
SLAVE DEVICE
Acknowledge
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SIGNAL FROM
MASTER DEVICE
A
C
K
A
C
K
FIGURE 11. BYTE WRITE SEQUENCE
BURST WRITE
The ISL29023 has a burst write operation, which allows the
master to write multiple consecutive bytes from a specific
address location. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle after
the first Data byte is transferred, the master can write to the
whole register array. After the receipt of each byte, the ISL29023
responds with an acknowledge, and the address is internally
incremented by one. The address pointer remains at the last
address byte written. When the counter reaches the end of the
register address list, it “rolls over” and goes back to the first
Register Address.
FN6691.4
May 1, 2014
ISL29023
SCL FROM
MASTER
8th CLk
9th CLk
HIGH IMPEDANCE
SDA FROM
TRANSMITTER
SDA FROM
RECEIVER
DATA
STABLE
START
DATA
CHANGE
DATA
STABLE
ACK
STOP
FIGURE 12. START, DATA STABLE, ACKNOWLEDGE, AND STOP CONDITION
S
T
A
R
T
SIGNAL FROM
MASTER DEVICE
DEVICE ADDRESS
WRITE
1
SIGNAL AT SDA
0
0
0
1
0
0
S
T
A
R
T
ADDRESS BYTE
0
1
A
C
K
SIGNALS FROM
SLAVE DEVICE
DEVICE ADDRESS
READ
0
0
0
1
0
A
C
K
0
DATA BYTE
S
T
O
P
1
A
C
K
FIGURE 13. BYTE ADDRESS READ SEQUENCE
Read Operation
ISL29023 has two basic read operations: Byte Read and Burst
Read.
BYTE READ
Byte read operations allow the master to access any register
location in the ISL29023. The Byte read operation is a two step
process. The master issues the START condition and the Device
Address byte with the R/W bit set to “0”, receives an
acknowledge, then issues the Register Address byte. After
acknowledging receipt of the register address byte, the master
immediately issues another START condition and the Device
Address byte with the R/W bit set to “1”. This is followed by an
acknowledge from the device and then by the 8-bit data word.
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition (See Figure
13).
BURST READ
Burst read operation is identical to the Byte Read operation.
After the first Data byte is transmitted, the master now responds
SIGNAL FROM
MASTER DEVICE
S
T
A DEVICE ADDRESS
WRITE
R
T
SIGNAL AT SDA
1 0 0 0 1 0 0 0
For more information about the I2C standard, please consult the
Phillips™ I2C specification documents.
Power On Reset
The Power-On Reset (POR) circuitry protects the internal logic
against powering up in the incorrect state. The ISL29023 will
power-up into Standby mode after VDD exceeds the POR trigger
level and will power-down into Reset mode when VDD drops
below the POR trigger level. This bidirectional POR feature
protects the device against ‘brown-out’ failure following a
temporary loss of power.
The POR is an important feature because it prevents the
ISL29023 from starting to operate with insufficient voltage, prior
to stabilization of the internal bandgap. The ISL29023 prevents
communication to its registers and greatly reduces the likelihood
of data corruption on power-up.
S
T
A DEVICE ADDRESS
READ
R
T
ADDRESS BYTE
DATA BYTE 2
DATA BYTE 1
S
T
O
P
DATA BYTE n
1 0 0 0 1 0 0 1
A
C
K
SIGNALS FROM
SLAVE DEVICE
with an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding with
an acknowledge but issuing a STOP condition (See Figure 14).
A
C
K
A
C
K
A
C
K
A
C
K
(“n” is any integer
greater than 1)
FIGURE 14. BURST READ SEQUENCE
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May 1, 2014
ISL29023
TABLE 1. REGISTER MAP
REGISTER ADDRESS
REGISTER BitS
NAME
DEC
HEX
B7
B6
B5
COMMAND-I
0
0x00
OP2
OP1
OP0
COMMAND-II
1
0x01
DATALSB
2
0x02
D7
D6
D5
DATAMSB
3
0x03
D15
D14
INT_LT_LSB
4
0x04
TL7
INT_LT_MSB
5
0x05
INT_HT_LSB
6
INT_HT_MSB
TEST
B2
B1
B0
HEX
FLAG
PRST1
PRST0
00h
RES1
RES0
RANGE1
RANGE0
00h
D4
D3
D2
D1
D0
00h
D13
D12
D11
D10
D9
D8
00h
TL6
TL5
TL4
TL3
TL2
TL1
TL0
00h
TL15
TL14
TL13
TL12
TL11
TL10
TL9
TL8
00h
0x06
TH7
TH6
TH5
TH4
TH3
TH2
TH1
TH0
FFh
7
0x07
TH15
TH14
TH13
TH12
TH11
TH10
TH9
TH8
FFh
8
0x08
0
0
0
0
0
0
0
0
00h
All the functionalities of the device are controlled by the
registers. The ADC data can also be read. The following sections
explain the details of each register bit. All RESERVED bits must
be set to zero, unless otherwise specified.
Decimal to Hexadecimal Conversion
To convert decimal value to hexadecimal value, divide the
decimal number by 16, and write the remainder on the side as
the least significant digit. This process is continued by dividing
the quotient by 16 and writing the remainder until the quotient is
0. When performing the division, the remainders, which will
represent the hexadecimal equivalent of the decimal number,
are written beginning at the least significant digit (right) and
each new digit is written to the next more significant digit (the
left) of the previous digit. Consider the number 175 decimal.
TABLE 2. DECIMAL TO HEXADECIMAL
DIVISION
QUOTIENT
REMINDER
HEX NUMBER
175/16
10 = A
15 = F
0xAF
Command-I Register (Address: 0x00)
TABLE 3. COMMAND-I REGISTER ADDRESS
REGISTER BITS
B6
B5 B4 B3
COMMANDI 0x00 OP2 OP1 OP0 0
B2
B1
B0
DFLT
(Hex)
0 FLAG PRST1 PRST0 0x00
The Command-I register consists of control and status bits. In
this register, there are two interrupt persist bits, one interrupt
status bit, and three operation mode bits. The operation mode
bits and the interrupt persist bits are independent of each other.
The default register value is 0x00 at power on.
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RESERVED
INTERRUPT PERSIST BITS (B0 - B1)
Following are detailed descriptions of the control registers
related to the operation of the ISL29023 ambient light sensor
device. These registers are accessed by the I2C serial interface.
For details on the I2C interface, refer to “Serial Interface” on
page 6.
NAME
B3
RESERVED
Register Description
Reg.
Addr
(Hex) B7
B4
DEFAULT
The interrupt persist bits provides control over when interrupts
occur. There are four different selections for this feature. A value
of n (where n is 1, 4, 8, and 16) results in an interrupt only if the
value remains outside the threshold window for n consecutive
integration cycles. For example, if n is equal to 16 and the ADC
resolution is set to 16-bits then the integration time is 100ms. An
interrupt is generated whenever the last conversion results in a
value outside of the programmed threshold window. The
interrupt is active-low and remains asserted until cleared by
writing the COMMAND register with the CLEAR bit set. Table 4
lists the possible interrupt persist bits.
TABLE 4. INTERRUPT PERSIST BITS
B1
B0
NUMBER OF INTEGRATION CYCLES (n)
0
0
1
0
1
4
1
0
8
1
1
16
INTERRUPT FLAG BIT (B2)
The interrupt flag bit is a status bit for light intensity detection.
The bit is set to logic HIGH when the light intensity crosses the
interrupt thresholds window (register address 0x04 - 0x07), and
set to logic LOW when its within the interrupt thresholds window.
Once the interrupt is triggered, the INT pin goes low and the
interrupt status bit goes HIGH until the status bit is polled
through the I2C read command. Both the INT pin and the
interrupt status bit are automatically cleared at the end of the
8-bit Device Register byte (0x00) transfer. Table 5 shows interrupt
flag states.
TABLE 5. INTERRUPT FLAG BIT
BIT 2
OPERATION
0
Interrupt is cleared or not triggered yet
1
Interrupt is triggered
FN6691.4
May 1, 2014
ISL29023
OPERATION MODE BITS (B5 - B7)
.
ISL29023 has different operating modes. These modes are
selected by setting B5 - B7 bits on register address 0x00. The
device powers up on a disable mode. Table 6 lists the possible
operating modes.
TABLE 6. OPERATING MODES BITS
B6
B5
0
0
0
Power-down the device (Default)
0
0
1
The IC measures ALS only once every
integration cycle. This is the lowest
operating mode.
1
OPERATION
0
B3
B2
NUMBER OF CLOCK CYCLES
n-BIT ADC
0
0
216
0
1
212 = 4,096
1
0
28 = 256
8
1
24
4
1
B7
0
TABLE 9. ADC RESOLUTION DATA WIDTH
= 65,536
16
12
= 16
Data Registers (Addresses: 0x02 and 0x03)
TABLE 10. ADC REGISTER BITS
IR once
NAME
Register Bits
Reg.
Addr
(Hex)
B7
B6
B5
B4
B3
B2
B1
B0
DFLT
(Hex)
D7
D6
D5
D4
D3
0
1
1
Reserved (DO NOT USE)
1
0
0
Reserved (DO NOT USE)
DATALSB 0x02
D2
D1
D0
0x00
1
0
1
The IC measures ALS continuously
DATAMSB 0x03 D15 D14 D13 D12 D11 D10
D9
D8
0x00
1
1
0
The IC measures IR continuous
1
1
1
Reserved (DO NOT USE)
Command-II Register (Address: 0x01)
TABLE 7. COMMAND-II REGISTER BITS
REGISTER BITS
Reg.
Addr
B2
B1
(Hex) B7 B6 B5 B4 B3
NAME
COMMANDII 0x01 0
0
0
B0
DFLT
(Hex)
The ISL29023 has two 8-bit read-only registers to hold the upper
and lower byte of the ADC value. The upper byte is accessed at
address 0x03 and the lower byte is accessed at address 0x02.
For 16-bit resolution, the data is from D0 to D15; for 12-bit
resolution, the data is from D0 to D11; for 8-bit resolution, the
data is from D0 to D7 and 4-bit resolution, the data is from D0 to
D3. The registers are refreshed after every conversion cycle. The
default register value is 0x00 at power-on.
TABLE 11. ADC DATA REGISTERS
0 RES1 RES0 RANGE1 RANGE0 0x00
The Command-II register consists of two dynamic range bits, and
two DAC resolution bits. The default register value is 0x00 at
power-on.
FULL SCALE RANGE (B1-B0)
The Full Scale Range (FSR) has four different selectable ranges.
Each range has a maximum allowable lux value. Higher range
values offer wider ALS lux value. Table 8 lists the possible values
of FSR for the 499kΩ REXT resistor.
ADDRESS
(hex)
D0 is LSB for 4, 8, 12 or 16-bit resolution; D3 is MSB for
4-bit resolution; D7 is MSB for 8-bit resolution
0x03
D15 is MSB for 16-bit resolution; D11 is MSB for 12-bit
resolution
Lower Interrupt Threshold Registers
(Address: 0x04 and 0x05)
TABLE 12. INTERRUPT REGISTER BITS
TABLE 8. RANGE REGISTER BITS
B0
B1
k
RANGE(k)
FSR (LUX) @ ALS
SENSING
FSR @ IR
SENSING
0
0
1
Range1
1,000
65535
0
1
2
Range2
4,000
65535
1
0
3
Range3
16,000
65535
1
1
4
Range4
64,000
65535
ADC RESOLUTION (B3 - B2)
B3 and B2 determine the ADC’s resolution and the number of
clock cycles per conversion. Changing the number of clock cycles
does more than just change the resolution of the device; it also
changes the integration time, which is the period the device’s
analog-to-digital (A/D) converter samples the photodiode current
signal for a measurement. The ONLY 16-bit ADC resolution is
capable of rejecting 50Hz and 60Hz flicker caused by artificial light
sources. Table 9 lists the possible ADC resolution.
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CONTENTS
0x02
Reg.
Addr
(Hex)
REGISTER BITS
DFLT
B1 B0 (Hex)
B7
B6
B5
B4
B3
B2
INT_LT_LSB 0x04 TL7
TL6
TL5
TL4
TL3
TL2 TL1 TL0 0x00
NAME
INT_LT_MSB 0x05 TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 0x00
The lower interrupt threshold registers are used to set the lower
trigger point for interrupt generation. If the ALS value crosses
below or is equal to the lower threshold, an interrupt is asserted
on the interrupt pin and the interrupt flag. Registers INT_LT_LSB
(0x04) and INT_LT_MSB (0x05) provide the low and high bytes,
respectively, of the lower interrupt threshold. The high and low
bytes from each set of registers are combined to form a 16-bit
threshold value. The interrupt threshold registers default to 0x00
upon power-up.
FN6691.4
May 1, 2014
ISL29023
Upper Interrupt Threshold Registers
(Address: 0x06 and 0x07)
where n is the number of bits of resolution and n = 4, 8, 12 or 16.
Therefore, 2n is the number of clock cycles. n can be programmed
at the command register 01(hex) bits 3 and 2.
TABLE 13. INTERRUPT REGISTER BITS
Reg.
Addr
(Hex)
TABLE 14. INTEGRATION TIME OF n-BIT ADC
REGISTER BITS
DFLT
B1 B0 (Hex)
B7
B6
B5
B4
B3
B2
INT_HT_LSB 0x06 TH7
TH6
TH5
TH4
TH3
TH2 TH1 TH0 0xFF
NAME
INT_HT_MSB 0x07 TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 0xFF
The upper interrupt threshold registers are used to set the upper
trigger point for interrupt generation. If the ALS value crosses
above or is equal to the upper threshold, an interrupt is asserted
on the interrupt pin and the interrupt flag. Registers INT_HT_LSB
(0x06) and INT_HT_MSB (0x07) provide the low and high bytes,
respectively, of the upper interrupt threshold. The high and low
bytes from each set of registers are combined to form a 16-bit
threshold value. The interrupt threshold registers default to 0xFF
on power-up.
Test Register (08 hex)
Register 8 is a reserved register that holds 00h during normal
operation.
Applications Information
The ISL29023’s ADC output codes, DATA, are directly
proportional to lux in the ambient light sensing.
(EQ. 1)
Here, Ecal is the calculated lux reading. The constant  is
determined by the Full Scale Range and the ADC’s maximum
output counts. The constant is independent of the light sources
(fluorescent, incandescent and sunlight) because the light
sources’ IR component is removed during the light signal
process. The constant can also be viewed as the sensitivity (the
smallest lux measurement the device can measure).
Range  k 
 = ---------------------------Count max
(EQ. 2)
Here, Range(k) is defined in Table 8. Countmax is the maximum
output counts from the ADC.
The transfer function used for n-bits ADC becomes:
Range  k 
E cal = ---------------------------  DATA
n
2
n = 16-BIT
n = 12-BIT
n = 8-BIT
n = 4-BIT
499**
90ms
5.6ms
352µs
22µs
**Recommended REXT resistor value
External Scaling Resistor REXT for fOSC and
Range
The ISL29023 uses an external resistor REXT to fix its internal
oscillator frequency fOSC and the light sensing range, Range. fOSC
and Range are inversely proportional to REXT. For user simplicity,
the proportionality constant is referenced to 499kΩ:
499k
Range = ------------------  Range  k 
R EXT
(EQ. 5)
499k
f OSC = ------------------  725 kHz
R EXT
(EQ. 6)
ADC Output in IR Sensing
The ISL29023’s ADC output codes, DATA, are directly
proportional to the IR intensity received in the IR sensing.
DATA IR =   E IR
Calculating Lux
E cal =   DATA
REXT (kΩ)
(EQ. 3)
Here, n = 4, 8, 12 or 16. This is the number of ADC bits
programmed in the command register. 2n represents the
maximum number of counts possible from the ADC output. Data
is the ADC output stored in the data registers (02 hex and 03
hex).
Integration and Conversion Time
(EQ. 7)
Here, EIR is the received IR intensity. The constant  changes with
the spectrum of background IR noise, such as sunlight and
incandescent light. The  also changes with the ADC’s range and
resolution selections.
VDD Power-up and Power Supply
Considerations
Upon power-up, please ensure a VDD slew rate of 0.5V/ms or
greater. For more information, see application note AN1534.
Noise Rejection
Electrical AC power worldwide is distributed at either 50Hz or
60Hz. Artificial light sources vary in intensity at the AC power
frequencies. The undesired interference frequencies are infused
on the electrical signals. This variation is one of the main sources
of noise for the light sensors. Integrating type ADC’s have
excellent noise-rejection characteristics for periodic noise
sources whose frequency is an integer multiple of the conversion
rate. By setting the sensor’s integration time to an integer
multiple of periodic noise signal, the performance of an ambient
light sensor can be improved greatly in the presence of noise. In
order to reject the AC noise, the integration time of the sensor
must to adjusted to match the AC noise cycle. For instance, a
60Hz AC unwanted signal’s sum from 0ms to k*16.66ms
(k = 1,2...ki) is zero. Similarly, setting the device’s integration
time to be an integer multiple of the periodic noise signal greatly
improves the light sensor output signal in the presence of noise.
The ADC resolution and fOSC determine the integration time, tint.
R EXT
n
n
1
t int = 2  -------------- = 2  ---------------------------------------------725kHz  499k
f OSC
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(EQ. 4)
FN6691.4
May 1, 2014
ISL29023
Suggested PCB Footprint
Temperature Coefficient
It is important that users check the “Surface Mount Assembly
Guidelines for Optical Dual Flat Pack No Lead (ODFN) Package”
before starting ODFN product board mounting, see TB477.
The limits stated for temperature coefficient (TC) are governed by
the method of measurement. The “Box” method is usually used
for specifying the temperature coefficient. The overwhelming
standard for specifying the temperature drift of a reference is to
evaluate the maximum voltage change over the specified
temperature range. This yields ppm/°C, and is calculated using
Equation 8:
Board Mounting Consideration
For applications requiring the light measurement, the board
mounting location should be reviewed. The device uses an
Optical Dual Flat Pack No Lead (ODFN) package, which subjects
the die to mild stresses when the printed circuit (PC) board is
heated and cooled, which slightly changes the shape. Because of
these die stresses, placing the device in areas subject to slight
twisting can cause degradation of reference voltage accuracy. It
is normally best to place the device near the edge of a board, or
on the shortest side, because the axis of bending is most limited
in that location.
Layout Considerations
The ISL29023 is relatively insensitive to layout. Like other I2C
devices, it is intended to provide excellent performance even in
significantly noisy environments. There are only a few
considerations that will ensure best performance.
Route the supply and I2C traces as far as possible from all
sources of noise. Use two power-supply decoupling capacitors,
1µF and 0.1µF, placed close to the device. REXT must be placed
as closely to the pin as possible to eliminate the stray
capacitance, which will greatly affect the performance of the
sensor.
Soldering Considerations
Convection heating is recommended for reflow soldering;
direct-infrared heating is not recommended. The plastic ODFN
package does not require a custom reflow soldering profile, and
is qualified to +260°C. A standard reflow soldering profile with a
+260°C maximum is recommended.
V HIGH – V LOW
6
TC = ----------------------------------------------------------------------------------  10
V NOMINAL   T HIGH – T LOW 
(EQ. 8)
where:
VHIGH is the maximum reference voltage over the temperature
range.
VLOW is the minimum reference voltage over the temperature
range.
VNOMINAL is the nominal reference voltage at +25°C.
THIGH - TLOW is the specified temperature range (°C)
Digital Inputs and Termination
The ISL29023 digital inputs are guaranteed to CMOS levels. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital inputs
are 50Ω lines, then 50Ω termination resistors should be placed
as close to the sensor inputs as possible, connected to the digital
ground plane (if separate grounds are used).
Typical Circuit
A typical application for the ISL29023 is shown in Figure 1. The
ISL29023’s I2C address is internally hard-wired as 1000100. The
device can be tied onto a system’s I2C bus together with other I2C
compliant devices.
1.7V TO 3.63V
R1
R2
I2C MASTER
R3
MICROCONTROLLER
SDA
SCL
INT
2.25V TO 3.63V
I2C SLAVE_0
1
2
C1
10µF
C2
0.1µF
3
REXT
499k
VDD
SDA
GND
SCL
REXT
INT
I2C SLAVE_1
I2C SLAVE_n
6
SDA
SDA
5
SCL
SCL
4
ISL29023
FIGURE 15. ISL29023 TYPICAL SYSTEM DIAGRAM
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SENSOR OFFSET
ISL29023
1
6
2
5
0.40
0.54
4
3
0.37
FIGURE 16. 6-LD ODFN SENSOR LOCATION OUTLINE
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ISL29023
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
May 1, 2014
FN6691.4
Related Literature on page 1, “VDD Power-up and Power Supply Considerations” on page 10, and the
explanation at Table 7 on page 9 were added.
Updated “Temperature Coefficient” on page 11.
April 16, 2013
FN6691.3
ESD Specification Added
November 21, 2012
FN6691.2
Corrected part number in "Ordering Information" on page 2 from ISL29023IROZ-T7S2378 to ISL29023IROZ-T7
Updated TJA on page 3 from 90 to 88.
May 14, 2012
FN6691.1
I2C section and Register description explained in more detail.
March 3, 2009
FN6691.0
Initial Release
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FN6691.4
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ISL29023
Package Outline Drawing
L6.2x2.1
6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN)
Rev 3, 5/11
2.10
A
6
PIN #1
INDEX AREA
B
6
PIN 1
INDEX AREA
1
0.65
1.35
2.00
1.30 REF
4 6X 0.30±0.05
(4X)
0.10
0.10 M C A B
0.65
TOP VIEW
6x0.35 ± 0.05
BOTTOM VIEW
2.50
PACKAGE
OUTLINE
2.10
SEE DETAIL "X"
0.65
(4x0.65)
0.10 C
MAX 0.75
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(1.35)
(6x0.30)
C
(6x0.20)
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
(6x0.55)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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