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ISL3034E, ISL3035E, ISL3036E
March 31, 2009
FN6492.0
4-Channel And 6-Channel High Speed,
Auto-direction Sensing Logic Level
Translators
Features
The ISL3034E, ISL3035E, ISL3036E 4- and 6-channel
bi-directional, auto-direction sensing, level translators
provide the required level shifting in multi-voltage systems at
data transfer rates up to 100Mbps. The auto-direction
sensing feature makes the ISL3034E, ISL3035E, ISL3036E
ideally suited for memory-card level translation (or for
generic four to six channel level translation) especially if
bit-by-bit direction control is desired. The VCC and VL supply
voltages set the logic levels on either side of the device.
Logic signals present on the IC’s VL side appear as higher
voltage logic signals on the IC’s VCC side and vice versa.
The ISL3035E features a CLK_RET output that returns the
same clock signal applied to the CLK_VL input, but with
timing that mimics the data returning from the I/OVCC inputs.
• 100Mbps Guaranteed Data Rate
The ISL3034E, ISL3035E, ISL3036E operate at full speed
with external input drivers that source as little as 4mA output
current. Each I/O channel is pulled up to VCC or VL by an
internal 30µA current source, allowing the ISL3034E,
ISL3035E, ISL3036E to be driven by either push-pull or
open-drain drivers.
The ISL3034E and ISL3036E include an enable (EN) input
that when driven low places the IC into a low-power
shutdown mode, with all I/O lines tri-stated. All versions
feature an automatic shutdown mode, that places the part in
the same shutdown state when VCC is less than VL. The
states of I/OVCC and I/OVL during shutdown are chosen by
selecting the appropriate product (see Table 1).
The ISL3034E, ISL3035E, ISL3036E operate with VCC
voltages from +2.2V to +3.6V and VL voltages from +1.35V
to +3.2V, making them ideal for data transfer between
low-voltage microcontrollers or ASICs and higher voltage
components.
• Best-In-Class ESD Protection: ±15kV IEC61000-4-2 ESD
Protection on ALL Input, Output, and I/O Lines
• Four (ISL3036) or Six (ISL3034, ISL3035) Bi-directional
Channels
• Auto-direction Sensing Eliminates Direction Control Logic
Pins
• Enable Input (ISL3034E, ISL3036E) for Logic Control of
Low Power SHDN Mode
• Clock Return Output (ISL3035E)
• Compatible with 4mA Input Drivers or Larger
• +1.35V ≤ VL ≤ +3.2V and +2.2V ≤ VCC ≤ +3.6V Supply
Voltage Range
• Pb-Free (RoHS Compliant)
• 16Ld µTQFN (2.6mmx1.8mm), 16 Ld TQFN (3mmx3mm),
and 14 Ld QFN (3.5mmx3.5mm) Packages
Applications
• Simplifies the Interface Between Two Logic ICs Operating
at Different Supply Voltages
• SD Card and MiniSD Card Level Translation
• MMC (Multi Media Card) Level Translation
• Memory Stick Card Level Translation
Typical Operating Circuit
+1.8V
+1.8V
SYSTEM
CONTROLLER
I/OVLSHDN
STATE
I/OVCC
DAT3
I/OVL
I/OVCC
DAT2
I/OVCC
SHDN
STATE
DAT1
I/OVL
I/OVCC
DAT1
DAT0
I/OVL
I/OVCC
DAT0
CMD
I/OVL
I/OVCC
CMD
CLOCK
CLOCK_IN
6
YES
16.5kΩ
to VL
16.5kΩ
to VCC
ISL3035E
100
6
NO
75kΩ to VL
High
Impedance
16.5kΩ
to VL
16.5kΩ
to VCC
4
YES
1
+3.3V
SD CARD
I/OVL
100
100
VL
VCC
ISL3035E
1µF
DAT2
ISL3034E
ISL3036E
0.1µF
DAT3
TABLE 1. SUMMARY OF FEATURES
NUMBER
DATA
OF
EN
RATE
PART
NUMBER (Mbps) CHANNELS PIN?
+3.3V
0.1µF
GND
CLK_VLCLK_VCC
CLK_RET
GND
CLOCK
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL3034E, ISL3035E, ISL3036E
Ordering Information
PART
NUMBER
PART
MARKING
ISL3034EIRTZ (Note 1)
34TZ
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
PKG.
DWG. #
16 Ld TQFN
L16.3x3A
ISL3034EIRTZ-T (Notes 1, 3)
34TZ
-40 to +85
16 Ld TQFN
L16.3x3A
ISL3034EIRUZ-T (Notes 2, 3)
GAE
-40 to +85
16 Ld µTQFN
L16.2.6x1.8A
ISL3035EIRTZ (Note 1)
35TZ
-40 to +85
16 Ld TQFN
L16.3x3A
ISL3035EIRTZ-T (Notes 1, 3)
35TZ
-40 to +85
16 Ld TQFN
L16.3x3A
ISL3035EIRUZ-T (Notes 2, 3)
GAF
-40 to +85
16 Ld µTQFN
L16.2.6x1.8A
ISL3036EIRZ-T (Notes 1, 3)
36EZ
-40 to +85
14 Ld QFN
L14.3.5x3.5
ISL3036EIRUZ-T (Notes 2, 3)
GAK
-40 to +85
16 Ld µTQFN
L16.2.6x1.8A
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Please refer to TB347 for details on reel specifications.
Pinouts
13 GND
14 I/OVCC6
I/OVL1 1
12 I/OVL6
10 I/OVL5
VL 2
9 I/OVL4
I/OVL2 3
10 I/OVL5
I/OVL3 4
9 I/OVL4
I/OVCC5 8
11 EN
I/OVCC4 7
I/OVCC4 7
2
I/OVCC5 8
I/OVCC2 5
I/OVCC3 6
I/OVL3 4
11 EN
I/OVCC3 6
I/OVL2 3
12 I/OVL6
THERMAL
PAD
I/OVCC2 5
VL 2
16 VCC
13 GND
14 I/OVCC6
15 I/OVCC1
16 VCC
I/OVL1 1
15 I/OVCC1
ISL3034E
(16 LD ΜTQFN)
TOP VIEW
ISL3034E
(16 LD TQFN)
TOP VIEW
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Pinouts (Continued)
10 I/OVL5
13 I/OVCC1
I/OVL2 3
12 I/OVCC2
11 I/OVCC3
I/OVL4 5
10 I/OVCC4
7
8
GND
EN
9
13 VCC
14 NC
I/OVL2 2
11 I/OVCC2
I/OVL3 3
10 I/OVCC3
I/OVL4 4
9 I/OVCC4
NC
GND 5
NC 6
12 I/OVCC1
EN 8
THERMAL
PAD
I/OVL3 4
I/OVL1 1
NC 7
VCC
I/OVL1 2
15 NC
ISL3036E
(16 LD ΜTQFN)
TOP VIEW
16 VL
VL
14
13 GND
9 I/OVL4
I/OVCC4 7
I/OVL3 4
I/OVCC3 6
10 I/OVL5
ISL3036E
(14 LD QFN)
TOP VIEW
1
11 CLK_RET
I/OVL2 3
I/OVCC2 5
I/OVCC5 8
I/OVCC4 7
I/OVCC2 5
9 I/OVL4
I/OVCC3 6
I/OVL3 4
12 CLK_VL
VL 2
NC 6
I/OVL2 3
I/OVL1 1
11 CLK_RET
THERMAL
PAD
I/OVCC5 8
12 CLK_VL
VL 2
14 CLK_VCC
16 VCC
13 GND
14 CLK_VCC
15 I/OVCC1
16 VCC
I/OVL1 1
15 I/OVCC1
ISL3035E
(16 LD ΜTQFN)
TOP VIEW
ISL3035E
(16 LD TQFN)
TOP VIEW
Pin Descriptions
NAME
VCC
VL
GND
EN
I/OVCCx
CLK_VCC
I/OVLx
CLK_VL
CLK_RET
FUNCTION
NOTES
VCC power supply, +2.2V to +3.6V. Decouple VCC to ground with a 0.1µF capacitor.
For normal operation, VCC > VL.
VL logic supply, +1.35V to +3.2V. Decouple VL to ground with a 0.1µF capacitor.
For normal operation, VCC > VL.
Ground Pin
±15kV IEC61000 ESD Protected Enable Input. Logic “0” puts the device in shutdown. Logic
“1” enables the device.
ISL3034E and ISL3036E only
±15kV IEC61000 ESD Protected Input/Output channel referenced to VCC.
±15kV IEC61000 ESD Protected Input/Output clock channel referenced to VCC.
ISL3035E only
±15kV IEC61000 ESD Protected Input/Output channel referenced to VL.
IEC61000 ESD Protected Input clock channel referenced to VL.
ISL3035E only
IEC61000 ESD Protected Output clock channel referenced to VL.
ISL3035E only
3
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Absolute Maximum Ratings
Thermal Information
(All voltages referenced to GND.)
VCC, VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
I/OVCC_, CLK_VCC . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V)
I/OVL_, CLK_VL, CLK_RET. . . . . . . . . . . . . . . -0.3V to (VL + 0.3V)
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
Short-Circuit Duration I/OVL_, I/OVCC_, CLK_VCC,
CLK_RET to GND. . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Thermal Resistance (Typical)
Operating Conditions
θJA (°C/W)
θJC (°C/W)
14 Ld QFN Package (Notes 4, 5). . . . .
46
6
16 Ld TQFN Package (Notes 4, 5). . . .
74
10
16 Ld µTQFN Package (Note 4) . . . . .
93
44
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Temperature Range . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air, and with “direct attach” features for
the QFN and TQFN. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VCC = +2.2V to +3.6V, VL = +1.35V to +3.2V, EN = VL, unless otherwise noted. Typical values are at
VCC = +3.3V, VL = +1.8V and TA = +25°C. (Note 6).
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
POWER SUPPLIES
VL Supply Range
VL
(Note 6)
Full
1.35
-
3.2
V
VCC Supply Range
VCC
(Note 6)
Full
2.2
-
3.6
V
VCC Quiescent Supply Current
ICC
I/OVCC = VCC, I/OVL = VL
Full
-
18
30
µA
VL Quiescent Supply Current
IVL
I/OVCC = VCC, I/OVL = VL
Full
-
12
18
µA
EN = GND or VL > VCC + 0.7V; ISL3034E and
ISL3036E Only
Full
-
-
2.5
µA
VL > VCC + 0.7V; ISL3035E Only
Full
-
-
2.5
µA
EN = GND or VL > VCC + 0.7V; ISL3034E and
ISL3036E Only
Full
-
-
4
µA
VL > VCC + 0.7V; ISL3035E Only
Full
-
-
4
µA
VL > VCC + 0.7V, VO = 0V or VCC, ISL3035E Only
Full
-
0.1
2
µA
1
µA
VCC Shutdown Supply Current
ICCSD
VL Shutdown Supply Current
ILSD
I/OVCC, CLK_VCC Tri-State
Leakage Current
ILKG
EN Input Current
IIN_EN
ISL3034E and ISL3036E Only
Full
-
VL - VCC Shutdown Threshold
High
VTH_H
VCC rising
Full
-0.2
0.05VL
0.7
V
VL - VCC Shutdown Threshold
Low
VTH_L
VCC falling
Full
-0.2
0.1VL
0.7
V
I/OVCC, I/OVL Pull-up
Resistance During Shutdown
RPU_SD1 EN = GND; ISL3034E and ISL3036E Only
Full
10
16.5
23
kΩ
I/OVL, CLK_VL , CLK_RET
Pull-up Resistance During
Shutdown
RPU_SD2 VL > (VCC + 0.7V); ISL3035E Only
Full
45
75
105
kΩ
Full
20
-
75
µA
Full
20
-
75
µA
Full
-
3
-
kΩ
I/OVL_, CLK_VL, CLK_RET Pullup Current
I/OVCC_, CLK_VCC Pull-up
Current
IVL_PU
EN = VL, I/OVL = GND
IVCC_PU EN = VL, I/OVCC = GND
I/OVL to I/OVCC DC Resistance
RON
4
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Electrical Specifications
VCC = +2.2V to +3.6V, VL = +1.35V to +3.2V, EN = VL, unless otherwise noted. Typical values are at
VCC = +3.3V, VL = +1.8V and TA = +25°C. (Note 6). (Continued)
PARAMETER
TEMP
(°C)
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
IEC61000-4-2 Air-Gap Discharge
25
-
±15
-
kV
IEC61000-4-2 Contact Discharge
25
-
>±9
-
kV
Human Body Model
25
-
±15
-
kV
HBM, per JEDEC
25
-
>±12
-
kV
Machine Model, per JEDEC
25
-
±1300
-
V
SYMBOL
TEST CONDITIONS
ESD PROTECTION
All Input and I/O Pins From Pin to
GND
All Pins
LOGIC-LEVEL THRESHOLDS
I/OVL, CLK_VL Input Voltage
High Threshold
VIHL
(Note 7)
Full
-
-
VL - 0.2
V
I/OVL, CLK_VL Input Voltage
Low Threshold
VILL
(Note 7)
Full
0.15
-
-
V
I/OVCC, CLK_VCC Input Voltage
High Threshold
VIHC
(Note 7)
Full
-
-
VCC - 0.4
V
I/OVCC, CLK_VCC Input Voltage
Low Threshold
VILC
(Note 7)
Full
0.2
-
-
V
EN Input Voltage High Threshold
VIH
Full
-
-
VL - 0.4
V
EN Input Voltage Low Threshold
VIL
Full
0.4
-
-
V
I/OVL, CLK_RET Output Voltage
High
VOHL
IOH = 20µA, I/OVCC ≥ VCC - 0.4V
Full
2/3 VL
-
-
V
I/OVL, CLK_RET Output Voltage
Low
VOLL
IOL = 20µA, I/OVCC ≤ 0.2V
Full
-
-
1/3 VL
V
I/OVCC, CLK_VCC Output
Voltage High
VOHC
IOH = 20µA, I/OVL ≥ VL - 0.2V
Full
2/3 VCC
-
-
V
I/OVCC, CLK_VCC Output
Voltage Low
VOLC
IOL = 20µA, I/OVL ≤ 0.15V
Full
-
-
1/3 VCC
V
On falling edge
25
-
3
-
ns
On rising edge
25
-
3
-
ns
I/OVL, CLK_RET Output
Accelerator Source Impedance
VL = 1.62V
25
-
11
-
Ω
VL = 3.2V
25
-
6
-
Ω
I/OVCC, CLK_VCC Output
Accelerator Source Impedance
VCC = 2.2V
25
-
9
-
Ω
VCC = 3.6V
25
-
8
-
Ω
I/OVL, CLK_RET Output
Accelerator Sink Impedance
VL = 1.62V
25
-
9
-
Ω
VL = 3.2V
25
-
8
-
Ω
I/OVCC, CLKVCC Output
Accelerator Sink Impedance
VCC = 2.2V
25
-
10
-
Ω
VCC = 3.6V
25
-
9
-
Ω
RISE/FALL TIME ACCELERATOR STAGE
Accelerator Pulse Duration
TIMING CHARACTERISTICS (RSOURCE = 150Ω, Input rise/fall time ≤ 1ns)
I/OVCC, CLK_VCC Rise Time
tRVCC
RS = 150Ω, CI/OVCC = 10pF, CCLK_VCC = 10pF,
push-pull drivers
Full
-
-
3.2
ns
I/OVCC, CLK_VCC Fall Time
tFVCC
RS = 150Ω, CI/OVCC = 10pF, CCLK_VCC = 10pF
Full
-
-
3.2
ns
I/OVL, CLK_RET Rise Time
tRVL
RS = 150Ω, CI/OVL = 15pF,
VL ≥ 1.35V
CCLK_RET = 15pF, push-pull drivers
VL ≥ 1.62V
Full
-
-
4
ns
Full
-
-
3.5
ns
5
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Electrical Specifications
VCC = +2.2V to +3.6V, VL = +1.35V to +3.2V, EN = VL, unless otherwise noted. Typical values are at
VCC = +3.3V, VL = +1.8V and TA = +25°C. (Note 6). (Continued)
PARAMETER
SYMBOL
I/OVL, CLK_RET Fall Time
tFVL
I/OVCC, CLK_VCC Propagation
Delay (Driving I/OVL, CLK_VL)
tPDVCC
tPDVCC Channel-to-Channel
Skew (Note 9)
tSKEWC
I/OVL, CLK_RET Propagation
Delay (Driving I/OVCC,
CLK_VCC)
tPDVL
tPDVL Channel-to-Channel Skew
(Note 9)
tSKEWL
Delay from EN High to I/OVCC
Active
tEN-VCC
tEN-VL
Delay from EN High to I/OVL
Active
Maximum Data Rate
D.R.1.35
D.R.1.6
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
RS = 150Ω, CI/OVL = 15pF,
CCLK_RET = 15pF
VL ≥ 1.35V
Full
-
-
4
ns
VL ≥ 1.62V
Full
-
-
3.5
ns
RS = 150Ω, CI/OVCC = 10pF,
CCLK_VCC = 10pF, push-pull
drivers
VL ≥ 1.35V
Full
-
-
7.5
ns
VL ≥ 1.62V
Full
-
-
6.5
ns
VL ≥ 1.35V
Full
-
-
1.3
ns
VL ≥ 1.62V
Full
-
-
1
ns
Full
-
-
6.5
ns
VL ≥ 1.35V
Full
-
-
1.3
ns
VL ≥ 1.62V
Full
-
-
0.8
ns
RLOAD = 1MΩ, CI/OVCC = 10pF (ISL3034E and
ISL3036E)
25
-
1.5
-
µs
RLOAD = 1MΩ, CI/OVL = 15pF (ISL3034E and
ISL3036E)
25
-
1.5
-
µs
VL ≥ 1.35V
Full
85
-
-
Mbps
VL ≥ 1.62V
Full
100
-
-
Mbps
RS = 150Ω, CI/OVL = 15pF, CCLK_RET = 15pF,
push-pull drivers
Push-pull operation,
RSOURCE = 150Ω,
CI/OVCC = 10pF, CI/OVL = 15pF,
CCLK_VCC = 10pF,
CCLK_RET = 15pF
NOTES:
6. VL must be less than or equal to VCC - 0.2V during normal operation. However, VL can be greater than VCC during start-up and shutdown
conditions and the part will not latch-up nor be damaged.
7. Input thresholds are referenced to the boost circuit.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Delta between all I/OVL channel prop delays, or delta between all I/OVCC channel prop delays, all channels tested at the same test conditions.
Test Circuits and Waveforms
VL
EN
VL
I/OVL
VCC
0V
tPHL
tPLH
I/OVCC
I/OVL
I/OVCC
150Ω
CL
SIGNAL
GENERATOR
VL
50%
50%
50%
10%
90%
90%
tRVCC
VOH
50%
10%
VOL
tFVCC
tPDVCC = tPLH or tPHL
FIGURE 1A. TEST CIRCUIT
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. I/OVCC OUTPUT PROPAGATION DELAY AND TRANSITION TIMES (PUSH - PULL)
6
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Test Circuits and Waveforms (Continued)
VL
EN
VCC
I/OVCC
VL
VCC
50%
50%
0V
tPHL
tPLH
I/OVL
I/OVCC
I/OVL
150Ω
90%
VOH
50%
10%
tRVL
CL
SIGNAL
GENERATOR
90%
50%
10%
VOL
tFVL
tPDVL = tPLH or tPHL
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. I/OVL OUTPUT PROPAGATION DELAY AND TRANSITION TIMES (PUSH - PULL)
VL
EN
EN
VL
SIGNAL
GENERATOR
50%
0V
VCC
tENL
VCC
GND
I/OVCC
I/OVL
1MΩ
SW1
VCC
SW2
GND
VCC
I/OVCC
50%
OUTPUT LOW
PARAMETER
SW1
SW2
tENL
GND
VCC
tENH
VCC
GND
tENH
OUTPUT HIGH
50%
I/OVCC
tEN-VCC = tENL OR tENH
VOL
VOH
0V
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. I/OVCC OUTPUT ENABLE TIMES
VCC
EN
EN
VCC
SIGNAL
GENERATOR
50%
0V
VL
tENL
VL
GND
I/OVCC
I/OVL
1MΩ
SW1
VL
VL
SW2
GND
I/OVL
50%
OUTPUT LOW
PARAMETER
SW1
SW2
tENL
GND
VL
tENH
VL
GND
tENH
OUTPUT HIGH
50%
I/OVL
tEN-VL = tENL OR tENH
FIGURE 4A. TEST CIRCUIT
VOL
VOH
0V
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. I/OVL OUTPUT ENABLE TIMES
7
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Application Information
VL
Overview
The ISL3034E, ISL3035E, ISL3036E are 100Mbps,
bi-directional voltage level translating ICs for multi-supply
voltage systems. These products shift lower voltage levels
on one interface side (supplied by VL) to a higher voltage
level on the other interface side (supplied by VCC), or vice
versa. VOH of the I/OVL pins tracks the VL supply, while VOH
of the I/OVCC pins tracks the VCC supply.
These ICs feature bit-by-bit auto-direction sensing to
increase flexibility, and to eliminate the need for direction
control pins. On chip pull-up current sources in the active
mode, and pull-up resistors in SHDN mode, eliminate the
need for most external bus resistors. Drivers interfacing with
these level translators may be open-drain or push-pull types,
and all three versions may also be used for unidirectional
level shifting.
The three versions share the same architecture, but the
ISL3034E is a general purpose 6-Channel version, while the
6-Channel ISL3035E specifically targets SD Card and other
memory card applications. The 4-channel ISL3036 targets
nibble and byte based applications, as well as 4-wire SPI
interfaces. Power supply ranges allow level shifting between
1.5V, 1.8V, and 2.5V powered devices on the VL side to
2.5V, and 3.3V devices on the VCC side.
Principles of Operation
When enabled, these level shifters detect transitions on an
I/O pin, and drive the appropriate logic level on the
corresponding I/O pin on the other “side”. If the transition
was low-to-high, the channel shifts the voltage up to VCC (for
transitions on an I/OVL pin) or down to VL (for transitions on
an I/OVCC pin), and then drives the shifted level on the other
side. The ISL3035E enables whenever VCC > VL + 200mV,
while the ISL3034E and ISL3036E enable if EN = 1 AND
VCC > VL + 200mV.
Upon detecting a transition on either I/O pin, that channel’s
accelerator circuitry actively drives the opposite side’s
(output) pin to GND or the output’s supply rail, and then turns
off. Weak hold circuitry then maintains the logic state until
the input is 3-stated, or until another active transition occurs
on either I/O pin for that channel. Figure 5 shows the
simplified block diagram of one level shifting channel. The
accelerator circuitry comprises high and low threshold
detectors, one shots with level shifters and large output
drivers. A transition on one of the I/OVL or I/OVCC pins
momentarily defines that pin as an input. When the high or
low threshold is crossed, a one-shot fires either the PMOS or
NMOS driver, respectively, on the opposite side (effectively
the output). These drivers are large enough to quickly drive
the output node to its respective supply or to GND. Note that
this transition on the “output” trips the transition detector on
that pin, firing its accelerator, which feeds back to the “input”
to help reinforce slow transitions, such as those from an
8
#
HIGH VTH
DETECT
#
LOW VTH
DETECT
VCC
VL
EN
I/OVCC
I/OVL
VCC
HIGH VTH
DETECT
#
LOW VTH
DETECT
#
# ONE-SHOT AND LEVEL SHIFTER
FIGURE 5. ONE CHANNEL SIMPLIFIED SCHEMATIC
open-drain type driver. Once the one-shot - and thus the
accelerator - times out (approximately 3ns to 4ns), the large
output drivers tri-state and the pins are weakly held in the
last state by the small NMOS transistor between I/OVL and
I/OVCC (for a low) or by the small current sources (for a
high). In this static state, the I/O pins are easily overdriven by
the next transition from an external driver. Having large
pull-up and pull-down devices in the accelerator (vs just an
active pull-up) nearly eliminates the concern about the
external driver’s output impedance, and that impedance’s
effect on VOL, fall times and data rate.
The weak pull-up current sources on each I/O pin and the
NMOS pass transistors, remain ON whenever the IC is
enabled. If a channel’s external driver tri-states, the weak
pull-up currents either keep the I/O pins high, or if the last
state was a low the current sources pull the I/O pins high. In
the latter case, each channel’s accelerators will once again
fire when either the I/OVL or the I/OVCC voltage crosses the
accelerator’s high threshold level.
Auto Direction Sensing
Each level translator channel independently and
automatically determines the direction of data transfer
without any external control signals. As described earlier, a
transition on either of the channel’s I/O pins momentarily
defines that pin as an input, which then translates and drives
that input signal to the channel’s corresponding pin on the
other port (now the output). After a brief period of active
driving, both I/O pins return to their weak “hold” mode, where
the next transition on either I/O pin determines the direction
for the next transfer.
Auto sensing saves valuable processor GPIO pins (three
[CLK, CMD, DAT] for SD Card applications, or six for the
general purpose hex case), and simplifies the software
associated with the peripheral interface.
Using Open Drain Drivers
These level translators’ accelerator based architecture
works equally well when driven by push-pull or open drain
type drivers (e.g., for the CMD line initialization in MMC
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
applications). The low static pull-up current is easily
overdriven by an active pull-down, and the feedback nature
of the accelerators (i.e., the accelerator firing in one direction
also triggers the accelerator in the opposite direction) aids
the passive pull-up once the input signal passes the
accelerator’s high threshold. The pull-up current and load
capacitance set the input signal rise time, and thus the
maximum data rate. For slow data rates the internal pull-up
current may suffice, but higher data rates - or more heavily
loaded signal lines - may require an external pull-up resistor.
Using External Bus Resistors
As mentioned earlier, these level translators incorporate I/O
pin pull-up current sources when enabled, and I/O pin
pull-up resistors in SHDN (except for the ISL3035E’s I/OVCC
pins). Therefore, external pull-up or pull-down resistors
shouldn’t be necessary, and aren’t recommended, unless
using high-speed open drain signaling.
Power Supplies
respectively. Both products include SHDN mode 16.5kΩ
pull-ups on the I/OVCC and I/OVL pins.
ISL3035E
+1.8V
+3.3V
1µF
0.1µF
0.1µF
1µF
+1.8V
SYSTEM
CONTROLLER
HOST
DAT3
I/OVL_
I/OVL_
I/OVCC_
I/OVCC_
DAT3
DAT2
DAT1
I/OVL_
I/OVCC_
DAT1
DAT0
I/OVL_
I/OVCC_
DAT0
CMD
I/OVL_
I/OVCC_
CMD
CLOCK
CLOCK_IN
GND
VL
VCC
ISL3035E
CLK_VCC
CLK_VL
+3.3V
SD CARD
DAT2
CLOCK
CLK_RET
GND
GND
WIDE SUPPLY RANGE
These ICs operate from a wide range of supply voltages.
VL is designed to connect to the supply of 1.5V, 1.8V, and
2.5V powered devices, while VCC is targeted for 2.5V, and
3.3V components. Remember that VCC must be greater
than VL for proper operation.
POWER SUPPLY SEQUENCING
Either VCC or VL may be powered up first, but the IC
remains in SHDN until VCC exceeds VL by as much as
200mV. VL may exceed VCC by as much as 4V without
causing any damage.
I/O PIN INPUT THRESHOLDS VS SUPPLY VOLTAGE
Even though the “Electrical Specification” table on page 4
shows the I/O pin input thresholds (VIH, VIL) with a fixed
delta from the supplies or GND, the thresholds are better
represented as a percentage of the supplies. The typical
I/OVCC and CLK_VCC VIH runs about 55% to 60% of VCC,
while the corresponding VIL runs about 33% of VCC. The
typical I/OVL and CLK_VL VIH runs about 60% to 70% of VL,
while the corresponding VIL runs about 25% to 35% of VL.
Low Power SHDN Mode
This family of level translators features a low power SHDN
mode that tri-states all the I/O and output pins, considerably
reduces current consumption, and enables any pull-up
resistors on a port’s I/O pins (see Table 1). The ISL3034E
and ISL3036E enter the SHDN mode when the EN input
switches low, or automatically when the VCC voltage drops
below the VL voltage. The ISL3035 has no enable pin, so it
enters SHDN only if VCC drops below VL. The VL supply
powers the EN circuitry.
ISL3034E and ISL3036E
The ISL3034E and ISL3036E are general purpose level
translators featuring an enable pin, and six or four channels,
9
FIGURE 6. ISL3035E IN AN SD CARD APPLICATION
The ISL3035E specifically targets memory card applications,
and Figure 6 illustrates its use in an SD Card application.
Instead of six general purpose channels, the ISL3035E
features five general purpose channels and one dedicated
CLK channel. In memory card applications, the CLK channel
is a unidirectional signal driven by the host controller and
used by the memory card to synchronize data reads and
writes. The ISL3035E’s CLK channel is unique in that the
host CLK applied to the CLK_VL pin routes to the memory
card via the CLK_VCC pin, but it also loops back to the host
on the CLK_RET pin. This CLK_RET signal better mimics
the timing of “read” data returned from the memory card (see
Figure 21 for signal timing), so using CLK_RET as the host’s
input CLK improves the CLK to data timing relationship.
CLK_RET is strictly an output, and CLK_VL is strictly an
input. If an ISL3035E application needs a sixth I/O channel
then the user needs to connect CLK_VL and CLK_RET
together. Connected this way, the combination channel has the
same architecture as the other I/O channels. Both CLK_RET
and CLK_VL have equivalent pull-up current sources and
SHDN pull-up resistors, so connecting these two pins together
doubles the pull-up current in either mode.
The bit-by-bit auto direction control eliminates the need for
GPIO signals to control the flow of data on the CMD and
DAT lines.
The ISL3035E has no enable pin, so it only enters the low
power SHDN mode when VCC drops below VL. There are no
SHDN pull-up resistors on the I/OVCC and CLK_VCC pins,
but there are 75kΩ pull-ups on the I/OVL, CLK_VL, and
CLK_RET pins.
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Best-in-Class ESD Protection
All pins on these devices include class 3 (>12kV) Human
Body Model (HBM) ESD protection structures, but the input
and I/O pins incorporate advanced structures allowing
them to survive ESD events in excess of ±15kV HBM and
±15kV to IEC61000-4-2. The I/OVCC pins are particularly
vulnerable to ESD damage because they typically connect
to an exposed port on the exterior of the finished product.
Simply touching the port pins, or connecting a memory
card, can cause an ESD event that might destroy
unprotected ICs. These new ESD structures protect the
device whether or not it is powered up and without
degrading the level shifting performance. This built-in ESD
protection eliminates the need for board level protection
structures (e.g., transient suppression diodes) and the
associated, undesirable capacitive load they present. To
ensure the full benefit of the built-in ESD protection,
connect the IC’s GND pin directly to a low impedance GND
plane.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (typically I/OVCC pins in memory card
applications) but the ISL3034E, ISL3035E, and ISL3036E
feature IEC61000 ESD protection on all logic and I/O pins
(both I/OVL and I/OVCC, as well as CLK pins). Unlike HBM
and MM methods which only test each pin-to-pin
combination without applying power, IEC61000 testing is
also performed with the IC in its typical application
Typical Performance Curves
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. All the EN, CLK, and I/O pins withstand
±15kV air-gap discharges, relative to GND.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±9kV. Devices in this family survive ±9kV contact
discharges (relative to the GND pin) on the EN, CLK, and I/O
pins.
Layout and Decoupling Considerations
These level translators’ high data rates and fast signal
transitions require that the accelerators have high transient
currents. Thus, short, low inductance supply traces and
decoupling within 1/8th inch of the IC are imperative with
very low impedance GND return paths.
25
VL = 1.8V
SWITCHING 6 I/OVL INPUTS
2.0
VL SUPPLY CURRENT (mA)
VL SUPPLY CURRENT (mA)
AIR-GAP DISCHARGE TEST METHOD
VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150Ω, Data Rate = 100Mbps, push-pull driver,
TA = +25°C; Unless Otherwise Specified.
2.5
SWITCHING 4 I/OVL INPUTS
1.5
1.0
SWITCHING 1 I/OVL INPUT
0.5
0
2.2
configuration (power applied). The IEC61000 standard’s
lower current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into these
devices’ pins allows the design of equipment meeting level 4
criteria without the need for additional board level protection.
2.4
2.6
2.8
3.0
3.2
VCC SUPPLY VOLTAGE (V)
3.4
3.6
FIGURE 7. VL SUPPLY CURRENT vs VCC SUPPLY VOLTAGE
10
VCC = 3.6V
20
SWITCHING 6 I/OVCC INPUTS
15
10
5
SWITCHING 4 I/OVCC INPUTS
SWITCHING 1 I/OVCC INPUT
0
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
VL SUPPLY VOLTAGE (V)
2.9
3.1 3.2
FIGURE 8. VL SUPPLY CURRENT vs VL SUPPLY VOLTAGE
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Typical Performance Curves
16
VL = 1.8V
30
SWITCHING 6 I/OVL INPUTS
VCC SUPPLY CURRENT (mA)
VCC SUPPLY CURRENT (mA)
35
VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150Ω, Data Rate = 100Mbps, push-pull driver,
TA = +25°C; Unless Otherwise Specified. (Continued)
25
SWITCHING 4 I/OVL INPUTS
20
15
10
SWITCHING 1 I/OVL INPUT
5
0
2.2
2.4
2.6
2.8
3.0
3.2
VCC SUPPLY VOLTAGE (V)
3.4
2.50
IL
2.30
2.25
2.20
2.15
ICC
2.10
2.05
2.00
-40
-15
10
35
TEMPERATURE (°C)
60
4
SWITCHING 1 I/OVCC INPUT
2
1.5
1.7
1.9
2.1
2.3
2.5
2.7
VL SUPPLY VOLTAGE (V)
2.9
3.1 3.2
SWITCHING 1 I/OVL INPUT
ICC
5
4
3
2
1
0
-40
85
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE
IL
-15
10
35
TEMPERATURE (°C)
60
85
FIGURE 12. SUPPLY CURRENT vs TEMPERATURE
18
40
16
SWITCHING 6 I/OVCC INPUTS
14
12
10
SWITCHING 4 I/OVCC INPUTS
8
6
SWITCHING 1 I/OVCC INPUT
2
10
15
20
25
30
CAPACITIVE LOAD (pF)
FIGURE 13. VL SUPPLY CURRENT vs I/OVL CAPACITIVE
LOAD
11
35
VCC SUPPLY CURRENT (mA)
VL SUPPLY CURRENT (mA)
6
6
2.35
0
SWITCHING 4 I/OVCC INPUTS
8
7
SWITCHING 1 I/OVCC INPUT
2.40
4
10
FIGURE 10. VCC SUPPLY CURRENT vs VL SUPPLY VOLTAGE
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.45
SWITCHING 6 I/OVCC INPUTS
12
0
1.3
3.6
FIGURE 9. VCC SUPPLY CURRENT vs VCC SUPPLY
VOLTAGE
VCC = 3.6V
14
35
SWITCHING 6 I/OVL INPUTS
30
25
SWITCHING 4 I/OVL INPUTS
20
15
10
SWITCHING 1 I/OVL INPUT
5
0
10
15
20
25
30
35
CAPACITIVE LOAD (pF)
FIGURE 14. VCC SUPPLY CURRENT vs I/OVCC CAPACITIVE
LOAD
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Typical Performance Curves
1.8
2.1
SWITCHING I/OVL INPUT
1.7
tFVCC
1.6
1.5
tRVCC
1.4
1.3
1.2
1.1
tRVL
1.7
tFVL
1.5
1.3
1.1
1.0
0.9
10
15
20
25
30
SWITCHING I/OVCC INPUT
1.9
RISE AND FALL TIMES (ns)
RISE AND FALL TIMES (ns)
VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150Ω, Data Rate = 100Mbps, push-pull driver,
TA = +25°C; Unless Otherwise Specified. (Continued)
0.9
10
35
15
CAPACITIVE LOAD (pF)
FIGURE 15. RISE/FALL TIME vs I/OVCC CAPACITIVE LOAD
3.4
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
4.0
tPLH
3.6
tPHL
3.4
3.2
tPLH
3.0
2.8
tPLH
2.6
tPHL
15
20
25
30
35
FIGURE 17. PROPAGATION DELAY vs I/OVCC CAPACITIVE
LOAD
2.4
10
15
1.0
0.5
0
30
35
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
3.0
2.5
I/OVL OUTPUT (V)
I/OVCC OUTPUT (V)
25
FIGURE 18. PROPAGATION DELAY vs I/OVL CAPACITIVE
LOAD
I/OVCC INPUT (V)
I/OVL INPUT (V)
1.5
20
CAPACITIVE LOAD (pF)
2.0
2.0
1.5
1.0
0
35
3.2
CAPACITIVE LOAD (pF)
0.5
30
SWITCHING I/OVCC INPUT
SWITCHING I/OVL INPUT
3.0
10
25
FIGURE 16. RISE/FALL TIME vs I/OVL CAPACITIVE LOAD
4.2
3.8
20
CAPACITIVE LOAD (pF)
CL = 35pF
TIME (4ns/DIV)
FIGURE 19. I/OVCC OUTPUT WAVEFORMS (100Mbps)
12
1.5
1.0
0.5
0
CL = 15pF
TIME (4ns/DIV)
FIGURE 20. I/OVL OUTPUT WAVEFORMS (100Mbps)
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
VCC = 3.3V, VL = 1.8V, CL = 15pF, RSOURCE = 150Ω, Data Rate = 100Mbps, push-pull driver,
TA = +25°C; Unless Otherwise Specified. (Continued)
2
1
Die Characteristics
0
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
CLK_VCC OUTPUT (V)
CLK_RET OUTPUT (V)
CLK_VL INPUT (V)
Typical Performance Curves
CL = 35pF
CL = 15pF
SUBSTRATE AND TQFN/QFN THERMAL PAD
POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL3034E, ISL3035E - 2600
ISL3036E - 2000
PROCESS:
1.5
1.0
Si Gate BiCMOS
0.5
0
TIME (4ns/DIV)
FIGURE 21. ISL3035E CLOCK WAVEFORMS (100Mbps)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
13
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
L16.2.6x1.8A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
2X
A
N
SYMBOL
E
0.10 C
1 2
2X
0.10 C
MIN
0.10 C
C
A
0.05 C
A1
SIDE VIEW
e
PIN #1 ID
K
1 2
NX L
L1
0.45
0.50
0.55
-
-
-
0.05
-
0.127 REF
(DATUM B)
(DATUM A)
BOTTOM VIEW
-
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
0.40 BSC
-
K
0.15
-
-
-
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N
16
2
Nd
4
3
Ne
4
3
θ
NX b 5
16X
0.10 M C A B
0.05 M C
NOTES
A
e
SEATING PLANE
MAX
A1
A3
TOP VIEW
NOMINAL
0
-
12
4
Rev. 5 2/09
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
NX (b)
L
5
e
SECTION "C-C"
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
TERMINAL TIP
C C
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
1.40
2.20
0.90
0.40
0.20
0.50
0.20
0.40
10 LAND PATTERN
14
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Package Outline Drawing
L14.3.5x3.5
14 LEAD QUAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (QFN)
Rev 0, 2/08
3.50
2x 2.0
A
PIN 1 6
INDEX AREA
8x 0.50
6
B
PIN #1 INDEX AREA
2
6
1
3.50
7
2.05 ± 0 . 15
2x 1.50
8
14
0.15
(4X)
13
9
TOP VIEW
0.10 M C A B
0.07
4 16X 0.23 +- 0.05
VIEW “A-A”
14x 0.40 ± 0.10
BOTTOM VIEW
( 2.00 )
(8x 0.50)
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08 C
( 3.30 TYP )
(
( 2x 1.5 )
2.05)
SIDE VIEW
( 14x 0.23 )
C
( 14 x 0.60)
TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
DETAIL “X”
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
15
FN6492.0
March 31, 2009
ISL3034E, ISL3035E, ISL3036E
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
)
2X
L16.3x3A
0.15 C A
D
A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
9
D/2
MILLIMETERS
D1
D1/2
2X
N
6
INDEX
AREA
0.15 C B
1
2
3
E1/2
E/2
E
MAX
NOTES
0.75
0.80
-
A1
-
-
0.05
-
A2
-
-
0.80
9
0.30
5, 8
0.20 REF
0.18
D
B
TOP VIEW
A2
A
D2
/ / 0.10 C
0
C
A3
SIDE VIEW
9
5
NX b
4X P
E
3.00 BSC
-
2.75 BSC
9
1.35
1.50
1.65
7, 8, 10
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
2
8
Nd
4
3
NX k
Ne
4
3
D2
2 N
1
(DATUM A)
2
3
6
INDEX
AREA
8
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
C
L
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
L
L1
10
L
e
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
16
9
4. All dimensions are in millimeters. Angles are in degrees.
A1
e
9
12
3. Nd and Ne refer to the number of terminals on each D and E.
NX b
10
0.60
-
2. N is the number of terminals.
BOTTOM VIEW
C
L
-
-
NOTES:
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
-
θ
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
E2/2
N e
P
Rev. 0 6/04
(Ne-1)Xe
REF.
E2
7
NX L
C C
7, 8, 10
16
7
L1
9
1.65
N
4X P
8
1.50
0.10 M C A B
D2
(DATUM B)
A1
-
2.75 BSC
1.35
e
SEATING PLANE
9
E1
E2
0.08 C
0.23
3.00 BSC
D1
0.15 C B
4X
NOMINAL
0.70
b
9
0.15 C A
MIN
A
A3
E1
2X
2X
SYMBOL
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.
FN6492.0
March 31, 2009
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