DATASHEET

ISL54050
®
Data Sheet
November 22, 2008
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Dual SPDT Analog Switch
The Intersil ISL54050 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+4.5V supply. Targeted applications include battery powered
equipment that benefit from low rON (0.29Ω) and fast
switching speeds (tON = 40ns, tOFF = 20ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54050 is offered in small form factor package, alleviating
board space limitations.
FN6356.4
Features
• Pin Compatible Replacement for the NLAS5223 and
NLAS5223L
• ON-Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29Ω
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω
• rON Matching Between Channels . . . . . . . . . . . . . . . . .0.06Ω
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . .0.03Ω
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . <0.45µW
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV
The ISL54050 is a committed dual single-pole/double-throw
(SPDT) that consists of two normally open (NO) and two
normally closed (NC) switches. This configuration can be
used as a dual 2-to-1 multiplexer. The ISL54050 is pin
compatible with the NLAS5223 and NLAS5223L.
TABLE 1. FEATURES AT A GLANCE
• Break-before-Make
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 10 Ld 1.8mmx1.4mmx0.5mm µTQFN
• Pb-Free (RoHS Compliant)
ISL54050
Applications
Number of Switches
2
SW
SPDT or 2-1 MUX
4.3V rON
0.29Ω
4.3V tON/tOFF
40ns/20ns
3V rON
0.33Ω
3V tON/tOFF
50ns/27ns
1.8V rON
0.55Ω
1.8V tON/tOFF
70ns/54ns
Package
10 Ld 1.8mmx1.4mmx0.5mm µTQFN
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
Ordering Information
PART NUMBER
(Note)
ISL54050IRUZ-T*
PART
MARKING
TEMP. RANGE
(°C)
A
-40 to +85
PACKAGE
(Pb-free)
10 Ld 1.8mmx1.4mmx0.5mm µTQFN
Tape and Reel
PKG.
DWG. #
L10.1.8x1.4A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54050
Pinout
Pin Descriptions
(Note 1)
ISL54050
(10 LD µTQFN)
TOP VIEW
IN2
NC2
GND
7
6
8
PIN
V+
5
NC1
NO2
9
4
10
3
1
2
V+
NO1
IN1
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
COM2
FUNCTION
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
COM1
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
NOTE:
LOGIC
NC1 and NC2
NO1 and NO2
0
ON
OFF
1
OFF
ON
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
2
FN6356.4
November 22, 2008
ISL54050
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Output Voltages
COMx (Note 2). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Thermal Resistance (Typical)
θJA (°C/W)
10 Ld µTQFN Package (Note 3) . . . . . . . . . . . . . . .
143
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(see Figures 5, 9)
rON Matching Between Channels,
ΔrON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max rON (Notes 7, 9)
rON Flatness, rFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(Notes 6, 9)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V or floating
0
V+
V
25
0.30
0.5
Ω
Full
0.35
0.7
Ω
25
0.06
0.07
Ω
Full
0.08
0.08
Ω
25
0.03
0.15
Ω
Full
0.04
0.15
Ω
25
-100
100
nA
Full
-195
195
nA
25
-100
100
nA
Full
-195
195
nA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(see Figure 1)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(see Figure 1)
25
40
ns
Full
50
ns
25
20
ns
Full
30
ns
Break-Before-Make Time Delay, tD
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(see Figure 3)
Full
8
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
170
pC
OFF-Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(see Figure 4)
25
62
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(see Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
0.005
%
25
62
pF
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
3
FN6356.4
November 22, 2008
ISL54050
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
TEMP
MIN
(°C) (Notes 5, 8)
25
TYP
MAX
(Notes 5, 8) UNITS
176
pF
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
4.5
V
25
0.1
µA
Full
1
µA
25
12
µA
Input Voltage Low, VINL
Full
0.5
V
Input Voltage High, VINH
Full
1.6
Full
-0.5
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
1.65
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+ (Note 9)
Electrical Specifications - 3V Supply
PARAMETER
V
0.5
µA
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full
ON-Resistance, rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(see Figure 5)
rON Matching Between Channels,
ΔrON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON (Note 7)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or floating
25
0
V+
V
0.5
Ω
0.7
Ω
0.06
0.07
Ω
0.08
Ω
0.03
0.15
Ω
0.15
Ω
0.35
Full
25
Full
25
Full
25
0.9
nA
Full
30
nA
25
0.8
nA
Full
30
nA
DYNAMIC CHARACTERISTICS
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(see Figure 1)
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(see Figure 1)
Turn-OFF Time, tOFF
25
50
ns
Full
60
ns
25
27
ns
Full
35
ns
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(see Figure 3)
Full
9
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
94
pC
OFF-Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(see Figure 4)
25
62
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(see Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
0.005
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
65
pF
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
181
pF
COM ON Capacitance, CCOM(ON)
4
FN6356.4
November 22, 2008
ISL54050
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
Unless Otherwise Specified. (Continued)
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
25
0.01
µA
Full
0.52
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
Input Voltage High, VINH
25
1.4
Full
-0.5
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+ (Note 9)
Electrical Specifications - 1.8V Supply
PARAMETER
0.5
V
V
0.5
µA
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 8)
TYP
MAX
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Full
Analog Signal Range, VANALOG
V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+
(see Figure 5)
ON-Resistance, rON
0
25
0.7
Full
V+
V
0.8
Ω
0.85
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF
(see Figure 1)
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF
(see Figure 1)
25
70
ns
Full
80
ns
25
54
ns
Full
65
ns
Break-Before-Make Time Delay, td
V+ = 2.0V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF
(see Figure 3)
Full
10
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
42
pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
70
pF
f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7)
25
186
pF
COM ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
Input Voltage High, VINH
25
1.0
Full
-0.5
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 9)
0.4
V
V
0.5
µA
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Limits established by characterization and are not production tested.
5
FN6356.4
November 22, 2008
ISL54050
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
tr < 5ns
tf < 5ns
50%
C
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
COM
IN
VOUT
90%
SWITCH
OUTPUT
VOUT
NO OR NC
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) ---------------------------R L + r ( ON )
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
ΔVOUT
V+
LOGIC
INPUT
ON
ON
C
VG
VOUT
COM
NO OR NC
GND
IN
CL
OFF
0V
LOGIC
INPUT
Q = ΔVOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
V+
LOGIC
INPUT
NO
VNX
0V
VOUT
COM
NC
SWITCH
OUTPUT
VOUT
90%
LOGIC
INPUT
0V
tD
FIGURE 3A. MEASUREMENT POINTS
RL
50Ω
IN
CL
35pF
GND
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6356.4
November 22, 2008
ISL54050
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
rON = V1/100mA
NO OR NC
NO OR NC
IN
VNX
0V or V+
100mA
IN
V1
0V OR V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO OR NC
COM
50Ω
NO OR NC
IN1
IN
0V or V+
0V OR V+
IMPEDANCE
ANALYZER
NC OR NO
COM
ANALYZER
COM
N.C.
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54050 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
ON-resistance (0.29Ω) and high speed operation
(tON = 40ns, tOFF = 20ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(4.5µW max), low leakage currents (195nA max), and the tiny
µTQFN package. The ultra low ON-resistance and rON
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the ISL54050 IC (see Figure 8).
7
GND
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC, which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation, the sub-microamp IDD current of
the IC produces an insignificant voltage drop across the
100Ω series resistor resulting in no impact to switch
operation or performance.
FN6356.4
November 22, 2008
ISL54050
V+
OPTIONAL
PROTECTION
RESISTOR
C
OPTIONAL
SCHOTTKY
DIODE
V+
100Ω
OPTIONAL
PROTECTION
RESISTOR
NO
COM
NC
INX
VNX
VCOM
IN
GND
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
FIGURE 9. OVERVOLTAGE PROTECTION
Supply Sequencing and Overvoltage Protection
Power-Supply Considerations
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
The ISL54050 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL54050 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer
to the “Electrical Specifications” tables starting on page 3
and “Typical Performance Curves” on page 9 for details.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 9). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-micro amp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins, as shown in Figure 9, will shunt the
fault current to the supply or to ground thereby protecting the
switch. These Schottky diodes must be sized to handle the
expected fault current.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure 19). At 2.7V,
the VIL level is about 0.53V. This is still above the 1.8V
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
The ISL54050 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example, driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply,
the device draws only 12µA of current (see Figure 17 for
VIN = 2.85V).
8
FN6356.4
November 22, 2008
ISL54050
Frequency Performance
Leakage Considerations
In 50Ω systems, the ISL54050 has a -3dB bandwidth of
25MHz (see Figure 22). The frequency response is very
consistent over a wide V+ range and for varying analog
signal levels.
Reverse ESD protection diodes are internally connected
between each analog signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feed-through from a switch’s input to its output. OFFisolation is the resistance to this feed-through, while
crosstalk indicates the amount of feed-through from one
switch to another. Figure 23 details the high OFF-isolation
and crosstalk rejection provided by this part. At 100kHz,
OFF-isolation is about 62dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease OFF-isolation and
crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and V+ or GND.
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified.
0.30
0.35
ICOM = 100mA
ICOM = 100mA
0.34
0.29
0.28
rON (Ω)
rON (Ω)
0.33
0.27
V+ = 2.7V
0.32
0.31
V+ = 3.9V
V+ = 3V
0.30
0.26
0.25
V+ = 4.3V
0.29
V+ = 4.5V
0
1
2
3
4
0.28
5
V+ = 3.3V
0
0.5
1.0
1.5
2.0
VCOM (V)
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.35
ICOM = 100mA
3.5
V+ = 4.3V
ICOM = 100mA
0.65
+85°C
V+ = 1.65V
0.30
rON (Ω)
0.55
rON (Ω)
3.0
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.70
0.60
2.5
V+ = 1.8V
0.50
+25°C
0.45
0.25
V+ = 2V
0.40
0.35
-40°C
0.30
0.20
0
0.5
1.0
1.5
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
9
2.0
0
1
2
3
VCOM (V)
4
5
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN6356.4
November 22, 2008
ISL54050
Typical Performance Curves
0.40
0.40
V+ = 3.3V
ICOM = 100mA
0.35
+85°C
0.30
V+ = 2.7V
ICOM = 100mA
+85°C
0.35
rON (Ω)
rON (Ω)
TA = +25°C, Unless Otherwise Specified. (Continued)
+25°C
+25°C
0.30
0.25
0.20
-40°C
0
0.5
1.0
-40°C
1.5
2.0
VCOM (V)
2.5
3.0
0.25
3.5
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
0.60
0.55
1.0
1.5
VCOM (V)
2.0
2.5
3.0
200
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
+25°C
150
0.50
-40°C
0.45
iON (µA)
rON (Ω)
0.5
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
V+ = 1.8V
ICOM = 100mA
+85°C
0
0.40
0.35
100
50
0.30
0.25
0
0.5
1.0
VCOM (V)
1.5
0
2.0
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
1
2
3
VIN1 AND VIN2 (V)
4
5
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
1.1
200
VINH
1.0
150
VINH AND VINL (V)
0.9
Q (pC)
100
V+ = 4.3V
50
V+ = 1.8V
0
0.7
0.6
0.5
V+ = 3V
-50
-100
0.8
VINL
0.4
0
1
2
3
4
5
VCOM (V)
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
10
0.3
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6356.4
November 22, 2008
ISL54050
TA = +25°C, Unless Otherwise Specified. (Continued)
250
200
200
150
tOFF (ns)
+85°C
150
+25°C
100
-40°C
25
1.0
1.5
100
+85°C
+25°C
50
2.0
2.5
3.0
3.5
4.0
-40°C
0
1.0
4.5
1.5
2.0
V+ (V)
-20
0
CROSSTALK (dB)
NORMALIZED GAIN (dB)
3.5
4.0
4.5
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
-10
-2
-4
10
V+ = 4.3V
20
-30
30
-40
40
-50
50
ISOLATION
-60
60
70
-70
80
-80
CROSSTALK
-90
V+ = 3.3V
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
90
100
-100
10M
20M
FREQUENCY (Hz)
FIGURE 22. FREQUENCY RESPONSE
11
3.0
V+ (V)
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
1M
2.5
100M
OFF-ISOLATION (dB)
tON (ns)
Typical Performance Curves
-110
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
110
500M
FIGURE 23. CROSSTALK AND OFF-ISOLATION
FN6356.4
November 22, 2008
ISL54050
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
A
L10.1.8x1.4A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
2X
MIN
NOMINAL
MAX
NOTES
0.10 C
1
2X
2
0.10 C
TOP VIEW
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.10 C
C
A
0.05 C
A
0.127 REF
0.15
0.20
0.25
5
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
SEATING PLANE
A1
SIDE VIEW
(DATUM A)
PIN #1 ID
NX L
1
NX b 5
10X
0.10 M C A B
0.05 M C
2
L1
5
(DATUM B)
7
-
b
0.40 BSC
-
L
0.35
0.40
0.45
L1
0.45
0.50
0.55
-
N
10
2
Nd
2
3
Ne
3
3
θ
0
-
12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
e
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
NX (b)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
5
L
SECTION "C-C"
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
e
8. Maximum allowable burrs is 0.076mm in all directions.
TERMINAL TIP
C C
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.20
1.00
0.60
1.00
9. JEDEC Reference MO-255.
0.50
1.80
0.40
0.20
0.20
0.40
10 LAND PATTERN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN6356.4
November 22, 2008
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