DATASHEET

DATASHEET
High Voltage Synchronous Rectified Buck MOSFET
Drivers
ISL6208C
Features
The ISL6208C is a high frequency, dual MOSFET driver,
optimized to drive two N-channel power MOSFETs in a
synchronous-rectified buck converter topology. It is especially
suited for mobile computing applications that require high
efficiency and excellent thermal performance. The driver,
combined with an Intersil multiphase buck PWM controller,
forms a complete single-stage core-voltage regulator solution
for advanced mobile microprocessors.
• Dual MOSFET drives for synchronous rectified bridge
The ISL6208C features 4A typical sinking current for the lower
gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the phase node. This
prevents shoot-through power loss caused by the high dv/dt of
phase voltages. The operating voltage matches the 30V
breakdown voltage of the MOSFETs commonly used in mobile
computer power supplies.
• Adaptive shoot-through protection
• 0.5Ω ON-resistance and 4A sink current capability
• Supports high switching frequency up to 2MHz
- Fast output rise and fall time
- Low propagation delay
• Three-state PWM input for power stage shutdown
• Internal bootstrap Schottky diode
• Low bias supply current (5V, 80µA)
• Diode emulation for enhanced light load efficiency and
prebiased start-up applications
• VCC POR (Power-On-Reset) feature integrated
The ISL6208C also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown. This
feature eliminates a protective Schottky diode usually seen in
microprocessor power systems.
• Low three-state shutdown holdoff time (typical 160ns)
MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208C. Each driver is capable of driving a 3000pF load
with propagation delays of 8ns and transition times under
10ns. Bootstrapping is implemented with an internal Schottky
diode. This reduces system cost and complexity, while allowing
the use of higher performance MOSFETs. Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
Applications
A diode emulation feature is integrated in the ISL6208C to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into prebiased
outputs. When diode emulation is enabled, the driver will allow
discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off the
low-side MOSFET gate.
Related Literature
• Pin-to-pin compatible with ISL6207
• DFN package
• Pb-free (RoHS compliant)
• Core voltage supplies for Intel™ and AMD™ mobile
microprocessors
• High frequency low profile DC/DC converters
• High current low output voltage DC/DC converters
• High input voltage DC/DC converters
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”
• Technical Brief TB447 “Guidelines for Preventing
Boot-to-Phase Stress on Half-Bridge MOSFET Driver ICs”
June 1, 2016
FN8395.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6208C
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application with 2-Phase Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Diode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Three-State PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Adaptive Shoot-Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reducing Phase Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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ISL6208C
Block Diagram
VCC
BOOT
FCCM
UGATE
PHASE
SHOOTTHROUGH
PROTECTION
CONTROL
LOGIC
PWM
VCC
LGATE
10kΩ
GND
THERMAL PAD
FIGURE 1. BLOCK DIAGRAM
Typical Application with 2-Phase Converter
+5V
VBAT
+5V
+5V
VCC
FB
VSEN
PWM1
PWM
PWM2
PGOOD
UGATE
FCCM
VCC
PHASE
DRIVE
ISL6208C
THERMAL
PAD
FCCM
MAIN
CONTROL
+VCORE
BOOT
COMP
LGATE
ISEN1
VID
ISEN2
+5V
VBAT
VCC
BOOT
FS
DACOUT
GND
FCCM
PWM
UGATE
DRIVE
ISL6208C
PHASE
THERMAL LGATE
PAD
FIGURE 2. TYPICAL APPLICATION WITH 2-PHASE CONVERTER
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ISL6208C
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6208CHRZ-T
8CH
-10 to +100
6k
8 Ld 2x2 DFN
L8.2x2D
ISL6208CIRZ-T
8CI
-40 to +100
6k
8 Ld 2x2 DFN
L8.2x2D
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6208C. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL6208C
(8 LD 2x2 DFN)
TOP VIEW
UGATE 1
86 PHASE
BOOT 2
7 FCCM
PWM 3
66 VCC
GND 4
5 LGATE
Pin Description
PIN
SYMBOL
1
UGATE
The UGATE pin is the upper gate drive output. Connect to gate of the high-side power N-channel MOSFET.
2
BOOT
BOOT is the floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin
and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal
Bootstrap Diode” on page 9 for guidance in choosing the appropriate capacitor value.
3
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation. See
“Three-State PWM Input” on page 9 for further details. Connect this pin to the PWM output of the controller.
4
GND
GND is the ground pin for the IC.
5
LGATE
6
VCC
7
FCCM
The FCCM pin enables or disables Diode Emulation. When FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced. See “Diode Emulation” on page 9 for more detail.
8
PHASE
Connect the PHASE pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
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DESCRIPTION
LGATE is the lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect the VCC pin to a +5V bias supply. Place a high quality bypass capacitor from this pin to GND. The VCC pin
of the driver(s) and related VCC or +5V bias supply pin of the Intersil controller must share a common +5V supply.
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ISL6208C
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (VFCCM, VPWM) . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . . -0.3V to 33V (DC) or 36V (<20ns)
BOOT To PHASE Voltage (VBOOT-PHASE). . . . . . . . . . . . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 30V
GND - 8V (<20ns Pulse Width, 10µJ)
UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld 2x2 DFN Package (Notes 5, 6) . . . . . .
89
24
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Hi-Temp Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating
temperature range, -40°C to +100°C (Industrial), -10°C to +100°C (Hi-Temp Commercial).
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
-
80
-
µA
VCC Rising
-
3.40
3.90
V
VCC Falling
2.40
2.90
-
V
Hysteresis
-
500
-
mV
0.50
0.55
0.65
V
SYMBOL
PARAMETER
TEST CONDITIONS
VCC SUPPLY CURRENT
IVCC
Bias Supply Current
PWM pin floating, VFCCM = 5V
POR
BOOTSTRAP DIODE
VF
Forward Voltage
VVCC = 5V, forward bias current = 2mA
Input Current
VPWM = 5V
-
250
-
µA
VPWM = 0V
-
-250
-
µA
PWM Three-State Rising Threshold
VVCC = 5V
0.70
1.00
1.30
V
PWM Three-State Falling Threshold
VVCC = 5V
3.5
3.8
4.1
V
Three-State Shutdown Hold-Off Time
VVCC = 5V, temperature = +25°C
100
175
250
ns
FCCM LOW Threshold
0.50
-
-
V
FCCM HIGH Threshold
-
-
2.0
V
PWM INPUT
IPWM
tTSSHD
FCCM INPUT
SWITCHING TIME
tRU
UGATE Rise Time
VVCC = 5V, 3nF load
-
8.0
-
ns
tRL
LGATE Rise Time
VVCC = 5V, 3nF load
-
8.0
-
ns
tFU
UGATE Fall Time
VVCC = 5V, 3nF load
-
8.0
-
ns
tFL
LGATE Fall Time
VVCC = 5V, 3nF load
-
4.0
-
ns
UGATE Turn-Off Propagation Delay
VVCC = 5V, outputs unloaded
-
18
-
ns
tPDLU
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ISL6208C
Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating
temperature range, -40°C to +100°C (Industrial), -10°C to +100°C (Hi-Temp Commercial). (Continued)
SYMBOL
PARAMETER
MIN
(Note 7)
TEST CONDITIONS
TYP
MAX
(Note 7)
UNIT
tPDLL
LGATE Turn-Off Propagation Delay
VVCC = 5V, outputs unloaded
-
25
-
ns
tPDHU
UGATE Turn-On Propagation Delay
VVCC = 5V, outputs unloaded
10
20
30
ns
tPDHL
LGATE Turn-On Propagation Delay
VVCC = 5V, outputs unloaded
10
20
30
ns
UG/LG Three-State Propagation Delay
VVCC = 5V, outputs unloaded
-
35
-
ns
-
400
-
ns
-
1
2.5
Ω
tPTS
tLGMIN
Minimum LG ON-TIME in DCM
OUTPUT
RU
Upper Drive Source Resistance
500mA source current
IU
Upper Driver Source Current
VUGATE-PHASE = 2.5V
-
2.00
-
A
RU
Upper Drive Sink Resistance
500mA sink current
-
1
2.5
Ω
IU
Upper Driver Sink Current
VUGATE-PHASE = 2.5V
-
2.00
-
A
RL
Lower Drive Source Resistance
500mA source current
-
1
2.5
Ω
IL
Lower Driver Source Current
VLGATE = 2.5V
-
2.00
-
A
RL
Lower Drive Sink Resistance
500mA sink current
-
0.5
1.0
Ω
IL
Lower Driver Sink Current
VLGATE = 2.5V
-
4.00
-
A
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
2.5V
PWM
tPDHU
tPDLU
tRU
tTSSHD
tRU
tFU
tFU
tPTS
1V
UGATE
LGATE
tPTS
1V
tRL
tFL
tTSSHD
tPDHL
tPDLL
tFL
FIGURE 3. TIMING DIAGRAM
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ISL6208C
Functional Pin Description
Theory of Operation
UGATE
Designed for speed, the ISL6208C dual MOSFET driver controls
both high-side and low-side N-channel FETs from one externally
provided PWM signal.
The UGATE pin is the upper gate drive output. Connect to gate of
the high-side power N-channel MOSFET.
BOOT
BOOT is the floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn on the
upper MOSFET. See “Internal Bootstrap Diode” on page 9 for
guidance in choosing the appropriate capacitor value.
PWM
The PWM signal is the control input for the driver. The PWM signal
can enter three distinct states during operation. See “Three-State
PWM Input” on page 9 for further details. Connect this pin to the
PWM output of the controller.
GND
GND is the ground pin for the IC.
LGATE
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-channel MOSFET.
VCC
Connect the VCC pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
FCCM
A rising edge on PWM initiates the turn-off of the lower MOSFET
(see “Timing Diagram”). After a short propagation delay [tPDLL],
the lower gate begins to fall. Typical fall times [tFL] are provided
in the “Electrical Specifications” on page 5. Adaptive
shoot-through circuitry monitors the LGATE voltage. When LGATE
has fallen below 1V, UGATE is allowed to turn ON. This prevents
both the lower and upper MOSFETs from conducting
simultaneously, or shoot-through.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay (tPDLU) is encountered before the upper gate
begins to fall (tFU). The upper MOSFET gate-to-source voltage is
monitored, and the lower gate is allowed to rise after the upper
MOSFET gate-to-source voltage drops below 1V. The lower gate
then rises (tRL), turning on the lower MOSFET.
This driver is optimized for converters with large step-down
compared to the upper MOSFET because the lower MOSFET
conducts for a much longer time in a switching period. The lower
gate driver is therefore sized much larger to meet this application
requirement.
The 0.5Ω ON-resistance and 4A sink current capability enables
the lower gate driver to absorb the current injected to the lower
gate through the drain-to-gate capacitor of the lower MOSFET and
prevents a shoot-through caused by the high dv/dt of the phase
node.
The FCCM pin enables or disables Diode Emulation. When FCCM
is LOW, diode emulation is allowed. Otherwise, continuous
conduction mode is forced. See “Diode Emulation” on page 9 for
more detail.
PHASE
Connect the PHASE pin to the source of the upper MOSFET and
the drain of the lower MOSFET. This pin provides a return path for
the upper gate driver.
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ISL6208C
Typical Performance Waveforms
FIGURE 4. LOAD TRANSIENT (0A TO 30A, 3-PHASE)
FIGURE 5. LOAD TRANSIENT (30A TO 0A, 3-PHASE)
FIGURE 6. DCM TO CCM TRANSITION AT NO LOAD
FIGURE 7. CCM TO DCM TRANSITION AT NO LOAD
FIGURE 8. PREBIASED START-UP IN CCM MODE
FIGURE 9. PREBIASED START-UP IN DCM MODE
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ISL6208C
Diode emulation allows for higher converter efficiency under light
load situations. With diode emulation active, the ISL6208C will
detect the zero current crossing of the output inductor and turn
off LGATE. This ensures that discontinuous conduction mode
(DCM) is achieved. Diode emulation is asynchronous to the PWM
signal. Therefore, the ISL6208C will respond to the FCCM input
immediately after it changes state. Refer to“Typical Performance
Waveforms” on page 8. Note: Intersil does not recommend Diode
Emulation use with rDS(ON) current sensing topologies. The
turn-OFF of the low-side MOSFET can cause gross current
measurement inaccuracies.
Three-State PWM Input
voltage over a PWM cycle is 200mV. One will find that a
bootstrap capacitance of at least 0.125µF is required. The next
larger standard value capacitance is 0.15µF. A good quality
ceramic capacitor is recommended.
2.0
1.8
1.6
CBOOT_CAP (µF)
Diode Emulation
1.4
1.2
1.0
0.8
QGATE = 100nC
0.6
The VCC pin of the driver(s) and related VCC or +5V bias supply
pin of the Intersil controller must share a common +5V supply.
Adaptive Shoot-Through
Protection
Both drivers incorporate adaptive shoot-through protection to
prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during UGATE
turn-off. Once the upper MOSFET gate-to-source voltage has
dropped below a threshold of 1V, the LGATE is allowed to rise.
Internal Bootstrap Diode
nC
50
A unique feature of the ISL6208C and other Intersil drivers is the
addition of a shutdown window to the PWM input. If the PWM
signal enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both MOSFET
gates are pulled and held low. The shutdown state is removed
when the PWM signal moves outside the shutdown window.
Otherwise, the PWM rising and falling thresholds outlined in the
“Electrical Specifications” table on page 5 determine when the
lower and upper gates are enabled.
0.4
0.2
20nC
0.0
0.0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
VBOOT_CAP (V)
0.8
0.9
1.0
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency and total gate charge of the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation is approximately 800mW. When designing the driver
into an application, it is recommended that the following
calculation be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated by the
driver is approximated, as shown in Equation 2:
P = f sw  1.5V U Q + V L Q  + I VCC V
U
L
CC
(EQ. 2)
Where fsw is the switching frequency of the PWM signal. VU and
VL represent the upper and lower gate rail voltage. QU and QL is
the upper and lower gate charge determined by MOSFET
selection and any external capacitance added to the gate pins.
The lVCC VCC product is the quiescent power of the driver and is
typically negligible.
This driver features an internal bootstrap Schottky diode. Simply
adding an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from Equation 1:
Q GATE
C BOOT  -----------------------V BOOT
(EQ. 1)
Where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate charge,
QGATE , of 25nC at 5V and also assume the droop in the drive
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ISL6208C
Thermal Management
1000
QU =100nC
QL = 200nC
900
QU = 50nC
QL = 100nC
QU = 50nC
QL = 50nC
800
POWER (mW)
700
600
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal pad of
the DFN to the power ground with multiple vias is recommended.
This heat spreading allows the part to achieve its full thermal
potential.
QU = 20nC
QL =50nC
500
400
300
200
100
0
0
200
400
600
800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 11. POWER DISSIPATION vs FREQUENCY
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices (both
upper and lower FETs) could cause increased PHASE ringing,
which may lead to voltages that exceed the absolute maximum
rating of the devices. When PHASE rings below ground, the
negative voltage could add charge to the bootstrap capacitor
through the internal bootstrap diode. Under worst-case
conditions, the added charge could overstress the BOOT and/or
PHASE pins. To prevent this from happening, the user should
perform a careful layout inspection to reduce trace inductances,
and select low lead inductance MOSFETs and drivers. D2PAK and
DPAK packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must be
used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
A good layout would help reduce the ringing on the phase and
gate nodes significantly:
• Avoid using vias for decoupling components where possible,
especially in the BOOT-to-PHASE path. Little or no use of vias
for VCC and GND is also recommended. Decoupling loops
should be short.
• All power traces (UGATE, PHASE, LGATE, GND, VCC) should be
short and wide, and avoid using vias. If vias must be used, two
or more vias per layer transition is recommended.
• Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
• Keep the connection in between the SOURCE of lower FET and
power ground wide and short.
• Input capacitors should be placed as close to the DRAIN of the
upper FET and the SOURCE of the lower FET as thermally
possible.
Note: Refer to Intersil Tech Brief TB447 for more information.
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ISL6208C
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest revision.
DATE
REVISION
CHANGE
June 1, 2016
FN8395.1
Added note to VCC pin description on page 4 and to “Three-State PWM Input” on page 9 that +5V supply
should be common with Intersil controller.
Added AC specification to BOOT-GND Absolute Maximum Rating on page 5.
On page 12 - Updated L8.2x2D POD from rev 0 to rev 1. Updates since rev 0:
Tiebar Note 5 updated From: "Tiebar shown (if present) is a non-functional feature."
To: "Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends)."
November 29, 2012
FN8395.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL6208C
Package Outline Drawing
L8.2x2D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD
Rev 1, 3/15
2.00
6
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
A
B
8
1
2.00
6x 0.50
(4X)
1.55±0.10
0.15
0.10M C A B 0.22
4
TOP VIEW
( 8x0.30 )
0.90±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
0.90±0.10
BASE PLANE
0 . 00 MIN.
0 . 05 MAX.
SEATING PLANE
0.08 C
SIDE VIEW
0 . 2 REF
C
DETAIL "X"
( 8x0.20 )
PACKAGE
OUTLINE
( 8x0.30 )
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
( 6x0.50 )
1.55
2.00
between 0.15mm and 0.30mm from the terminal tip.
( 8x0.22 )
0.90
2.00
TYPICAL RECOMMENDED LAND PATTERN
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5.
6.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8395.1
June 1, 2016
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