DATASHEET

High-Speed USB 2.0 (480Mbps) DPST Switch with
Overvoltage Protection (OVP) and Dedicated Charger
Port Detection
ISL54226
Features
The Intersil ISL54226 is a single supply, dual SPST (Single
Pole/Single Throw) switch that is configured as a DPST. It can
operate from a single 2.7V to 5.25V supply. The part was
designed for switching or isolating a USB high-speed source or a
USB high-speed and full-speed source in portable battery
powered products.
• High-speed (480Mbps) and full-speed (12Mbps) signaling
capability per USB 2.0
The 3.5Ω SPST switches were specifically designed to pass USB
full speed and USB high-speed data signals. They have high
bandwidth and low capacitance to pass USB high-speed data
signals with minimal distortion.
• 1.8V logic compatible (2.7V to +3.6V supply)
• OE/ALM pin to open all switches and indicate overvoltage
fault condition
• Charger interrupt indicator output
• Power OFF protection
• COM pins overvoltage protection for +5.25V and -5V fault
voltages
The ISL54226 has OVP detection circuitry on the COM pins to
open the SPST switches when the voltage at these pins
exceeds 3.8V or goes negative by -0.45V. It isolates fault
voltages up to +5.25V or down to -5V from getting passed to
the other side of the switch, thereby protecting the USB downstream transceiver.
• -3dB frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790MHz
The OE/ALM logic pin is an open drain input/output that can
be driven to open the switches or monitored to tell when the
part is in an overvoltage state.
• Pb-Free (RoHS compliant)
The part has an interrupt (INT) output pin to indicate a 1 to 1
(high/high) state on the COM lines to inform the µprocessor
when entering a dedicated charging port mode of operation.
The ISL54226 is available in 8 Ld 1.2mmx1.4mm µTQFN and
8 Ld 2mmx2mm TDFN packages. It operates over a
temperature range of -40 to +85°C.
• Low ON capacitance @ 240MHz. . . . . . . . . . . . . . . . . . . . . 2pF
• Low ON-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5Ω
• Single supply operation (VDD). . . . . . . . . . . . . . . 2.7V to 5.25V
• Available in µTQFN and TDFN packages
• Compliant with USB 2.0 short circuit and overvoltage
requirements without additional external components
Applications
• MP3 and other personal media players
• Cellular/mobile phones, PDA’s
• Digital cameras and camcorders
• USB switching
3.3V
3.3V
500Ω
USB CONNECTOR
INT
OE/ALM
LOGIC
CONTROL
VBUS
D-
COM -
D+
OVP
DET
COM +
µP
DUSB
GND
ISL54226
4MΩ
D+
HIGH-SPEED
TRANSCEIVER
VOLTAGE SCALE (0.1V/DIV)
100kΩ
VDD
GND
TIME SCALE (0.2ns/DIV)
FIGURE 1. TYPICAL APPLICATION
September 12, 2013
FN7614.1
1
FIGURE 2. USB 2.0 HS EYE PATTERN WITH SWITCHES IN THE
SIGNAL PATH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL54226
Pin Configurations
ISL54226
(8 LD 2x2 TDFN)
TOP VIEW
COM +
PD
INT
6
7
8
GND
COM -
ISL54226
(8 LD 1.2x1.4 µTQFN)
TOP VIEW
1
8
VDD
7
OE/ALM
6
D-
5
COM-
LOGIC
D+
OVP
4MΩ
1
5
D-
2
COM+
3
GND
4
D+
LOGIC
OVP
2
3
4
OE/ALM
VDD
INT
4MΩ
NOTE:
1. Switches Shown for OE/ALM = Logic “0”.
Pin Descriptions
Truth Table
INPUT
µTQFN
TDFN
PIN
NAME
4
1
INT
Charger Mode Interrupt Output
5
2
D+
6
3
COM+
7
4
GND
Ground Connection
8
5
COM-
USB Data Port
1
6
D-
USB Data Port
2
7
3
8
VDD
-
PD
PD
DESCRIPTION
OUTPUT
SIGNAL AT COM
PINS
OE/ALM
D-, D+
INT
OE/ALM
STATE
USB Data Port
0V to 3.6V
0
OFF
High
Low
Normal
USB Data Port
0V to 3.6V
1
ON
High
High
Normal
Overvoltage
Range
0
OFF
High
Low
OVP
Overvoltage
Range
1
OFF
High
Low
OVP
COM Pins Tied
Together
0
OFF
Low
Low
Charger
Port (CP)
COM Pins Tied
Together
1
ON
High
High
Normal
OE/ALM Switch Enable/Alarm (Open Drain)
Drive Low to Open Switches
Outputs are Low when OVP is Activated
Power Supply
Thermal Pad. Tie to Ground or Float
Logic “0” when ≤0.5V, Logic “1” when ≥1.4V with a 2.7V to 3.6V Supply.
TABLE 1. OVP TRIP POINT VOLTAGE
SYSTEM VOLTAGE CONDITIONS
TRIP POINT
CODEC SUPPLY
SWITCH SUPPLY (VDD)
COMs SHORTED TO
PROTECTED
MIN
MAX
2.7V to 3.3V
2.7V to 5.25V
VBUS
Yes
3.62V
3.95V
2.7V to 3.3V
2.7V to 5.25V
-5V
Yes
-0.6V
-0.29V
2
FN7614.1
September 12, 2013
ISL54226
Ordering Information
PART NUMBER
(Notes 2, 5)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
Tape & Reel
(Pb-Free)
PKG.
DWG. #
ISL54226IRUZ-T (Note 4)
U5
-40 to +85
8 Ld 1.2mmx1.4mm µTQFN
L8.1.4x1.2
ISL54226IRUZ-T7A (Note 4)
U5
-40 to +85
8 Ld 1.2mmx1.4mm µTQFN
L8.1.4x1.2
ISL54226IRTZ-T (Note 3)
226
-40 to +85
8 Ld 2mmx2mm TDFN
L8.2x2C
ISL54226IRTZ-T7A (Note 3)
226
-40 to +85
8 Ld 2mmx2mm TDFN
L8.2x2C
ISL54226IRZEVAL1Z
Evaluation Board
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54226. For more information on MSL please see techbrief TB363.
3
FN7614.1
September 12, 2013
ISL54226
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V
VDD to COMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V
COMx to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6V
Input Voltages
D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
COM+, COM- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 6.5V
OE/ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V
Continuous Current (COM - / D-, COM + / D+) . . . . . . . . . . . . . . . . . ±40mA
Peak Current (COM-/D-, COM+/D+)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
Human Body Model (Tested per JESD22-A114-F) . . . . . . . . . . . . >5.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . >250V
Charged Device Model (Tested per JESD22-C101-D) . . . . . . . . . . . . >2kV
Latch-up (Tested per JEDEC; Class II Level A) . . . . . . . . . . . . . . . . at +85°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld µTQFN Package (Notes 7, 9) . . . . . . .
210
165
8 Ld TDFN Package (Notes 6, 8). . . . . . . . .
96
19
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Normal Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V
Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 5.25V
Analog Signal Range
VDD = 2.7V to 5.25V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications - 2.7V to 5.25V Supply
Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH = 1.4V,
VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON (High-Speed)
VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or
VCOM- = 0V to 400mV (see Figure 4, Note 15)
rON Matching Between Channels, ΔrON
(High-Speed)
VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or
VCOM- = Voltage at max rON, (Notes 14, 15)
rON Flatness, RFLAT(ON)
(High-Speed)
VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or
VCOM- = 0V to 400mV, (Notes 13, 15)
Full
ON-Resistance, rON
VDD = 3.3V, OE/ALM = 1.4V, ICOMx = 17mA, VCOM+ or
VCOM-= 3.3V (see Figure 4, Note 15)
+25
Full
-
-
22
Ω
OFF Leakage Current, IDx(OFF)
VDD = 5.25V, OE/ALM = 0V, VDx = 0.3V, 3.3V,
VCOMX = 3.3V, 0.3V
25
-20
1
20
nA
Full
-
30
-
nA
ON Leakage Current, IDx(ON)
VDD = 5.25V, OE/ALM = 5.25V, VDx = 0.3V, 3.3V,
VCOMX = 0.3V, 3.3V
25
-9
-
9
µA
Full
-12
-
12
µA
25
-
-
11
µA
Power OFF Leakage Current, ICOM+, ICOM- VDD = 0V, VCOM+ = 5.25V, VCOM- = 5.25V, OE/ALM = 0V
25
-
3.5
5
Ω
Full
-
-
7
Ω
25
-
0.2
0.45
Ω
Full
-
-
0.55
Ω
25
-
0.26
1
Ω
-
-
1.2
Ω
-
6.8
17
Ω
Power OFF Logic Current, IOE/ALM
VDD = 0V, OE/ALM = 5.25V
25
-
-
22
µA
Power OFF D+/D- Current, ID+, ID-
VDD = 0V, OE/ALM = VDD, VD+ = VD- = 5.25V
25
-
-
1
µA
Positive Fault-Protection Trip Threshold,
VPFP
VDD = 2.7V to 5.25V, OE/ALM = VDD
(see Table 1 on page 2)
25
3.62
3.8
3.95
V
Negative Fault-Protection Trip Threshold,
VNFP
VDD = 2.7V to 5.25V, OE/ALM = VDD
(see Table 1 on page 2)
25
-0.6
-0.45
-0.29
V
OFF Persistence Time
Fault Protection Response Time
Negative OVP Response: VDD = 2.7V, OE/ALM = VDD,
VDx = 0V to -5V, RL = 1.5kΩ
25
-
102
-
ns
Positive OVP Response: VDD = 2.7V, OE/ALM = VDD,
VDx = 0V to 5.25V, RL = 1.5kΩ
25
-
2
-
µs
Overvoltage Protection Detection
4
FN7614.1
September 12, 2013
ISL54226
Electrical Specifications - 2.7V to 5.25V Supply
Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH = 1.4V,
VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
ON Persistence Time
Fault Protection Recovery Time
TEMP
MIN
MAX
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
VDD = 2.7V, OE/ALM = VDD , VDx = 0V to 5.25V or 0V to
-5V, RL = 1.5kΩ
25
-
45
-
µs
Turn-ON Time, tON
VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF
(see Figure 3)
25
-
160
-
ns
Turn-OFF Time, tOFF
VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF
(see Figure 3)
25
-
60
-
ns
Skew, (tSKEWOUT - tSKEWIN)
VDD = 3.3V, OE/ALM = 3.3V, RL = 45Ω, CL = 10pF,
tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%)
(see Figure 7)
25
-
50
-
ps
Rise/Fall Degradation (Propagation
Delay), tPD
VDD = 3.3V, OE/ALM = 3.3V, RL = 45Ω, CL = 10pF,
(see Figure 7)
25
-
250
-
ps
Crosstalk
VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 6)
25
-
-39
-
dB
OFF-Isolation
VDD = 3.3V, OE/ALM = 0V, RL = 50Ω, f = 240MHz
25
-
-23
-
dB
DYNAMIC CHARACTERISTICS
-3dB Bandwidth
Signal = 0dBm, 0.86VDC offset, RL = 50Ω
25
-
790
-
MHz
OFF Capacitance, COFF
f = 1MHz, VDD = 3.3V, OE/ALM = 0V (see Figure 5)
25
-
2.5
-
pF
COM ON Capacitance, C(ON)
f = 1MHz, VDD = 3.3V, OE/ALM = 3.3V, (see Figure 5)
25
-
4
-
pF
COM ON Capacitance, C(ON)
f = 240MHz, VDD = 3.3V, OE/ALM = 3.3V
25
-
2
-
pF
Full
2.7
25
-
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
Positive Supply Current, IDD
VDD = 5.25V, OE/ALM = 5.25V
Positive Supply Current, IDD
VDD = 3.6V, OE/ALM = 3.6V
Positive Supply Current, IDD
VDD = 4.3V, OE/ALM = 2.6V
Positive Supply Current, IDD
VDD = 3.6V, OE/ALM = 1.4V
45
5.25
V
56
µA
Full
-
-
59
µA
25
-
23
30
µA
Full
-
-
34
µA
25
-
35
45
µA
Full
-
-
50
µA
25
-
25
32
µA
Full
-
-
38
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VOE/ALML
VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, VOE/ALMH
VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Voltage Low, VOE/ALML
VDD = 3.7V to 4.2V
Full
-
-
0.7
V
Input Voltage High, VOE/ALMH
VDD = 3.7V to 4.2
Full
1.7
-
-
V
Input Voltage Low, VOE/ALML
VDD = 4.3V to 5.25V
Full
-
-
0.8
V
Input Voltage High, VOE/ALMH
VDD = 4.3V to 5.25V
Full
2.0
-
-
V
Input Current, IOE/ALML
VDD = 5.25V, OE/ALM = 0V
Full
-
-8.2
-
nA
Input Current, IOE/ALMH
VDD = 5.25V, OE/ALM = 5.25V, 4MΩ Pull-down
Full
-
1.4
-
µA
NOTES:
10. VLOGIC = Input voltage to perform proper function.
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value.
15. Limits established by characterization and are not production tested.
5
FN7614.1
September 12, 2013
ISL54226
Test Circuits and Waveforms
VDD
LOGIC
INPUT
VDD
tr < 20ns
tf < 20ns
50%
0V
VINPUT
tOFF
SWITCH
INPUT VINPUT
VOUT
Dx
COMx
SWITCH
INPUT
OE/ALM
VOUT
90%
90%
SWITCH
OUTPUT
C
VIN
RL
50Ω
GND
0V
CL
50pF
tON
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (INPUT) -----------------------R L + r ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. SWITCHING TIMES
VDD
C
rON = V1/17mA
COMx
VHSDX
17mA
VDD
OE/ALM
V1
Dx
GND
Repeat test for all switches.
FIGURE 4. rON TEST CIRCUIT
VDD
VDD
C
C
SIGNAL
GENERATOR
COMx
COM+
OE/ALM
OE/ALM
IMPEDANCE
ANALYZER
VIN
0V OR
VDD
Dx
GND
50Ω
D+
COM-
D-
ANALYZER
GND
NC
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 5. CAPACITANCE TEST CIRCUIT
6
FIGURE 6. CROSSTALK TEST CIRCUIT
FN7614.1
September 12, 2013
ISL54226
Test Circuits and Waveforms (Continued)
VDD
C
tri
90%
10%
DIN+
50%
VDD
tskew_i
DIN-
90%
OE/ALM
15.8Ω
DIN+
50%
COM-
143Ω
10%
DIN-
tfi
tro
15.8Ω
OUT+
DCL
COM+
OUT-
D+
CL
143Ω
45Ω
45Ω
90%
10%
OUT+
50%
GND
tskew_o
OUT-
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
50%
90%
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
10%
tf0
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7B. TEST CIRCUIT
FIGURE 7. SKEW TEST
Application Block Diagram
3.3V
3.3V
500Ω
100kΩ
VDD
INT
3.6V
USB CONNECTOR
VBUS
>1MΩ
LOGIC
CONTROL
µCONTROLLER
OE/ALM
4MΩ
D-
COM -
D-
D+
OVP
DET
COM +
D+
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
GND
ISL54226
7
GND
PORTABLE MEDIA DEVICE
FN7614.1
September 12, 2013
ISL54226
Detailed Description
Curves” beginning on page 11.
The ISL54226 device is a dual single pole/single throw (SPST)
analog switch configured as a DPST that operates from a single
DC power supply in the range of 2.7V to 5.25V.
The Dx switches were specifically designed to pass USB 2.0
high-speed (480Mbps) differential signals in the range of 0V to
400mV. They have low capacitance and high bandwidth to pass
the USB high-speed signals with minimum edge and phase
distortion to meet USB 2.0 high-speed signal quality
specifications. See Figure 17 in the “Typical Performance Curves”
on page 12 for USB High-speed Eye Pattern taken with switch in
the signal path.
It was designed for switching a USB high-speed or full-speed
source in portable battery powered products. It is offered in small
µTQFN and TDFN packages for use in MP3 players, cameras,
PDAs, cellphones, and other personal media players.
The part consists of two 3.5Ω high-speed SPST switches. These
switches have high bandwidth and low capacitance to pass USB
high-speed (480Mbps) differential data signals with minimal
edge and phase distortion. They can also swing from 0V to 3.6V
to pass USB full speed (12Mbps) differential data signals with
minimal distortion.
The Dx switches can also pass USB full-speed signals (12Mbps) in
the range of 0V to 3.6V with minimal distortion and meet all the
USB requirements for USB 2.0 full-speed signaling. See Figure 18
in the “Typical Performance Curves” on page 13 for USB
Full-speed Eye Pattern taken with switch in the signal path.
The part contains special overvoltage detection and protection
(OVP) circuitry on the COM+ and COM- pins. This circuitry acts to
open the USB in-line switches when the part senses a voltage on
the COM pins that is >3.8V (typ) or < -0.45V (typ). It isolates
voltages up to 5.25V and down to -5V from getting through to the
other side of the switch to protect the USB transceiver connected
at the D+ and D- pins.
Overvoltage Protection (OVP)
The device has an open drain OE/ALM pin that can be driven
“Low” to open all switches. The OE/ALM pin gets internally pulled
“Low” whenever the part senses an overvoltage condition. The
pin must be externally pulled “High” with a 100kΩ pull-up resistor
and monitored for a “Low” to determine when an overvoltage
condition has occurred.
The part has charger port interrupt detection circuitry (CP) on the
COM pins that outputs a Low on the INT pin to inform the
µController or power management circuitry when entering a
dedicated charging port mode of operation. The charger mode
operation is initiated by driving the OE/ALM pin Low and
externally connecting the COM pins together which pulls the COM
lines High, triggering the INT pin to go Low and the SPST switches
to open.
The ISL54226 was designed for MP3 players, cameras,
cellphones, and other personal media player applications that
need to switch a high-speed or full-speed transceiver source. A
“Typical Application Block Diagram” of this functionality is shown
on page 7.
A detailed description of the SPST switches is provided in the
following section.
The switches are active (turned ON) whenever the OE/ALM
voltage is logic “1” (High) and OFF when the OE/ALM voltage is
logic “0” (Low).
The maximum normal operating signal range for the Dx switches
is from 0V to 3.6V. For normal operation the signal voltage
should not be allow to exceed these voltage levels or go below
ground by more than -0.3V.
However, in the event that a positive voltage >3.8V (typ) to 5.25V,
such as the USB 5V VBUS voltage, gets shorted to one or both of
the COM+ and COM- pins or a negative voltage < -0.45V (typ) to
-5V gets shorted to one or both of the COM pins, the ISL54226
has OVP circuitry to detect the over voltage condition and open
the SPST switches to prevent damage to the USB down-stream
transceiver connected at the signal pins (D-, D+).
The OVP and power-off circuitry allows the COM pins (COM-,
COM+) to be driven up to 5.25V while the VDD supply voltage is in
the range of 0V to 5.25V. In this condition the part draws <100µA
of ICOMx and IDD current and causes no stress to the IC. In
addition the SPST switches are OFF and the fault voltage is
isolated from the other side of the switch.
The OE/ALM pin gets internally pulled low whenever the part
senses an overvoltage condition. The pin must be externally
pulled “High” with a 100kΩ pull-up resistor and monitored for a
“Low” to determine when an overvoltage condition has occurred.
This output can be monitored by a µController to indicate a fault
condition to the system.
High-Speed (Dx) SPST Switches
The Dx switches are bi-directional switches that can pass USB
high-speed and USB full-speed signals when VDD is in the range
of 2.7V to 5.25V.
When powered with a 2.7V supply, these switches have a
nominal rON of 3.5Ω over the signal range of 0V to 400mV with a
rON flatness of 0.26Ω. The rON matching between the switches
over this signal range is only 0.2Ω, ensuring minimal impact by
the switches to USB high-speed signal transitions. As the signal
level increases, the rON switch resistance increases. At signal
level of 3.3V, the switch resistance is nominally 9.8Ω.
See Figures 11, 12, 13, 14, 15, 16 in the “Typical Performance
8
FN7614.1
September 12, 2013
ISL54226
External VDD Series Resistor to Limit IDD
Current during Negative OVP Condition
The series resistor also provides improved ESD and latch-up
immunity. During an overvoltage transient event (such as occurs
during system level IEC 61000 ESD testing), substrate currents
can be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from the
VDD power supply to ground. This will result in a significant
amount of current flow in the IC, which can potentially create a
latch-up state or permanently damage the IC. The external VDD
resistor limits the current during this overstress situation and has
been found to prevent latch-up or destructive damage for many
overvoltage transient events.
Under normal operation the low microamp IDD current of the IC
produces an insignificant voltage drop across the series resistor
resulting in no impact to switch operation or performance.
VSUPPLY
C
PROTECTION
RESISTOR
100Ω TO 1kΩ
-5V
FAULT
VOLTAGE
COM-
OVP
0
2.7V
100
200
300
400
500 600 700
RESISTOR (Ω)
INT
800
900
1k
FIGURE 9. NEGATIVE OVP IDD CURRENT vs RESISTOR VALUE vs
VSUPPLY
POWER
MANAGEMENT
BATTERY CHARGER
CIRCUITRY
VSUPPLY
VBUS
BATTERY
CHARGER
200Ω
D+ COM+
D-
“LOW” TO
INDICATE
CHARGER
CONNECTED
C
VDD
CHG DET
COM-
D+
D-
USB
TRANCEIVER
OE/ALM
LOGIC
GND
INT
µP
DRIVEN LOW BY µP
(OE/ALM = “0”)
FIGURE 10. CHARGER PORT DETECTION
LOW
TO
INDICATE
OVP
FIGURE 8. VDD SERIES RESISTOR TO LIMIT IDD CURRENT DURING
NEGATIVE OVP AND FOR ENHANCED ESD AND LATCHUP IMMUNITY
9
5
D+
OE/ALM
GND
3.6V
10
100kΩ
D-
LOGIC
15
GND
IDD
VDD
COM+
5.25V
USB CONNECTOR
With a negative -5V fault voltage at both com pins, the graph in
Figure 9 shows the IDD current draw for different external resistor
values for supply voltages of 2.7V, 3.6V, and 5.25V. Note: With a
500Ω resistor the current draw is limited to around 5mA. When
the negative fault voltage is removed the IDD current will return
to it’s normal operation current of 25µA to 45µA.
VCOM+ = VCOM- = -5V
20
IDD (mA)
A 100Ω to 1kΩ resistor in series with the VDD pin (see Figure 8)
is required to limit the IDD current draw from the system power
supply rail during a negative OVP fault event.
25
CHARGER PORT DETECTION
The ISL54226 has special charger port detection circuitry that
monitors the voltage at the com pins to detect when a battery
charger has been connected into the USB port (see Figure 10).
When the battery charger is connected to the USB connector it
shorts the COM+ and COM- pins together. The shorting of the pins
is sensed by the ISL54226 IC and it pulls the COM+ and COMlines high and as long as the OE/ALM pin is driven low
(OE/ALM = “0”) by the µP, it will drive its INT logic output “Low” to
tell the power management circuitry that a battery charger is
connected at the port and not a USB host transceiver. The power
management circuitry will then set the appropriate current level
and use the USB connector VBUS line to charge the battery.
FN7614.1
September 12, 2013
ISL54226
ISL54226 Operation
TABLE 2. LOGIC CONTROL VOLTAGE LEVELS
The following will discuss using the ISL54226 shown in the
“Application Block Diagram” on page 7.
Power
The power supply connected at the VDD pin provides the DC bias
voltage required by the ISL54226 part for proper operation. The
ISL54226 can be operated with a VDD voltage in the range of
2.7V to 5.25V.
For lowest power consumption you should use the lowest VDD
supply.
A 0.01µF or 0.1µF decoupling capacitor should be connected
from the VDD pin to ground to filter out any power supply noise
from entering the part. The capacitor should be located as close
to the VDD pin as possible.
In a typical application, VDD will be in the range of 2.8V to 4.3V
and will be connected to the battery or LDO of the portable
media device.
Logic Control
The state of the ISL54226 device is determined by the voltage at
the OE/ALM pin and the signal voltage at the COM pins. Refer to
“Truth Table” on page 2.
The OE/ALM pin is internally pulled low through 4MΩ resistors to
ground and can be tri-stated by a µProcessor.
The OE/ALM pin is an open drain connection. It should be pulled
high through an external 100kΩ pull-up resistor. The OE/ALM pin
can then be driven “Low” by a µProcessor to open all switches or
it can be monitored by the µProcessor for a “Low” when the part
goes into an overvoltage condition.
The ISL54226 is designed to minimize IDD current consumption
when the logic control voltage is lower than the VDD supply
voltage. With VDD = 3.6V and the OE/ALM logic pin is at 1.4V the
part typically draws only 25µA. With VDD = 4.3V and the OE/ALM
logic pin is at 2.6V the part typically draws only 35µA. Driving the
logic pin to the VDD supply rail minimizes power consumption.
LOGIC = “0” (LOW)
LOGIC = “1” (HIGH)
VDD SUPPLY RANGE
OE/ALM
OE/ALM
2.7V to 3.6V
≤0.5V
or
floating
≥1.4V
3.7V to 4.2V
≤0.7V
or
floating
≥1.7V
4.3V to 5.25V
≤0.8V
or
floating
≥2.0V
Normal Operation Mode
With a signal level in the range of 0V to 3.6V the switches will be
ON when the OE/ALM pin = Logic “1” and will be OFF (high
impedance) when the OE/ALM pin = Logic “0”.
USB 2.0 VBUS Short Requirements
The USB specification in section 7.1.1 states a USB device must
be able to withstand a VBUS short (4.4V to 5.25V) or a -1V short to
the D+ or D- signal lines when the device is either powered off or
powered on for at least 24 hours.
The ISL54226 part has special power-off protection and OVP
detection circuitry to meet these short circuit requirements. This
circuitry allows the ISL54226 to provide protection to the USB
down-stream transceiver connected at its signal pins (D-, D+) to
meet the USB specification short circuit requirements.
The power-off protection and OVP circuitry allows the COM pins
(COM-, COM+) to be driven up to 5.25V or down to -5V while the
VDD supply voltage is in the range of 0V to 5.25V. In these
overvoltage conditions with a 500Ω external VDD resistor the
part draws <55µA of current into the COM pins and causes no
stress/damage to the IC. In addition all switches are OFF and the
shorted VBUS voltage will be isolated from getting through to the
other side of the switch channels, thereby protecting the USB
transceiver.
The OE/ALM pin can be driven with a voltage higher than the VDD
supply voltage. It can be driven up to 5.25V with a VDD supply in
the range of 2.7V to 5.25V.
10
FN7614.1
September 12, 2013
ISL54226
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
16
3.4
ICOM = 17mA
2.7V
3.3
12
3.2
10
3.0V
rON (Ω)
rON (Ω)
ICOM = 17mA
14
3.3V
3.1
2.7V
8
3.0V
6
3.6V
4.3V
4
3.0
2.9
5.25V
0
0.1
0.2
2
0.3
0
0.4
0
0.6
1.2
2.4
3.0
3.6
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH
VOLTAGE
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH
VOLTAGE
18
V+ = 2.7V
ICOM = 17mA
V+ = 2.7V
16 ICOM = 17mA
4.0
14
+85°C
3.5
12
rON (Ω)
rON (Ω)
1.8
VCOM (V)
VCOM (V)
4.5
3.3V
5.25V
+25°C
3.0
2.5
-40°C
10
+85°C
8
+25°C
6
4
2.0
-40°C
2
1.5
0
0.1
0.2
0.3
0
0.4
0
0.5
1.0
VCOM (V)
1.5
2.0
VCOM (V)
2.5
3.0
3.5
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
9
4.0
V+ = 3.3V
ICOM = 17mA
8
+85°C
3.5
7
3.0
rON (Ω)
rON (Ω)
6
+25°C
5
+85°C
4
+25°C
2.5
3
-40°C
V+ = 3.3V
ICOM = 17mA
2.0
0
-40°C
2
0.1
0.2
0.3
VCOM (V)
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
11
0.4
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.6
VCOM (V)
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FN7614.1
September 12, 2013
ISL54226
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 3.3V
TIME SCALE (0.2ns/DIV)
FIGURE 17. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
12
FN7614.1
September 12, 2013
ISL54226
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
FIGURE 18. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
0.0
5.0
4.5
-0.5
4.0
VDD = 3.3V
VDD = 5.25V
IOL CURRENT (mA)
IOH CURRENT (mA)
3.5
-1.0
-1.5
VDD = 5.25V
-2.0
3.0
2.5
2.0
1.5
VDD = 3.3V
1.0
0.5
-2.5
0
1
2
3
4
VOH VOLTAGE (V)
FIGURE 19. IOH vs VOH vs VDD for INT
13
5
0.0
0
1
2
3
4
5
VOL VOLTAGE (V)
FIGURE 20. IOL vs VOL vs VDD for INT
FN7614.1
September 12, 2013
ISL54226
1
-10
0
-20
-1
-30
-2
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
-3
-4
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
-40
-50
-60
-70
-80
-90
-100
1M
10M
100M
1G
-110
0.001
0.01
FREQUENCY (Hz)
10M
100M
500M
FIGURE 22. OFF-ISOLATION
Die Characteristics
-10
RL = 50Ω
VIN = 0dBm, 0.2VDC BIAS
SUBSTRATE AND TDFN THERMAL PAD POTENTIAL
(POWERED UP):
-30
NORMALIZED GAIN (dB)
1M
FREQUENCY (Hz)
FIGURE 21. FREQUENCY RESPONSE
-20
0.1
GND
-40
TRANSISTOR COUNT:
-50
1297
-60
PROCESS:
-70
Submicron CMOS
-80
-90
-100
-110
0.001
0.01
0.1
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 23. CROSSTALK
14
FN7614.1
September 12, 2013
ISL54226
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
September 12, 2013
FN7614.1
Page 2, Pin Description table OE/ALM Description: changed the last line from: “Outputs a Low when OTV is
Activated” to: “Outputs are Low when OVP is Activated”
Page 4 - Updated ESD ratings from:
Human Body Model (Tested per JESD22-A114-F)..........>2kV
Machine Model (Tested per JESD22-A115-A)................>150V
Charged Device Model (Tested per JESD22-C101-D)......>2kV
to:
Human Body Model (Tested per JESD22-A114-F)..........>5.5kV
Machine Model (Tested per JESD22-A115-A)................>250V
Charged Device Model (Tested per JESD22-C101-D)......>2kV
July 29, 2010
FN7614.0
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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15
FN7614.1
September 12, 2013
ISL54226
Package Outline Drawing
L8.2x2C
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD
Rev 0, 07/08
2.00
6
PIN #1 INDEX AREA
A
B
6
PIN 1
INDEX AREA
8
1
0.50
2.00
1.45±0.050
Exp.DAP
(4X)
0.15
0.10 M C A B
0.25
( 8x0.30 )
TOP VIEW
0.80±0.050
Exp.DAP
BOTTOM VIEW
( 8x0.20 )
Package Outline
( 8x0.30 )
SEE DETAIL "X"
( 6x0.50 )
1.45
2.00
0.10 C
0 . 75 ( 0 . 80 max)
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 8x0.25 )
0.80
2.00
TYPICAL RECOMMENDED LAND PATTERN
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
16
FN7614.1
September 12, 2013
ISL54226
Package Outline Drawing
L8.1.4x1.2
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/09
0.80
REF
4X 0.40 BSC
1.40
A
PIN 1
INDEX AREA
PIN 1
INDEX AREA
B
6
8
0.30
1.20
C0.10
5
1
0.40
0.60
7X 0.30
0.10
2X
±0.05
2
4
0.10 M C A B
0.40 BSC
TOP VIEW
0.05 M C
4 8 X 0.20
BOTTOM VIEW
SEE DETAIL "X"
0.80
REF
MAX. 0.50
4X 0.40
PKG OUTLINE
0.10
C
C
SEATING PLANE
0.08
8 X 0.20
C
SIDE VIEW
0.60
0.60
7X 0.50
C
0 . 2 REF
0.70
0.60
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
17
FN7614.1
September 12, 2013
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