DATASHEET

Wideband Differential 3:1 Multiplexer
ISL54233
Features
The Intersil ISL54233 is a single supply differential 3 to 1
multiplexer that operates from a single supply in the range of
2.7V to 4.6V. It was designed to multiplex between three
different differential data sources, allowing the multiplexing of
USB 2.0 high speed data signals, UART data signals and digital
video through a common headphone connector in Personal
Media Players and other portable battery powered devices.
• High Speed (480Mbps) and Full Speed (12Mbps) Signaling
Capability per USB 2.0 on All Ports
The switch channels have low ON capacitance and high
bandwidth (1.6GHz) to pass USB high speed signals (480Mbps)
and digital video signals with minimal edge and phase distortion
and can swing rail-to-rail to pass UART and full-speed USB
signals.
• COM Pins Overvoltage Tolerant to 5.5V
All channels of the multiplexer can be turned OFF (disabled) by
driving the C0 and C1 logic pins to the low state.
• Available 12 Ld UTQFN and 12 Ld TQFN Packages
The ISL54233 is available in a tiny 12 Ld 2.2mmx1.4mm
ultra-thin QFN and 12 Ld 3mmx3mm TQFN package. It operates
over a temperature range of -40°C to +85°C.
• Pb-Free (RoHS Compliant)
Related Literature
• Digital Video Transmission
• COM Pins Allow Negative Swings to -2V
• All Switches OFF Mode
• Power OFF Protection
• Low ON Capacitance @ 240MHz . . . . . . . . . . . . . . . . . . 2.8pF
• -3dB Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6GHz
• Single Supply Operation (VDD) . . . . . . . . . . . . . . . . 2.7V to 4.6V
• Compliant with USB 2.0 Short Circuit Requirements Without
Additional External Components
Applications
• MP4 and Other Personal Media Players
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Mobile Phone/Smart Phone
• Tablets, Readers, GPS and MHL
1
3.3V
VBUS
C0
VDD
0
C1
3DLOGIC
3D+
4MΩ
2D-
DIGITAL
VIDEO
COM -
2D+
COM +
1D-
UART
1D+
USB/DATA JACK
USB
TRANSCEIVER
NORMALIZED GAIN (dB)
µCONTROLLER
-1
-2
-3
-4
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
ISL54233
GND
1M
10M
100M
1G
2G
FREQUENCY (Hz)
FIGURE 1. TYPICAL APPLICATION
December 21, 2011
FN7918.0
1
FIGURE 2. BANDWIDTH CHARACTERISTICS CURVE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL54233
Pin Configuration
12 LD 2.2X1.4 UTQFN
TOP VIEW
12 LD 3x3 TQFN
TOP VIEW
3D-
VDD
C0
3D-
VDD
C0
12
11
10
12
11
10
PD
3D+
LOGIC
CONTROL
1
9
C1
3D+
4MΩ
LOGIC
CONTROL
1
9
C1
4MΩ
2D-
2
8
COM -
2D+
3
7
COM +
2D-
2
8
COM -
2D+
3
7
COM +
4MΩ
4MΩ
4
5
6
1D-
1D+
GND
4
5
6
1D-
1D+
GND
NOTE:
1. ISL54233 switches shown for C1 = Logic “1” and C0 = Logic “0”.
Pin Descriptions
UTQFN
TQFN
NAME
1
1
2
Truth Table
FUNCTION
C1
C0
3D+
USB3/DV Differential Input
0
0
Wired-OR Audio
All switches open
2
2D-
USB2/DV Differential Input
0
1
USB/DV #1
1D- and 1D+ ON
3
3
2D+
USB2/DV Differential Input
1
0
USB/DV #2
2D- and 2D+ ON
4
4
1D-
USB1/DV Differential Input
1
1
USB/DV #3
3D- and 3D+ ON
5
5
1D+
USB1/DV Differential Input
6
6
GND
Ground Connection
7
7
COM+
Data Common Pin
8
8
COM-
Data Common Pin
9
9
C1
Digital Control Input
10
10
C0
Digital Control Input
11
11
VDD
Power Supply
12
12
3D-
USB3/DV Differential Input
-
PAD
PAD
Thermal Pad. Tie to Ground or Float
2
MODE
COMMENTS
C0, C1: Logic “0” when ≤ 0.5V or float, Logic “1” when ≥ 1.4V with VDD in
range of 2.7V to 3.6V.
FN7918.0
December 21, 2011
ISL54233
Ordering Information
PART
MARKING
TEMP. RANGE
(°C)
ISL54233IRUZ-T (Notes 2, 3)
HM
-40 to +85
12 Ld 2.2mmx1.4mm UTQFN (Tape and Reel)
L12.2.2x1.4A
ISL54233IRUZ-T7A (Notes 2, 3)
HM
-40 to +85
12 Ld 2.2mmx1.4mm UTQFN (Tape and Reel)
(250pc Reel)
L12.2.2x1.4A
ISL54233IRTZ (Note 4)
4233
-40 to +85
12 Ld 3mmx3mm TQFN
L12.3x3A
ISL54233IRTZ-T (Note 2, 4)
4233
-40 to +85
12 Ld 3mmx3mm TQFN (Tape and Reel)
L12.3x3A
PART NUMBER
PACKAGE
(Pb-Free)
PKG.
DWG. #
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54233. For more information on MSL please see techbrief TB363.
3
FN7918.0
December 21, 2011
ISL54233
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
Input Voltages
1D+, 1D-, 2D+, 2D-, 3D+, 3D- . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 5.5V
C0, C1 (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
Output Voltages
COM-, COM+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 5.5V
Continuous Current (1D-, 1D+, 2D-, 2D+, 3D-, 3D+). . . . . . . . . . . . . . . . . ±40mA
Peak Current (1D-, 1D+, 2D-, 2D+, 3D-, 3D+)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . >5kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . >400V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . >2kV
Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . . . . at +85°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
12 Ld UTQFN Package (Notes 7, 10) . . . . .
155
90
12 Ld TQFN Package (Notes 8, 9) . . . . . . .
58
1.0
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 4.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. Signals on C1 and C0 exceeding GND by specified amount are clamped. Limit current to maximum current ratings.
7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
10. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications - 2.7V to 3.6V Supply
Test Conditions: VDD = +3.0V, GND = 0V, VC0H, VC1H = 1.4V, VC0L, VC1L = 0.5V,
(Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes
12, 13)
TYP
MAX
(Notes
12, 13)
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
VDD = 2.7V to 4.6V
Full
-1
-
VDD
V
ON-Resistance, rON
VDD = 2.7V, ICOMx = 17mA, VD+ or VD- = 0V to 400mV
(see Figure 5, Note 15)
25
-
6
8
Ω
rON Matching Between Channels, ΔrON VDD = 2.7V, ICOMx = 17mA, VD+ or VD- = Voltage at max rON,
(Notes 15, 16)
rON Flatness, rFLAT(ON)
VDD = 2.7V, ICOMx = 17mA, VD+ or VD- = 0V to 400mV,
(Notes 14, 15)
ON-Resistance, rON
VDD = 3.3V, ICOMx = 17mA, VD+ or VD- = 3.3V (see Figure 5,
Note 15)
OFF Leakage Current, IXD+(OFF) or
IXD-(OFF), ICOMX(OFF)
VDD = 4.6V, All OFF Mode (C0 = 0.5V, C1 = 0.5V), VCOM- or
VCOM+ = 0.3V, 3.3V, VXD+ or VXD- = 3.3V, 0.3V
ON Leakage Current, IXD+(ON) or
IXD-(ON), ICOMX(ON)
VDD = 4.6V, VXD+ or VXD- = 0.3V, 3.3V, VCOM- or VCOM+ = 0.3V,
3.3V
Full
-
-
10
Ω
25
-
0.07
0.5
Ω
Full
-
-
0.55
Ω
25
-
0.32
0.8
Ω
Full
-
-
1.2
Ω
+25
-
9.5
15
Ω
Full
-
-
20
Ω
25
-15
-
15
nA
Full
-20
-
20
nA
25
-20
-
20
nA
Full
-25
-
25
nA
VDD = 2.7V, RL = 50Ω, CL = 10pF, (see Figure 3)
25
-
125
-
ns
Data Channel to Data Channel Address VDD = 2.7V, RL = 50Ω, CL = 10pF, (see Figure 3)
Transition Time, tTRANS
25
-
125
-
ns
Break-Before-Make Time Delay, tD
VDD = 3.6V, RL = 50Ω, CL = 10pF, (see Figure 4)
25
-
30
-
ns
Skew, (tSKEWOUT - tSKEWIN)
VDD = 3.0V, RL = 45Ω, CL = 10pF, tR = tF = 500ps at 480Mbps,
(Duty Cycle = 50%) (see Figure 8)
25
-
75
-
ps
Total Jitter, tJ
VDD = 3.0V, RL = 50Ω, CL = 10pF, tR = tF = 500ps at 480Mbps
25
-
210
-
ps
DPDT DYNAMIC CHARACTERISTICS
All OFF to ON or ON to All OFF Address
Transition Time, tTRANS
4
FN7918.0
December 21, 2011
ISL54233
Electrical Specifications - 2.7V to 3.6V Supply
Test Conditions: VDD = +3.0V, GND = 0V, VC0H, VC1H = 1.4V, VC0L, VC1L = 0.5V,
(Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
TYP
MAX
(Notes
12, 13)
Rise/Fall Degradation (Propagation
Delay), tPD
VDD = 3.0V, RL = 45Ω, CL = 10pF, (see Figure 8)
25
-
250
-
ps
Crosstalk
VDD = 3.0V, RL = 50Ω, f = 240MHz
25
-
-36
-
dB
OFF-Isolation
VDD = 3.0V, RL = 50Ω, f = 240MHz
25
-
-32
-
dB
-3dB Bandwidth
Signal = 0dBm, 0.2VDC offset, RL = 50Ω
25
-
1.6
-
GHz
OFF Capacitance, CXD+OFF, CXD-OFF
f = 1MHz, VDD = 3.0V (see Figure 6)
25
-
3
-
pF
COM ON Capacitance, CCOM-(ON),
CCOM+(ON)
f = 1MHz, VDD = 3.0V (see Figure 6)
25
-
6
-
pF
COM ON Capacitance, CCOM-(ON),
CCOM+(ON)
f = 240MHz, VDD = 3.0V
25
-
2.8
-
pF
Full
2.7
4.6
V
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes
12, 13)
UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
Positive Supply Current, IDD
(ALL OFF Mode)
VDD = 3.6V, C1 = GND, C0 = GND
Positive Supply Current, IDD
(USB1 Mode)
VDD = 3.6V, C1 = GND, C0 = VDD
Positive Supply Current, IDD
(USB2 Mode)
VDD = 3.6V, C1 = VDD, C0 = GND
Positive Supply Current, IDD
(USB3 Mode)
VDD = 3.6V, C0 = C1 = VDD
Power OFF COMx Current, ICOMx
VDD = 0V, C0 = C1 = Float, COMx = 5.25V
Power OFF Logic Current, IC0, IC1
VDD = 0V, C0 = C1 = 5.25V
Power OFF D+/D- Current, IXD+, IXD-
VDD = 0V, C0 = C1 = Float, XD- = XD+ = 5.25V
C0, C1 Voltage Low, VC0L, VC1L
VDD = 2.7V to 3.6V
C0, C1 Voltage High, VC0H, VC1H
C0, C1 Input Current, IC0L, IC1L
25
-
6.5
8
µA
Full
-
-
15
µA
25
-
6.5
8
µA
Full
-
-
15
µA
25
-
6.5
8
µA
Full
-
-
15
µA
25
-
6.5
8
µA
Full
-
-
15
µA
25
-
-
1
µA
25
-
11
-
µA
25
-
5
-
µA
Full
-
-
0.5
V
VDD = 2.7V to 3.6V
Full
1.4
-
5.25
V
VDD = 3.6V, C0 = C1 = 0V or Float
Full
-50
6.2
50
nA
C0, C1 Input Current, IC0H, IC1H
VDD = 3.6V, C0 = C1 = 3.6V
Full
-2
1.6
2
µA
C0, C1 Pull-Down Resistor, RCx
VDD = 3.6V, C0 = C1 = 3.6V, Measure current into C0 or C1 pin
and calculate resistance value.
Full
-
4
-
MΩ
DIGITAL INPUT CHARACTERISTICS
NOTES:
11. Vlogic = Input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
15. Limits established by characterization and are not production tested.
16. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value,
between 1D+ and 1D- or between 2D+ and 2D- or between 3D+ and 3D-.
5
FN7918.0
December 21, 2011
ISL54233
Test Circuits and Waveforms
VC0,C1
LOGIC
INPUT
VC0,C1
50%
VINPUT
tOFF
SWITCH
V
INPUT INPUT
VOUT
SWITCH
INPUT
COMx
C0, C1
VOUT
90%
SWITCH
OUTPUT
C
VDD
tr < 20ns
tf < 20ns
90%
LOGIC
INPUT
0V
CL
10pF
RL
50Ω
GND
tON
Logic input waveform is inverted for switches that have the opposite logic
sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(INPUT) R + r
L
ON
FIGURE 3A. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 3B. ADDRESS tTRANS TEST CIRCUIT
FIGURE 3. SWITCHING TIMES
VDD
C
3D- OR 3D+
VC0
LOGIC
INPUT
2D- OR 2D+
VINPUT
VC1
VOUT
COMx
1D- OR 1D+
SWITCH
OUTPUT
VOUT
90%
0V
CL
10pF
RL
50Ω
C0, C1
GND
LOGIC
INPUT
tD
Repeat test for all switches. CL includes fixture and stray capacitance.
FIGURE 4B. TEST CIRCUIT
FIGURE 4A. MEASUREMENT POINTS
FIGURE 4. BREAK-BEFORE-MAKE TIME
VDD
C
VDD
rON = V1/17mA
C
CTRL
xD- OR xD+
xD- OR xD+
VD- OR VD+
C0
V1
17mA
C1
0V
VDD
VCx
IMPEDANCE
ANALYZER
VCxL OR
VCxH
COMx
COMx
GND
GND
Repeat test for all switches.
Repeat test for all switches.
FIGURE 5. rON TEST CIRCUIT
6
FIGURE 6. CAPACITANCE TEST CIRCUIT
FN7918.0
December 21, 2011
ISL54233
Test Circuits and Waveforms (Continued)
VDD
C
CTRL
SIGNAL
GENERATOR
xD-
50Ω
COMx
VCx
0V OR FLOAT
COMx
ANALYZER
50Ω
xD+
N.C.
GND
FIGURE 7. CROSSTALK TEST CIRCUIT
VDD
C
tri
90%
DIN+
DIN-
50%
10%
tskew_i
90%
0V
C0
VDD
C1
15.8Ω
DIN+
50%
COM+
DIN-
15.8Ω
CL
COM-
CL
143Ω
OUT-
10%
50%
tskew_o
50%
90%
45Ω
OUT-
D-
90%
OUT+
OUT+
D+
143Ω
10%
tfi
tro
VDD
45Ω
GND
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals
tf0
10%
|tskew_0| Change in Skew through the Switch for Output Signals
|tskew_i| Change in Skew through the Switch for Input Signals
FIGURE 8A. MEASUREMENT POINTS
FIGURE 8B. TEST CIRCUIT
FIGURE 8. SKEW TEST
7
FN7918.0
December 21, 2011
ISL54233
Application Block Diagram
3.3V
µCONTROLLER
100Ω
VDD
3D3D+
C0
LOGIC CONTROL
4MΩ
2D-
DIGITAL
VIDEO
C1
COM -
2D+
COM +
1D-
UART
1D+
GND
AUDIO
CODEC
ISL54233
HEAD
PHONE
JACK
ISL54406
Detailed Description
The ISL54233 device consists of dual SP3T (single pole/triple
throw) analog switches. It operates from a single DC power
supply in the range of 2.7V to 4.6V. It was designed to function as
a differential 3 to 1 multiplexer to select between three different
differential data signals. It is offered in tiny UTQFN and TQFN
packages for use in MP3 players, PDAs, cellphones, and other
personal media players.
The device consists of six 6Ω data switches. It was designed to
pass high-speed USB differential data and digital video signals
with minimal edge and phase distortion. It can swing rail-to-rail to
pass UART and full-speed USB signals.
The COM pins can accept signals that swing below ground by as
much as -2V. This allows an audio source to be wired-OR
connected at the COM pins.
The ISL54233 was specifically designed for MP3 players,
personal media players and cellphone applications that need to
combine three differential data channels into a single shared
connector, thereby saving space and component cost. This
functionality is shown in the Typical Application Block Diagram
on page 1.
VBUS
USB/DATA JACK
USB
TRANSCEIVER
These switches can also swing rail-to-rail and pass USB full-speed
(12Mbps) and UART signals with minimal distortion. See
Figure 17 for USB full-speed Eye Pattern taken with the switch in
the signal path.
The maximum normal operating signal range for the USB
switches is from -1V to VDD. The signal voltage at D- and D+
should not be allowed to exceed the VDD voltage rail or go below
ground by more than -1V for normal operation.
Fault Protection and Power-Off Protection
However, in the event that the USB 5.25V VBUS voltage were
shorted to one or both of the COM pins, the ISL54233 has fault
protection circuitry to prevent damage to the ISL54233 part. The
fault circuitry allows the signal pins (COM-, COM+, 1D-, 1D+, 2D-,
2D+, 3D-, 3D+) to be driven up to 5.25V while the VDD supply
voltage is in the range of 0V to 4.6V. This fault condition causes
no stress to the IC.
In addition, when VDD is at 0V (ground) all switches are OFF and
the fault voltage is isolated from the other side of the switch
(Power-Off Protection).
A detailed description of the switches is provided in the following
sections.
When VDD is in the range of 2.7V to 4.6V, the fault voltage will
pass through to the output of an active switch channel.
Note: During the fault condition, normal operation is not
guaranteed until the fault condition is removed.
Data Switches
ISL54233 Operation
The six data switches (1D+, 1D-, 2D+, 2D-, 3D+, 3D-) are 6Ω
bidirectional switches that were specifically designed to pass
high-speed USB differential data signals in the range of 0V to
400mV. The switches have low capacitance and high bandwidth
to pass USB high-speed signals (480Mbps) with minimum edge
and phase distortion to meet USB 2.0 signal quality
specifications. See Figures 15 and 16 for high-speed Eye Pattern
taken with the switch in the signal path.
The discussion that follows will discuss using the ISL54233 in the
“Application Block Diagram” on page 8.
8
FN7918.0
December 21, 2011
ISL54233
POWER
USB/DV 1 Mode
The power supply connected at VDD (pin 11) provides power to
the ISL54233 part. Its voltage should be kept in the range of
2.7V to 4.6V. In a typical application, VDD will be in the range of
2.7V to 4.3V and will be connected to the battery or LDO of the
MP3 player or cellphone.
If the C1 pin = Logic “0” and C0 pin = Logic “1” the part will go
into USB/DV1 mode. The 1D- and 1D+ switches are ON and the
2D- and 2D+ switches and 3D- and 3D+ will be OFF (high
impedance).
A 0.01µF or 0.1µF decoupling capacitor should be connected
from the VDD pin to ground to filter out any power supply noise
from entering the part. The capacitor should be located as close
to the VDD pin as possible.
If the C1 = Logic “1” and C0 pin = Logic “0” the part will be in the
USB/DV2 mode. The 2D- and 2D+ switches will be ON and the
1D- and 1D+ switches and the 3D- and 3D+ will be OFF (high
impedance).
LOGIC CONTROL
USB/DV 3 Mode
The state of the ISL54233 device is determined by the voltage at
the C1 pin (pin 9) and the C0 pin (pin 10). Refer to the “Truth
Table” on page 2.
If the C1 pin = Logic “1” and C0 pin = Logic “1” the part will be in
the USB/DV3 mode. The 3D- and 3D+ switches are ON, and the
1D- and 1D+ switches and 2D- and 2D+ switches will be OFF
(high impedance).
The C1 pin and C0 pin are internally pulled low through 4MΩ
resistors to ground and can be tri-stated or left floating.
The C1 pin and C0 pin can be driven with a voltage that is higher
than the VDD supply voltage. They can be driven up to 5.25V with
the VDD supply in the range of 2.7V to 4.6V. Driving the logic
higher than the supply rail will cause the logic current to
increase. With VDD = 2.7V and VLOGIC = 5.25V, ILOGIC current is
approximately 5.5µA.
Logic Control Voltage Levels
With VDD in the range of 2.7V to 3.6V the logic levels are: C1,
C0 = Logic “0” (Low) when ≤ 0.5V or Floating. C1, C0 = Logic “1”
(High) when ≥ 1.4V.
ALL SWITCHES OFF Mode
If the C1 pin = Logic “0” and C0 pin = Logic “0” the part will be in
the ALL SWITCHES OFF mode. In this mode, the 3D- and 3D+
data switches, the 2D- and 2D+ data switches, and the 1D- and
1D+ data switches will be OFF (high impedance).
The COM pins can accommodate signals that swing below
ground by as much as -2V. This allows an audio CODEC to be
connected to the COM pins when the device is in the all off state.
USB/DV 2 Mode
Printed Circuit Board Design for High
Frequency Performance
In 50Ω systems, the ISL54233 has a -3dB bandwidth of 1.6GHz
(see Figure 19).
To achieve this high bandwidth requires careful design and layout
of the PCB board. Signal traces must be designed to minimize
reflections and reduce parasitic resistance, inductance and
capacitance that degrade the frequency response performance.
Figure 9 shows a picture of the engineering board used to
measure the frequency response of the ISL54233 part. The
board was specifically design for taking high frequency
bandwidth measurements. The board was made with special
materials and was carefully layed out using RF board techniques
to maximize it for high frequency operation.
The next section, “Board Layout Guidelines”, will provide a list of
the PCB board requirements needed to get the maximum
bandwidth from the ISL54233 part when tested with a 50Ω
Network Analyzer.
FIGURE 9. RF HIGH FREQUENCY BOARD
9
FN7918.0
December 21, 2011
ISL54233
BOARD LAYOUT GUIDELINES
• The ISL54233 device must be soldered directly onto the
PCB board. No IC sockets can be used. Their parasitic
impedance will degrade the frequency performance.
• Route all controlled impedance signal lines on the top
(signal) layer with no vias or through holes. Vias or through
holes make it difficult to maintain a controlled impedance
and tend to generate reflections.
• The signal traces (1D+, 1D-, 2D+, 2D-, 3D+, 3D-, COM- and
COM+) must have a controlled (characteristic) impedance of
50Ω ±5%. Tight control on trace width and dielectric
thickness must be followed to get 50Ω lines. Impedance
tests results for controlled lines should be requested from
the board fabrication house.
• The signal trace lengths should be as short ( <1 inch from
SMA connector to the switch pin) and straight as possible. If
it becomes necessary to turn 90°, use two 45° turns or an
arc instead of making a single 90° turn. This reduces
reflections on the signal by minimizing impedance
discontinuities.
• A four layer PCB board: Signal (top) layer), Thin-Dielectric,
GND (2nd layer), Thick-Dielectric, GND (3rd layer),
Thin-Dielectric, Signal (Bottom layer) is required to achieve
50Ω traces. The top and bottom thin-dielectric are Nelco
4000-13 or Rogers 4350 core type material. The center
thick-dielectric is FR4 pre-preg material.
Figure 10 illustrates the material and sequencing of the
layers. The dimensions called out are those required to
achieve 50Ω microstrip for the signal traces.
• Use Edge - Launch SMA connectors for all signal lines. The
SMA connector terminal should be tapered to the signal
trace.
GND
10 mil
TRACE
GND
TOP (SIGNAL) LAYER
5 mil
ROGERS 4350 CORE
GND LAYER
52 mil
FR4 PRE-PREG
GND LAYER
5 mil
ROGERS 4350 CORE
BOTTOM LAYER
FIGURE 10. FOUR LAYER BOARD STACK-UP
10
• Ground stitching should be done along signal traces and
around SMA ground connectors. This helps to isolate the
trace in a ground conduit. This reduces capacitive coupling
between traces and provides a good return path for the
signal.
• Use dry film solder mask. Clear the solder mask from signal
trace.
• Power and/or logic lines can be run on the bottom layer.
Logic lines should be routed away from the signal lines. This
will minimize capacitive coupling from the logic lines.
• A 4.7µF capacitor is placed from VCC to GND where the power
is brought onto the board. It keeps any low frequency noise
from getting on the board. Since a bulk capacitor will look
inductive at higher frequencies, an additional 0.1µF capacitor
is placed across the supply lines. A 0.01µF decoupling
capacitor needs to be connected from the VDD pin to ground
of the ISL54233 part to filter out any power supply noise from
entering the part. The capacitor should be a RF type chip
capacitor and should be located as close to the VDD pin as
possible. Note: RF type capacitors have a smaller foot-print
than regular capacitors.
FN7918.0
December 21, 2011
ISL54233
Typical Performance Curves
6.7
TA = +25°C, Unless Otherwise Specified.
9
ICOM = 40mA
VDD = 2.7V
6.6
VDD = 2.7V
ICOM = 40mA
+85°C
8
6.5
7
VDD = 3.0V
6.3
rON (Ω)
rON (Ω)
6.4
VDD = 3.3V
6.2
VDD = 3.6V
6.1
+25°C
6
-40°C
5
6.0
VDD = 4.6V
5.9
5.8
0
0.05
0.10
0.15
0.20
0.25
VCOM (V)
4
VDD = 4.0V
0.30
0.35
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
9
3
0.40
16
ICOM = 40mA
+85°C
0.15
0.20
0.25
VCOM (V)
0.30
0.35
0.40
12
+25°C
rON (Ω)
rON (Ω)
0.10
VDD = 3.3V
ICOM = 40mA
14
7
6
-40°C
5
+85°C
10
8
+25°C
6
-40°C
4
3
0.05
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE vs TEMPERATURE
VDD = 3.3V
8
0
4
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
VCOM (V)
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE vs TEMPERATURE
11
2
0
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.3
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE vs TEMPERATURE
FN7918.0
December 21, 2011
ISL54233
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 2.7V
USB NEAR END MASK
TIME SCALE (0.2ns/DIV)
FIGURE 15. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
12
FN7918.0
December 21, 2011
ISL54233
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 2.7V
USB FAR END MASK
TIME SCALE (0.2ns/DIV)
FIGURE 16. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
13
FN7918.0
December 21, 2011
ISL54233
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
VOLTAGE SCALE (0.5V/DIV)
VDD = 2.7V
TIME SCALE (10ns/DIV)
FIGURE 17. EYE PATTERN: 12Mbps USB SIGNAL WITH USB SWITCHES IN THE SIGNAL PATH
14
FN7918.0
December 21, 2011
ISL54233
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
1
-20
-40
0
-60
-1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
-80
-100
-2
-3
-4
-120
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
-140
0.001
0.01
0.1
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 18. OFF-ISOLATION USB SWITCHES
1M
10M
100M
1G
2G
FREQUENCY (Hz)
FIGURE 19. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE AND TQFN THERMAL PAD POTENTIAL
(POWERED UP):
GND
TRANSISTOR COUNT:
837
PROCESS:
Submicron CMOS
15
FN7918.0
December 21, 2011
ISL54233
Revision History
DATE
REVISION
December 21, 2011
FN7918.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL54233
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN7918.0
December 21, 2011
ISL54233
Package Outline Drawing
L12.3x3A
12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE
Rev 0, 09/07
3.00
0.5
BSC
A
B
6
12
10
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
4X 1.45
3.00
9
7
3
0.10 M C A B
(4X)
0.15
4
6
0.25 +0.05 / -0.07
4
12X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 75
C
BASE PLANE
( 2 . 8 TYP )
1.45 )
SEATING PLANE
0.08 C
(
SIDE VIEW
0.6
C
0 . 50
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
0 . 25
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
17
FN7918.0
December 21, 2011
ISL54233
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L12.2.2x1.4A
D
6
INDEX AREA
2X
A
B
12 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
N
E
0.10 C
1
2X
2
0.10 C
MIN
NOMINAL
A
0.45
A1
-
A3
TOP VIEW
0.10 C
C
A1
A
SYMBOL
0.05 C
LEADS COPLANARITY
SIDE VIEW
MAX
NOTES
0.50
0.55
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.15
2.20
2.25
-
E
1.35
1.40
1.45
-
e
0.40 BSC
-
k
0.20
-
-
-
L
0.35
0.40
0.45
-
N
12
2
Nd
3
3
Ne
3
3
θ
0
-
12
4
Rev. 0 12/06
NOTES:
(DATUM A)
PIN #1 ID
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
1
NX L
2
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side, respectively.
e
Ne
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM B)
NX b
5
0.10 M C A B
0.05 M C
Nd
3
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
BOTTOM VIEW
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
CL
NX (b)
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
(A1)
L
5
1.50
e
SECTION "C-C"
C C
TERMINAL TIP
2.30
1
2
0.40
3
0.45 (12x)
0.25 (12x)
0.40
TYPICAL RECOMMENDED LAND PATTERN
18
10
FN7918.0
December 21, 2011
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