DATASHEET

ISL6262
®
Data Sheet
Two-Phase Core Regulator for IMVP-6
Mobile CPUs
The ISL6262 is a two-phase buck converter regulator
implementing Intel® IMVP-6 protocol, with embedded gate
drivers. The two-phase buck converter uses two interleaved
channels to effectively double the output voltage ripple
frequency and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller real estate area.
The heart of the ISL6262 is R3 Technology™, Intersil’s
Robust Ripple Regulator modulator. Compared with the
traditional multiphase buck regulator, the R3 Technology™
has the fastest transient response. This is due to the R3
modulator commanding variable switching frequency during
a load transient.
Intel Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology, which effectively reduces power
dissipation in Intel Pentium processors. To boost battery life,
the ISL6262 supports DPRSLRVR (deeper sleep),
DPRSTP# and PSI# functions and maximizes the efficiency
via automatically enabling different phase operation modes.
At heavy load operation of the active mode, the regulator
commands the two phase continuous conduction mode
(CCM) operation. While the PSI# is asserted at the medium
load in the active mode, the ISL6262 smoothly disables one
phase and operates in a one-phase CCM. When the CPU
enters deeper sleep mode, the ISL6262 enables diode
emulation to maximize the efficiency at the light load.
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
A 0.5% system accuracy of the core output voltage over
temperature is achieved by the ISL6262.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per Intel IMVP-6
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or precision resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
1
May 15, 2006
FN9199.2
Features
• Precision Two-phase CORE Voltage Regulator
- 0.5% System Accuracy Over Temperature
- Enhanced load line accuracy
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Support VID Change on-the-fly
• Multiple Current Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Thermal Monitor
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
ISL6262CRZ
(Note)
PART
MARKING
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL6262CRZ-T ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
ISL6262IRZ
(Note)
ISL6262IRZ
-40 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL6262IRZ-T ISL6262IRZ
(Note)
-40 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6262
Pinout
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISL6262 (7x7 QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
1
36 BOOT1
PSI#
2
35 UGATE1
PGD_IN
3
34 PHASE1
RBIAS
4
33 PGND1
VR_TT#
5
32 LGATE1
NTC
6
SOFT
7
OCSET
8
29 PGND2
VW
9
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FB2 12
2
13
14
15
16
17
18
19
20
21
22
23
24
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
GND
VDD
ISEN2
ISEN1
25 NC
FN9199.2
May 15, 2006
ISL6262
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 -+7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . . -0.3 -+7V
Thermal Resistance (Typical)
θJA°C/W
θJC°C/W
QFN Package (Notes 1, 2). . . . . . . . . .
29
4.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . -10°C to 100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to 125°C
Ambient Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 100°C
Junction Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 5V, TA = -40°C to 100°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VR_ON = 3.3V
-
3.1
3.6
mA
VR_ON = 0V
-
-
1
µA
INPUT POWER SUPPLY
+5V Supply Current
IVDD
+3.3V Supply Current
I3V3
No load on CLK_EN#
-
-
1
µA
Battery Supply Current at VIN pin
IVIN
VR_ON = 0V, VIN = 25V,
-
-
1
µA
POR (Power-On Reset) Threshold
PORr
VDD Rising
-
4.35
4.5
V
PORf
VDD Falling
3.9
4.1
-
V
No load, closed loop, active mode,
TA = 0°C to 100°C, VID = 0.75-1.5V
-0.5
-
0.5
%
VID = 0.5-0.7375V
-8
-
8
mV
VID = 0.3-0.4875V
-15
-
15
mV
TA = -40°C to 100°C, VID = 0.75-1.5V
-0.8
-
0.8
%
VID = 0.5-0.7375V
-10
-
10
mV
VID = 0.3-0.4875V
-18
-
18
mV
RRBIAS = 147kΩ
1.45
1.47
1.49
V
1.188
1.2
1.212
V
SYSTEM AND REFERENCES
System Accuracy
%Error
(Vcc_core)
ISL6262CRZ
%Error
(Vcc_core)
ISL6262IRZ
RBIAS Voltage
RRBIAS
Boot Voltage
VBOOT
Maximum Output Voltage
VCC_CORE
(max)
VID = [0000000]
-
1.5
-
V
VCC_CORE
(min)
VID = [1100000]
-
0.3
-
V
VID = [1111111]
-
0
-
V
RFSET = 3.9kΩ, 2 channel operation,
Vcomp = 2V
-
300
-
kHz
200
-
500
kHz
VID Off State
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW
Adjustment Range
3
FN9199.2
May 15, 2006
ISL6262
Electrical Specifications
VDD = 5V, TA = -40°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-0.3
-
0.3
mV
-
90
-
dB
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
AV0
Error Amp Gain-Bandwidth Product
GBW
CL = 20pF
-
18
-
MHz
SR
CL = 20pF
-
5
-
V/µs
-
10
150
nA
Imbalance Voltage
-
-
1
mV
Input Bias Current
-
20
-
nA
-47
-41
-35
µA
±170
±200
±230
µA
Error Amp Slew Rate
FB Input Current
IIN(FB)
ISEN
SOFT-START CURRENT
Soft-Start Current
ISS
Soft Geyserville Current
IGV
|SOFT - REF|>100mV
Soft Deeper Sleep Entry Current
IC4
DPRSLPVR = 3.3V
-47
-41
-35
µA
Soft Deeper Sleep Exit Current
IC4EA
DPRSLPVR = 3.3V
35
41
47
µA
Soft Deeper Sleep Exit Current
IC4EB
DPRSLPVR = 0V
170
200
230
µA
GATE DRIVER DRIVING CAPABILITY
UGATE Source Resistance
RSRC(UGATE)
500mA Source Current
-
1
1.5
Ω
UGATE Source Current
ISRC(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
UGATE Sink Resistance
RSNK(UGATE)
500mA Sink Current
-
1
1.5
Ω
UGATE Sink Current
ISNK(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
LGATE Source Resistance
RSRC(LGATE)
500mA Source Current
-
1
1.5
Ω
LGATE Source Current
ISRC(LGATE)
VLGATE = 2.5V
-
2
-
A
LGATE Sink Resistance
RSNK(LGATE)
500mA Sink Current
-
0.5
0.9
Ω
LGATE Sink Current
ISNK(LGATE)
VLGATE = 2.5V
-
4
-
A
-
1.1
-
kΩ
UGATE to PHASE Resistance
Rp(UGATE)
GATE DRIVER SWITCHING TIMING (refer to timing diagram)
UGATE Turn-On Propagation Delay
TA = -10°C to 100°C
PVCC = 5V, Outputs Unloaded
20
30
44
ns
ISL6262CRZ
tPDHU
PVCC = 5V, Outputs Unloaded
18
30
44
ns
7
15
30
ns
ISL6262CRZ
TA = -10°C to 100°C
PVCC = 5V, Outputs Unloaded
tPDHL
PVCC = 5V, Outputs Unloaded
5
15
30
ns
0.43
0.58
0.72
V
tPDHU
ISL6262IRZ
LGATE Turn-On Propagation Delay
tPDHL
ISL6262IRZ
BOOTSTRAP DIODE
Forward Voltage
VDDP = 5V, Forward Bias Current = 2mA
Leakage
VR = 16V
-
-
1
µA
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
VOL
IPGOOD = 4mA
-
0.11
0.4
V
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
-
1
µA
4
FN9199.2
May 15, 2006
ISL6262
Electrical Specifications
VDD = 5V, TA = -40°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
PGOOD Delay
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TA = -10°C to 100°C
CLK_EN# Low to PGOOD High
5.5
6.8
8.1
ms
ISL6262CRZ
tpgd
CLK_EN# Low to PGOOD High
5.3
6.8
8.1
ms
OVH
VO rising above setpoint > 1ms
160
200
240
mV
OVHS
VO rising above setpoint > 0.5µs
1.675
1.7
1.725
V
tpgd
ISL6262IRZ
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
I(Rbias) = 10µA
9.8
10
10.2
µA
OC Threshold Offset
DROOP rising above OCSET > 120µs
-3.5
-
3.5
mV
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 > 1ms
-
7.5
-
mV
-365
-300
-240
mV
Undervoltage Threshold
(VDIFF-SOFT)
UVf
VO falling below setpoint for > 1ms
LOGIC INPUTS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL
-
-
1
V
VR_ON, DPRSLPVR and PGD_IN
Input High
VIH
2.3
-
-
V
Leakage Current of VR_ON and
PGD_IN
IIL
Logic input is low
-1
0
-
µA
IIH
Logic input is high at 3.3V
-
0
1
µA
IIL_DPRSLP
DPRSLPVR input is low
-1
0
-
µA
IIH_DPRSLP
DPRSLPVR input is high at 3.3V
-
0.45
1
µA
Leakage Current of DPRSLPVR
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
VIL
-
-
0.3
V
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH
0.7
-
-
V
Leakage Current of DAC(VID0VID6), PSI# and DPRSTP#
IIL
Logic input is low
-1
0
-
µA
IIH
Logic input is high at 1V
-
0.45
1
µA
53
60
68
µA
1.165
1.18
1.205
V
-
5
9
Ω
2.9
3.1
-
V
-
0.18
0.4
V
THERMAL MONITOR
NTC Source Current
NTC = 1.3 V
Over-Temperature Threshold
V(NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
CLK_EN# High Output Voltage
VOH
3V3 = 3.3V, I = -4mA
CLK_EN# Low Output Voltage
VOL
ICLK_EN# = 4mA
CLK_EN# OUTPUT LEVELS
5
FN9199.2
May 15, 2006
ISL6262
ISL6262 Gate Driver Timing Diagram
PWM
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tPDHL
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Functional Pin Description
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
1
36 BOOT1
PSI#
2
35 UGATE1
PGD_IN
3
34 PHASE1
RBIAS
4
33 PGND1
VR_TT#
5
32 LGATE1
NTC
6
SOFT
7
OCSET
8
29 PGND2
VW
9
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FB2 12
18
19
VSEN
RTN
DROOP
DFB
VO
VSUM
20
21
22
23
24
ISEN1
17
ISEN2
16
VDD
15
GND
14
VIN
13
VDIFF
25 NC
PGOOD - Power good open-drain output. Will be pulled up
externally by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
RBIAS - 147K resistor to VSS sets internal current
reference.
PSI# - Low load current indicator input. When asserted low,
indicates a reduced load-current condition, and product goes
into single phase operation.
VR_TT# - Thermal overload output indicator with open-drain
output. Over temperature pull-down resistance is 10Ω.
PGD_IN - Digital Input. When asserted high, indicates
VCCP and VCC_MCH voltages are within regulation.
6
NTC - Thermistor input to VRTT# circuit and a 60µA current
source is connected internally to this pin.
FN9199.2
May 15, 2006
ISL6262
SOFT - A capacitor from this pin to GND pin sets the
maximum slew rate of the output voltage. The SOFT pin is
the non-inverting input of the error amplifier.
OCSET - Overcurrent set input. A resistor from this pin to
VO sets DROOP voltage limit for OC trip. A 10µA current
source is connected internally to this pin.
VW - A resistor from this pin to COMP programs the
switching frequency (exa. 4.42kΩ ≅ 300kHz).
COMP - This pin is the output of the error amplifier.
FB - This pin is the inverting input of error amplifier.
FB2 - There is a switch between FB2 pin and the FB pin.
The switch is closed in single-phase operation and is
opened in two phase operation. The components connecting
to FB2 is to adjust the compensation in single phase
operation to achieve optimum performance.
VDIFF - This pin is the output of the differential amplifier.
VSEN - Remote core voltage sense input.
RTN - Remote core voltage sense return.
DROOP - Output of the droop amplifier. The voltage level on
this pin is the sum of Vo and the programmed droop voltage
by the external resistors.
DFB - Inverting input to droop amplifier.
VO - An input to the IC that reports the local output voltage.
VSUM - This pin is connected to the summation junction of
channel current sensing.
LGATE1 - Lower-side MOSFET gate signal for phase 1.
PGND1 - The return path of the lower gate driver for
phase 1.
PHASE1 - The phase node of phase 1. This pin should
connect to the source of upper MOSFET.
UGATE1 - Upper MOSFET gate signal for phase 1.
BOOT1 - This pin is the upper gate driver supply voltage for
phase 1. An internal boot strap diode is connected to the
PVCC pin.
VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with
VID0 is the least significant bit (LSB) and VID6 is the most
significant bit (MSB).
VR_ON - Digital input enable. A high level logic signal on
this pin enables the regulator.
DPRSLPVR - Deeper sleep enable signal. A high level logic
indicates the micro-processor is in Deeper Sleep Mode and
also indicates a slow C4 entry or exit rate with 41µA
discharging or charging the SOFT cap.
DPRSTP# - Deeper sleep slow wake up signal. A low level
logic signal on this pin indicates the micro-processor is in
deeper sleep mode.
CLK_EN# - Digital output for system PLL clock. Goes active
10µs after PGD_IN is active and Vcore is within 10% of Boot
voltage.
3V3 - 3.3V supply voltage for CLK_EN#.
VIN - Battery supply voltage. It is used for input voltage
feedforward to improve the input line transient performance.
VSS - Signal ground. Connect to local controller ground.
VDD - 5V control power supply.
ISEN2 - Individual current sharing sensing for channel 2.
ISEN1 - Individual current sharing sensing for channel 1.
N/C - Not connected. Grounding this pin to signal ground in
the practical layout.
BOOT2 - This pin is the upper gate driver supply voltage for
phase 2. An internal boot strap diode is connected to the
PVCC pin.
UGATE2 - Upper MOSFET gate signal for phase 2.
PHASE2 - The phase node of phase 2. This pin should
connect to the source of upper MOSFET.
PGND2 - The return path of the lower gate driver for
phase 2.
LGATE2 - Lower-side MOSFET gate signal for phase 2.
PVCC - 5V power supply for gate drivers.
7
FN9199.2
May 15, 2006
ISL6262
PGND2
LGATE2
PHASE2
UGATE2
BOOT2
PGND1
LGATE1
PHASE1
UGATE1
BOOT1
VR_TT#
NTC
Functional Block Diagram
6µA
54µA
PVCC
PVCC
+
PVCC
PVCC
VDD
PVCC
1.18V
VIN
PVCC
1.2V
DRIVER
LOGIC
VIN
DRIVER
LOGIC
ULTRASONIC
TIMER
FLT
FLT
ISEN2
CURRENT
BALANCE
ISEN1
VSOFT
I_BALF
VIN
GND
VSOFT
VIN
MODULATOR
MODULATOR
OC
OC
CH1
CH2
VW
3V3
PGOOD
CLK_EN#
Vw
PGOOD
MONITOR
AND LOGIC
CH1
CH2
COMP
Vw
PHASE
SEQUENCER
PHASE
CONTROL
LOGIC
PGOOD
FLT
FAULT AND
PGOOD
LOGIC
SINGLE
PHASE
VO
E/A
VIN
FB2
-
+
PGD_IN
FB
SINGLE
PHASE
SOFT
VSOFT
OC
VDIFF
VO
SOFT
MODE CHANGE
REQUEST
+
+
+
+
+
-
-
0.5
RTN
VO
DROOP
VSEN
VO
DROOP
-
DFB
VSUM
+
10µA
DPRSTP#
DPRSLPVR
PSI#
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
1
MODE
CONTROL
DAC
-
OCSET
DACOUT
RBIAS
SINGLE
PHASE
FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6262
8
FN9199.2
May 15, 2006
ISL6262
Typical Performance Curves 300kHz, DCR Sense, 2xIRF7821/2xIRF7832 Per Phase
100
1.16
VIN = 8.0V
VIN = 8.0V
1.14
80
VIN = 12.6V
70
VIN = 19.0V
1.12
60
VOUT (V)
EFFICIENCY (%)
90
50
40
30
VIN = 12.6V
1.10
VIN = 19.0V
1.08
1.06
20
1.04
10
0
0
5
10
15
20
25
30
35
40
45
1.02
50
0
10
20
IOUT (A)
40
50
FIGURE 2. ACTIVE MODE EFFICIENCY, 2 PHASE, CCM,
PSI# = HIGH, VID = 1.15V
FIGURE 3. ACTIVE MODE LOAD LINE, 2 PHASE, CCM,
PSI# = HIGH, VID = 1.15V
100
1.16
VIN = 8.0V
90
1.15
80
VIN = 12.6V
70
1.14
VIN = 19.0V
60
VOUT (V)
EFFICIENCY (%)
30
IOUT (A)
50
40
1.13
VIN = 8.0V
VIN = 12.6V
1.12
30
VIN = 19.0V
20
1.11
10
0
0
2
4
6
8
10
12
14
16
18
1.10
20
0
2
4
6
8
IOUT (A)
FIGURE 4. ACTIVE MODE EFFICIENCY, 1 PHASE, CCM,
PSI# = LOW, VID = 1.15V
12
14
16
18
20
FIGURE 5. ACTIVE MODE LOAD LINE, 1 PHASE, CCM,
PSI# = LOW, VID = 1.15V
100
0.765
0.76
90
VIN = 8.0V
0.755
80
VIN = 19.0V
VOUT (V)
EFFICIENCY (%)
10
IOUT (A)
VIN = 12.6V
70
0.75
VIN = 8.0V
VIN = 19.0V
0.745
60
0.74
50
0.1
1
IOUT (A)
FIGURE 6. DEEPER SLEEP MODE EFFICIENCY, 1 PHASE,
DCM MODE, VID = 0.7625V
9
10
0.735
VIN = 12.6V
0
2
4
6
8
10
IOUT (A)
FIGURE 7. DEEPER SLEEP MODE LOAD LINE, 1 PHASE,
DCM MODE, VID = 0.7625V
FN9199.2
May 15, 2006
ISL6262
Typical Performance Curves
0.36µH Filter Inductor and 4 x 330µF Output SP Caps
VOUT
VSOFT
VOUT
VR_ON
VSOFT
VR_ON
CSOFT = 15nF
FIGURE 8. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1V, ILOAD = 10A
CSOFT = 15nF
FIGURE 9. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1.4375V, ILOAD = 10A
VOUT
VOUT @ 1.4375V
IL1, IL2
VOUT @ 1.2V
PGD_IN
IIN
IMVP-6_PWRGD
CLK_EN#
FIGURE 10. SOFT-START WAVEFORM SHOWING CLK_EN#
AND IMVP-6 PGOOD
LINE TRANSIENT
IIN
VOUT
FIGURE 11. INRUSH CURRENT AT START-UP, VIN = 8V,
VID = 1.4375V, ILOAD = 10A
VIN
FIGURE 12. 8V-20V INPUT LINE TRANSIENT RESPONSE,
CIN = 240µF
10
FIGURE 13. 2 PHASE CURRENT BALANCE, FULL LOAD = 50A
FN9199.2
May 15, 2006
ISL6262
Typical Performance Curves
0.36µH Filter Inductor and 4 x 330µF Output SP Caps (Continued)
VID3
VOUT
VOUT
DYNAMIC VID
ACTIVE MODE
LOAD TRANSIENT
PHASE1,
PHASE2
FIGURE 14. LOAD STEP-UP RESPONSE VIA CPU SOCKET
MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE
CCM
FIGURE 15. VID3 CHANGE OF 010X000 FROM 1.V TO 1.1V AT
DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
VID3
VOUT
VOUT
DYNAMIC VID
ACTIVE MODE
LOAD TRANSIENT
FIGURE 16. LOAD DUMP RESPONSE VIA CPU SOCKET
MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE
CCM
DROP PHASE IN
ACTIVE MODE
PSI#
PHASE1,
PHASE2
FIGURE 17. VID3 CHANGE OF 010X000 FROM 1.1V TO 1V AT
DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
PSI#
ADD PHASE IN
ACTIVE MODE
VCORE
VCORE
PHASE1
PHASE1
PHASE2
FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH
VID LSB CHANGE, AT DPRSLPVR = 0,
DPRSTP# = 1, ILOAD = 10A
11
PHASE2
FIGURE 19. 1-CCM TO 2-CCM UPON PSI# DEASSERTION
WITH VID LSB CHANGE AT DPRSLPVR = 0,
DPRSTP# = 1
FN9199.2
May 15, 2006
ISL6262
Typical Performance Curves
0.36µH Filter Inductor and 4 x 330µF Output SP Caps (Continued)
DPRSLPVR
DPRSLPVR
C4 EXIT/PHASE ADD
VOUT
C4 ENTRY WITH
PSI# ASSERTION
VOUT
PHASE1
PHASE1
PHASE2
FIGURE 20. C4 ENTER WITH VID CHANGE 0011X00 FROM
1.2V TO 1.15V, ILOAD = 2A, TRANSITION OF
2-CCM TO 1-DCM, PSI# TOGGLE FROM 1 TO 0
WITH DPRSLPVR FROM 0 TO 1
PHASE2
FIGURE 21. VID3 CHANGE OF 010X000 FROM 1.V TO 1.1V AT
DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
DPRSLPVR
DPRSLPVR
FAST BREAK C4 EXIT
VOUT
C4 ENTRY WITH PSI# = 0
VOUT
PHASE1
PHASE1
PHASE2
FIGURE 22. FAST BREAK C4 EXIT AT LOAD = 0.1A
PHASE2
FIGURE 23. C4 ENTRY WITH VID CHANGE OF 011X011 FROM
0.8625V TO 0.7625V, ILOAD = 3A, 1-CCM TO
1-DCM
VOUT
PHASE1
PGOOD
PGOOD
VOUT
IL1, IL2
FIGURE 24. OVERCURRENT PROTECTION
12
FIGURE 25. 1.7V OVERVOLTAGE PROTECTION SHOWS
OUTPUT VOLTAGE PULLED LOW TO 0.9V AND
PWM THREE-STATE
FN9199.2
May 15, 2006
ISL6262
Simplified Application Circuit for DCR Current Sensing
V +5
VIN
V +3.3
R12
3V3
VDD PVCC VIN
VIN
RBIAS
NTC
C7
R13
VR_TT#
VR_TT#
C8
VID<0:6>
UGATE1
BOOT1
SOFT
LO
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
ISL6262
DPRSLPVR
LGATE1
ISEN2
DPRSLPVR
PSI#
VO
VSUM
ISEN1
PGD_IN
MCHOK
VO'
R8
PGND2
PSI#
CL
RL
CO
CLK_ENABLE#
CLK_EN#
VIN
VR_ON
VR_ON
C8
PGOOD
IMVP-6_PWRGD
VSEN
REMOTE
SENSE
UGATE2
RTN
C5
VDIFF
R3
PHASE2
C3
R7
R11
RL
LGATE2
FB2
FB
C1
LO
BOOT2
R2
R9
PGND2
R1
ISEN1
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 26. ISL6262 BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
13
FN9199.2
May 15, 2006
ISL6262
Simplified Application Circuit for Resistive Current Sensing
V +5
VIN
V +3.3
R11
3V3
VDD PVCC VIN
VIN
RBIAS
NTC
C7
R12
VR_TT#
VR_TT#
C9
VID<0:6>
UGATE1
BOOT1
SOFT
L
RS
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
ISL6262
DPRSLPVR
LGATE1
ISEN2
DPRSLPVR
PSI#
VO
VSUM
ISEN1
PGD_IN
MCHOK
VO'
R8
PGND2
PSI#
CL
RL
CO
CLK_ENABLE#
CLK_EN#
VIN
VR_ON
VR_ON
C8
PGOOD
IMVP-6_PWRGD
VSEN
REMOTE
SENSE
UGATE2
RTN
PHASE2
C3
R11
R7
RL
LGATE2
FB2
FB
C1
RS
C5
VDIFF
R3
L
BOOT2
R2
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
CHF
R6
R4
C4
VO'
FIGURE 27. ISL6262 BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
14
FN9199.2
May 15, 2006
ISL6262
Theory of Operation
VDD
The ISL6262 is a two-phase regulator implementing Intel®
IMVP-6 protocol and includes embedded gate drivers for
reduced system cost and board area. The regulator provides
optimum steady-state and transient performance for
microprocessor core applications up to 50A. System
efficiency is enhanced by idling one phase at low-current
and implementing automatic DCM-mode operation.
The heart of the ISL6262 is R3 Technology™, Intersil’s
Robust Ripple Regulator modulator. The R3 modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. The ISL6262 modulator internally synthesizes
an analog of the inductor ripple current and uses hysteretic
comparators on those signals to establish PWM pulse
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL6262 to achieve lower
output ripple and lower phase jitter than either conventional
hysteretic or fixed frequency PWM controllers. Unlike
conventional hysteretic converters, the ISL6262 has an error
amplifier that allows the controller to maintain a 0.5% voltage
regulation accuracy throughout the VID range from 0.75V to
1.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
10mV/µs
VR_ON
2mV/µs
100µs
VBOOT
VID COMMANDED
VOLTAGE
SOFT & VO
20µs
PGD_IN
CLK_EN#
6.8ms
IMVP-6 PGOOD
FIGURE 28. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
PGD_IN Latch
It should be noted that PGD_IN going low will cause the
converter to latch off. This state will be cleared when VR_ON
is toggled. This feature allows the converter to respond to
other system voltage outages immediately.
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs per Table 1. The entire VID
table is presented in the intel IMVP-6 specification. The
ISL6262 will control the no-load output voltage to an
accuracy of ±0.5% over the range of 0.75V to 1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6
SPECIFICATION
VID6
VID5
VID4
VID3
VID2
VID1
Start-Up Timing
0
0
0
0
0
0
0
1.5000
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
100µs later, SOFT and VOUT begin ramping to the boot
voltage of 1.2V. At start-up, the regulator always operates in
a 2-phase CCM mode, regardless of control signal assertion
levels. During this internal, the SOFT cap is charged by
41µA current source. If the SOFT capacitor is selected to be
20nF, the SOFT ramp will be at 2mV/s for a soft-start time of
600µs. Once VOUT is within 10% of the boot voltage
and PGD_IN is HIGH for six PWM cycles (20µs for
frequency = 300kHz), then CLK_EN# is pulled LOW and the
SOFT cap is charged/discharged by approximate 200µA.
Therefore, VOUT slews at +10mV/s to the voltage set by the
VID pins. Approximately 7ms later, PGOOD is asserted
HIGH. Typical start-up timing is shown in Figure 28.
0
0
0
0
0
0
1
1.4875
0
0
0
0
1
0
1
1.4375
0
0
1
0
0
0
1
1.2875
0
0
1
1
1
0
0
1.15
0
1
1
0
1
0
1
0.8375
0
1
1
1
0
1
1
0.7625
1
1
0
0
0
0
0
0.3000
1
1
1
1
1
1
1
0.0000
15
VID0 VOUT (V)
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the microprocessor die. The
inputs to the amplifier are the VSEN and RTN pins.
As the load current increases from zero, the output voltage
will droop from the VID table value by an amount
proportional to current to achieve the IMVP-6 load line. The
ISL6262 provides for current to be measured using either
resistors in series with the channel inductors as shown in the
application circuit of Figure 27, or using the intrinsic series
FN9199.2
May 15, 2006
ISL6262
resistance of the inductors as shown in the application circuit
of Figure 26. In both cases signals representing the inductor
currents are summed at VSUM, which is the non-inverting
input to the DROOP amplifier shown in the block diagram of
Figure 1. The voltage at the DROOP pin minus the output
voltage, VO´, is a high-bandwidth analog of the total inductor
current. This voltage is used as an input to a differential
amplifier to achieve the IMVP-6 load line, and also as the
input to the overcurrent protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the loadline accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to
cause the voltages presented at the ISEN pins to be equal.
The ISL6262 controller can be configured for two-channel
operation, with the channels operating 180 degrees apart.
The channel PWM frequency is determined by the value of
RFSET connected to pin VW as shown in Figure 26 and
Figure 27. Input and output ripple frequencies will be the
channel PWM frequency multiplied by the number of active
channels.
High Efficiency Operation Mode
The ISL6262 has several operating modes to optimize
efficiency. The controller's operational modes are designed
to work in conjunction with the Intel IMVP-6 control signals to
maintain the optimal system configuration for all IMVP-6
conditions. These operating modes are established by the
IMVP-6 control signal inputs such as PSI#, DPRSLPVR, and
DPRSTP# as shown in Table 2. At high current levels, the
system will operate with both phases fully active, responding
rapidly to transients and deliver the maximum power to the
load. At reduced load current levels, one of the phases may
be idled. This configuration will minimize switching losses,
while still maintaining transient response capability. At the
lowest current levels, the controller automatically configures
the system to operate in single-phase automatic-DCM
mode, thus achieving the highest possible efficiency. In this
mode of operation, the lower FET will be configured to
automatically detect and prevent discharge current flowing
from the output capacitor through the inductors, and the
switching frequency will be proportionately reduced, thus
greatly reducing both conduction and switching losses.
Smooth mode transitions are facilitated by the R3
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms which robustly
maintain voltage-regulation for all control signal input
sequences and durations.
Mode-transition sequences will often occur in concert with
VID changes; therefore the timing of the mode transitions of
ISL6262 has been carefully designed to work in concert with
VID changes. For example, transitions into single-phase
mode will be delayed until the VID induced voltage ramp is
complete, to allow the associated output capacitor charging
current is shared by both inductor paths. While in singlephase automatic-DCM mode, VID changes will initiate an
immediate return to two-phase CCM mode. This ensures
that both inductor paths share the output capacitor charging
current and are fully active for the subsequent load current
increases.
The controller contains internal counters which prevent
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling. Signals of less than 7
switching periods do not result in implementation of
automatic-DCM mode.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6262
Intel IMVP-6
COMPLIANT LOGIC
OTHER LOGIC
COMMANDS
DPRSLPVR
DPRSTP#
PSI#
0
1
1
2-phase CCM
active mode
0
1
0
1-phase CCM
active mode
1
0
1
1-phase diode emulation
deeper sleep mode
1
0
0
1-phase diode emulation
deeper sleep mode
0
0
1
2-phase CCM
0
0
0
1-phase CCM
1
1
1
2-phase CCM
1
1
0
1-phase CCM
16
PHASE OPERATION MODES
EXPECTED CPU MODE
FN9199.2
May 15, 2006
ISL6262
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into automatic-DCM or forcedCCM mode, the timing is carefully adjusted to eliminate
output voltage excursions. When a phase is added, the
current balance between phases is quickly restored.
While PSI# is high, both phases are switching. If PSI# is
asserted low and either DPRSTP# or DPRSLPVR are not
asserted, the controller will transition to CCM operation with
only phase 1 switching, and both FET's of phase 2 will be off.
The controller will thus eliminate switching losses associated
with the unneeded channel.
VOUT & VSOFT
10mV/µs
-2.5mV/µs
2.5mV/µs
DPRSLPVR
and the ISL6262 will turn-off the lower FET of channel 1
whenever the channel 1 current decays to zero. As load is
further reduced, the phase 1 channel switching frequency
will decrease, thus maintaining high efficiency.
Dynamic Operation
Refer to Figure 29, the ISL6262 responds to changes in VID
command voltage by slewing to new voltages with a dV/dt
set by the SOFT capacitor and by the state of DPRSLPVR.
With CSOFT = 15nF and DPRSLPVR HIGH, the output
voltage will move at ±2.8mV/s for large changes in voltage.
For DPRSLPVR LOW, the large signal dV/dt will be
±13mV/s. As the output voltage approaches the VID
command value, the dV/dt moderates to prevent overshoot.
Keeping DPRSLPVR HIGH for voltage transitions into and
out of Deeper Sleep will result in low dV/dt output voltage
changes with resulting minimized audio noise. For fastest
recovery from Deeper Sleep to Active mode, holding
DPRSLPVR LOW will result in maximum dV/dt. Therefore,
the ISL6262 is IMVP-6 compliant for DPRSTP# and
DPRSLPVR logic.
Intersil's R3 Technology™ has intrinsic voltage feedforward.
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6262 will transiently raise the
switching frequency so that response time is decreased and
current is shared by two channels.
VID #
FIGURE 29. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
When PSI#, DPRSTP#, and DPRSLPVR are all asserted,
the controller will transition to single-phase DCM mode. In
this mode, both FET's associated with phase 2 will be off,
Protection
The ISL6262 provides overcurrent, overvoltage, undervoltage protection and over-temperature protection as
shown in Table 3.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6262
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurrent fault
<2µs
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Low-side FET on until Vcore
<0.85V, then PWM three-state,
PGOOD latched low (OV-1.7V
always)
VDD toggle
Overvoltage fault (1.7V)
Immediately
Overvoltage fault (+200mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Undervoltage fault
(-300mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Unbalance fault
(7.5mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
VR_TT# goes low
N/A
Over-temperature
fault (NTC <1.18V)
Immediately
17
FN9199.2
May 15, 2006
ISL6262
Overcurrent protection is tied to the voltage droop which is
determined by the resistors selected as described in the
“Component Selection and Application” section. After the
load-line is set, the OCSET resistor can be selected to
detect overcurrent at any level of droop voltage. An
overcurrent fault will occur when the load current exceeds
the overcurrent setpoint voltage while the regulator is in a
2-phase mode. While the regulator is in a 1-phase mode of
operation, the overcurrent setpoint is automatically reduced
by half. For overcurrents less than twice the OCSET level,
the over-load condition must exist for 120µs in order to trip
the OC fault latch. This is shown in Figure 24.
For over-loads exceeding twice the set level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection due to hard shorts.
In addition, excessive phase unbalance, for example, due to
gate driver failure, will be detected in two-phase operation
and the controller will be shut-down after one millisecond's
detection of the excessive phase current unbalance. The
phase unbalance is detected by the voltage on the ISEN
pins if the difference is greater than 7.5mV.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after one millisecond in that
condition. The PWM outputs will turn off and PGOOD will go
low. Note that most practical core regulators will have the
overcurrent set to trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
For output voltage exceeding the set value by +200mV for
one millisecond, a fault is declared. All of the above faults
have the same action taken: PGOOD is latched low and the
upper and lower power FETs are turned off so that inductor
current will decay through the FET body diodes. This
condition can be reset by bringing VR_ON low or by bringing
VDD below 4V. When these inputs are returned to their high
operating levels, a soft-start will occur.
threshold, the VR_TT# pin is pulled low indicating the need
for thermal throttling to the system oversight processor. No
other action is taken within the ISL6262 in response to NTC
pin voltage.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6262 uses 2 slew rates for various modes of
operation. The first is a slow slew rate, used to reduce inrush
current during start-up. It is also used to reduce audible
noise when entering or exiting Deeper Sleep Mode. A faster
slew rate is used to exit out of Deeper Sleep and to enhance
system performance by achieving active mode regulation
more quickly. Note that the SOFT cap current is bidirectional.
The current is flowing into the SOFT capacitor when the
output voltage is commanded to rise, and out of the SOFT
capacitor when the output voltage is commanded to fall.
Refer to Figure 30. The two slew rates are determined by
commanding one of two current sources onto the SOFT pin.
As can be seen in Figure 30, the SOFT pin has a
capacitance to ground. Also, the SOFT pin is the input to the
error amplifier and is, therefore, the commanded system
voltage. Depending on the state of the system, i.e. Start-Up
or Active mode, and the state of the DPRSLPVR pin, one of
the two currents shown in Figure 30 will be used to charge or
discharge this capacitor, thereby controlling the slew rate of
the commanded voltage. These currents can be found under
the SOFT-START CURRENT section of the Electrical
Specification Table.
ISL6262
ISS
I2
ERROR
AMPLIFIER
+
Refer to Figure 25, the second level of overvoltage
protection behaves differently. If the output exceeds 1.7V, an
OV fault is immediately declared, PGOOD is latched low and
the low-side FETs are turned on. The low-side FETs will
remain on until the output voltage is pulled down below
about 0.85V at which time all FETs are turned off. If the
output again rises above 1.7V, the protection process is
repeated. This offers the maximum amount of protection
against a shorted high-side FET while preventing output
ringing below ground. The 1.7V OV is not reset with VR_ON,
but requires that VDD be lowered to reset. The 1.7V OV
detector is active at all times that the controller is enabled
including after one of the other faults occurs so that the
processor is protected against high-side FET leakage while
the FETs are commanded off.
The first current, labelled ISS, is given in the Specification
Table as 41µA. This current is used during soft-start. The
second current, I2 sums with ISS to get the larger of the two
currents, labeled IGV in the Electrical Specification Table.
This total current is typically 200µA with a minimum of
175µA.
The ISL6262 has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.18V over-temperature
The IMVP-6 specification reveals the critical timing
associated with regulating the output voltage. The symbol,
18
SOFT
+
CSOFT
VREF
FIGURE 30. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
FN9199.2
May 15, 2006
ISL6262
SLEWRATE, as given in the IMVP-6 specification will
determine the choice of the SOFT capacitor, CSOFT, by the
following equation:
I GV
C SOFT = -----------------------------------SLEWRATE
(EQ. 1)
Using a SLEWRATE of 10mV/µs, and the typical IGV value,
given in the Electrical Specification Table of 200µA, CSOFT
is
C SOFT = 200μA ⁄ ( 10mV ⁄ 1μs )
(EQ. 2)
A choice of 0.015µF would guarantee a SLEWRATE of
10mV/µs is met for minimum IGV value, given in the
Electrical Specification Table. This choice of CSOFT will then
control the Start-Up slewrate as well. One should expect the
output voltage to slew to the Boot value of 1.2V at a rate
given by the following equation:
I SS
41μA
dV
------- = ------------------= ----------------------- = 2.8mV ⁄ μs
0.015μF
C SOFT
dt
(EQ. 3)
Selecting RBIAS
To properly bias the ISL6262, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10µA current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-Up Operation - CLK_EN# and PGOOD
The ISL6262 provides a 3.3V logic output pin for CLK_EN#.
The 3V3 pin allows for a system 3.3V source to be
connected to separated circuitry inside the ISL6262, solely
devoted to the CLK_EN# function. The output is a 3.3V
CMOS signal with 4mA sourcing and sinking capability. This
implementation removes the need for an external pull-up
resistor on this pin, and due to the normal level of this signal
being a low, removes the leakage path from the 3.3V supply
to ground through the pull-up resistor. This reduces 3.3V
supply current, that would occur under normal operation with
a pull-up resistor, and prolongs battery life. The 3.3V supply
should be decoupled to digital ground, not to analog ground
for noise immunity.
IMVP-6_PWRGD signal. This timer allows IMVP-6_PWRGD
to go high approximately 6.8ms after CLK_EN# goes low.
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6262 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are Vcc_sense and
Vss_sense respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode RC filters to analog ground on VSEN and RTN as
shown in Figure 31. The filter resistors should be 10Ω so that
they do not interact with the 50kΩ input resistance of the
differential amplifier. The filter resistor may be inserted
between Vcc_sense and VSEN pin. Another option is to
place to the filter resistor between Vcc_sense and VSEN pin
and between Vss_sense and RTN pin. Whether to need
these RC filter really depends on the actual board layout and
noise environment.
Due to the fact that the voltage feedback to the switching
regulator is sensed at the processor die, there exists the
potential of an overvoltage due to an open circuited
feedback signal, should the regulator be operated without
the processor installed. Due to this fact, we recommend the
use of the Ropn1 and Ropn2 connected to Vout and ground
as shown in Figure 31. These resistors will provide voltage
feedback in the event that the system is powered up without
a processor installed. These resistors may typically range
from 20 to 100Ω.
As mentioned in the “Theory of Operation” section of this
datasheet, CLK_EN# is logic level high at start-up until 20µs
after the system Vccp and Vcc_mch supplies are within
regulation, and the Vcc-core is in regulation at the Boot level.
Approximately 20µs after these voltages are within
regulation, as indicated by PGD_IN going high, CLK_EN#
goes low, triggering an internal timer for the
19
FN9199.2
May 15, 2006
ISL6262
ISEN1
ISEN2
ISEN2
ISEN1
10µA
ROCSET
OCSET
VO'
IPHASE1
+
OC
VSUM
+
DROOP
INTERNAL TO
ISL6262
+
-
+
RNTC
VSEN
DCR
+
Vdcr2
VO'
VDIFF
RL2
VSUM
VOUT
RO2
CBULK
CL2
ISEN2
Rdrp1
RO1
VO'
L2
RS
+
1 RTN
ISEN1
RPAR
Cn
C L1
RL1
IPHASE2
Rdrp2
Vdcr1
DCR
VSUM
RSERIES
DROOP
+
1 -
+
RS
VSUM
DFB
L1
VO'
VO'
82nF
10
0.018µF
Ropn1
ESR
TO VOUT
0.018µF
VCC_SENSE
VSS_SENSE
ROPN2
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
FIGURE 31. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM
architecture. The switching frequency can increase during
the application of a load to improve transient performance.
It also varies slightly due changes in input and output voltage
and output current, but this variation is normally less than
10% in continuous conduction mode.
Refer to Figure 26, the resistor connected between the VW
and COMP pins of the ISL6262 adjusts the switching
window, and therefore adjusts the switching frequency. The
RFSET resistor that sets up the switching frequency of the
converter operating in CCM can be determined using the
following relationship, where RFSET is in kΩ and the
switching period is in µs. Place a 47pF capacitor in parallel
with the frequency set resistor for better noise immunity.
R FSET ( kΩ ) ≅ ( period ( μs ) – 0.5 ) • 1.56
which senses the voltage change across an externally
placed negative temperature coefficient (NTC) thermistor.
Proper selection and placement of the NTC thermistor
allows for detection of a designated temperature rise by the
system.
Figure 32 shows the thermal throttling feature with
hysteresis. At low temperature, SW1 is on and SW2
connects to the 1.18V side. The total current going into NTC
pin is 60µA. The voltage on NTC pin is higher than threshold
voltage of 1.18V and the comparator output is low. VR_TT#
is pulling up high by the external resistor.
54µA
(EQ. 4)
6µA
VR_TT#
SW1
NTC
In discontinuous conduction mode (DCM), the ISL6262 runs
in period stretching mode. The switching frequency is
dependent on the load current level. In general, the lighter
load, the slower switching frequency. Therefore, the
switching loss is much reduced for the light load operation,
which is important for conserving the battery power in the
portable application.
+
VNTC
-
+
RNTC
Rs
1.20V
SW2
1.18V
INTERNAL TO
ISL6262
Voltage Regulator Thermal Throttling
lntel® IMVP-6 technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the
voltage regulator. The ISL6262 features a thermal monitor
20
FIGURE 32. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE IN ISL6262
FN9199.2
May 15, 2006
ISL6262
When temperature increases, the NTC resistor value on
NTC pin decreases. Thus, the voltage on NTC pin
decreases to a level lower than 1.18V. The comparator
output changes polarity and turns SW1 off and connects
SW2 to 1.20V. This pulls VR_TT# low and sends the signal
to start thermal throttle. There is a 6µA current reduction on
NTC pin and 20mV voltage increase on threshold voltage of
the comparator in this state. The VR_TT# signal will be used
to change the CPU operation and decrease the power
consumption. When the temperature goes down, the NTC
thermistor voltage will eventually go up. The NTC pin voltage
increases to 1.20V, the comparator output will then be able
to flip back. Such a temperature hysteresis feature of
VR_TT# is illustrated in Figure 33. T1 represents the higher
temperature point at which the VR_TT# goes from low to
high due to the system temperature rise. T2 represents the
lower temperature point at which the VR_TT# goes high
from low because the system temperature decreases to the
normal level.
VR_TT#
1
b • ⎛ -----------------------⎞
⎝ T + 273⎠
o
2.55kΩ • e
R NTCTo = -----------------------------------------------------------------------------e
1
b • ⎛ -----------------------⎞
⎝ T + 273⎠
2
–e
1
b • ⎛ -----------------------⎞
⎝ T + 273⎠
1
(EQ. 9)
For some cases, the constant b is not accurate enough to
approximate the NTC resistor value, the manufacturer
provides the resistor ratio information at different
temperature. The nominal NTC resistor value may be
expressed in another way as follows:
2.55kΩ
R NTCTo = ----------------------------------------------------------------------Λ
– Λ
R NTC – T
R NTC – T
2
(EQ. 10)
1
Λ
where R NTC – T is the normalized NTC resistance to its
nominal value. Most datasheet of the NTC thermistor gives
the normalized resistor value based on its value at 25°C.
Once the NTC thermistor resistor is determined, the series
resistor can be derived by:
Logic_1
1.18V
R S = ---------------- – R NTC ( T1 ) = 19.67kΩ – R NTC_T
60μA
1
(EQ. 11)
Once RNTCTo and Rs is designed, the actual NTC resistance
at T2 and the actual T2 temperature can be found in:
Logic_0
T2
T1
T (°C)
FIGURE 33. TEMPERATURE HYSTERESIS OF VR_TT#
Usually, the NTC thermistor's resistance can be
approximated by the following formula:
R NTC ( T ) = R NTCTo • e
Using Equation 5 into Equation 8, the required nominal NTC
resistor value can be obtained by:
1
1
b • ⎛ -------------------- – -----------------------⎞
⎝ T + 273 To + 273⎠
(EQ. 5)
T is the temperature of the NTC thermistor and b is a
parameter constant depending on the thermistor material.
To is the reference temperature in which the approximation
is derived. Most common temperature for To is 25°C. For
example, there are commercial NTC thermistor products
with b = 2750k, b = 2600k, b = 4500k or b = 4250k.
From the operation principle of the VR_TT# circuit
explained, the NTC resistor satisfies the following equation
group.
1.18V
R NTC ( T 1 ) + R S = ---------------- = 19.67kΩ
60μA
(EQ. 6)
1.2V
R NTC ( T 2 ) + R S = --------------- = 22.22kΩ
54μA
(EQ. 7)
R NTC_T
2
= 2.55kΩ + R NTC_T
1
1
T 2_actual = ----------------------------------------------------------------------------------- – 273
R NTC_T
⎞
1 ⎛
--- ln ⎜ -------------------------2⎟ + 1 ⁄ ( 273 + To )
b ⎝ R NTCTo ⎠
(EQ. 12)
(EQ. 13)
One example of using Equations 9, 10 and 11 to design a
thermal throttling circuit with the temperature hysteresis
100°C to 105°C is illustrated as follows. Since T1 = 105°C
and T2 = 100°C, if we use a Panasonic NTC with B = 4700,
the Equation 9 gives the required NTC nominal resistance as
R NTC_To = 396kΩ
In fact, the datasheet gives the resistor ratio value at 100°C
to 105°C, which is 0.03956 and 0.03322 respectively. The b
value 4700K in Panasonic datasheet only covers to 85°C.
Therefore, using Equation 10 is more accurate for 100°C
design, the required NTC nominal resistance at 25°C is
402kΩ. The closest NTC resistor value from manufacturer is
470kΩ. So the series resistance is given by Equation 11 as
follows,
R S = 19.67kΩ – R NTC_105°C = 19.67kΩ – 15.65kΩ = 4.067kΩ
From Equation 6 and Equation 7, the following can be
derived,
Furthermore, the NTC resistance at T2 is given by Equation 12.
R NTC ( T 2 ) – R NTC ( T 1 ) = 2.55kΩ
From the NTC datasheet, it can be concluded that the actual
temperature T2 is about 97°C. If using the Equation 13, T2 is
calculated to be 97.7°C. Check the NTC datasheet to decide
21
(EQ. 8)
R NTC_T2 = 2.55kΩ + R NTC_T1 = 18.16kΩ
FN9199.2
May 15, 2006
ISL6262
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 34.
whether Equation 9 or Equation 10 can accurately represent
the NTC resistor value at the designed temperature range.
Therefore, the NTC branch is designed to have a 470k NTC
and 4.02k resistor in series. The part number of the NTC
thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
thermistor should be placed in the spot which gives the best
indication of the temperature of voltage regulator circuit. The
actual hysteresis temperature is about 105°C and 97°C.
Figure 34 shows the simplified model of the droop circuitry.
Essentially one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by:
Static Mode of Operation - Static Droop Using DCR
Sensing
As previously mentioned, the ISL6262 has an internal
differential amplifier which provides for very accurate voltage
regulation at the die of the processor. The load line
regulation is also accurate for both two-phase and singlephase operation. The process of selecting the components
for the appropriate load line droop is explained here.
I OUT • DCR
V DCR_EQU = --------------------------------2
For the convenience of analysis, the NTC network
comprised of Rntc, Rseries and Rpar, given in Figure 31, is
labelled as a single resistor Rn in Figure 34.
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired load line droop
has several steps and is somewhat iterative.
The first step in droop load line compensation is to adjust
Rn, ROEQV and RSEQV such that sufficient droop voltage
exists even at light loads between the VSUM and VO' nodes.
As a rule of thumb we start with the voltage drop across the
Rn network, VN, to be 0.5-0.8 times VDCR_EQU. This ratio
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The two-phase solution using DCR sensing is shown in
Figure 31. There are two resistors connecting to the
terminals of inductor of each phase. These are labeled RS
and RO. These resistors are used to obtain the DC voltage
drop across each inductor. Each inductor will have a certain
level of DC current flowing through it, and this current when
multiplied by the DCR of the inductor creates a small DC
voltage drop across the inductor terminal. When this voltage
is summed with the other channels DC voltages, the total DC
load current can be derived.
The resultant NTC network resistor value is dependent on
the temperature and given by
( R series + R ntc ) • R par
R n ( T ) = -------------------------------------------------------------R series + R ntc + R par
OCSET
+
OC
VSUM
+
DROOP
-
INTERNAL TO
ISL6262
VDIFF
DCR
Vdcr EQV = I OUT × ------------2
DROOP
+
1 -
+
+
1 -
RTN VSEN
VO'
Cn
Rdrp1
+
VSUM
RS
RS EQV = -------2
DFB
Rdrp2
+
(EQ. 15)
For simplicity, the gain of Vn to the Vdcr_equ is defined by
G1, also dependent on the temperature of the NTC
thermistor.
RO is typically 1 to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
10µA
(EQ. 14)
VN
-
( Rntc + Rseries ) × Rpar
Rn = -------------------------------------------------------------------( Rntc + Rseries ) + Rpar
VO'
RO
RO EQV = --------2
FIGURE 34. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
22
FN9199.2
May 15, 2006
ISL6262
Δ
Rn ( T )
G 1 ( T ) = ------------------------------------------R n ( T ) + RS EQV
(EQ. 16)
DCR ( T ) = DCR 25°C • ( 1 + 0.00393*(T-25) )
(EQ. 17)
Therefore, the output of the droop amplifier divided by the
total load current can be expressed as follows.
DCR 25
R droop = G 1 ( T ) • ------------------- • ( 1 + 0.00393*(T-25) ) • k droopamp
2
(EQ. 18)
where Rdroop is the realized load line slope and 0.00393 is
the temperature coefficient of the copper. To achieve the
droop value independent from the temperature of the
inductor, it is equivalently expressed by the following.
G 1 ( T ) • ( 1 + 0.00393*(T-25) ) ≅ G 1t arg et
(EQ. 19)
The non-inverting droop amplifier circuit has the gain
Kdroopamp expressed as:
R drp2
k droopamp = 1 + ---------------R drp1
G1target is the desired gain of Vn over IOUT • DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described by:
G 1t arg et
G 1 ( T ) = ------------------------------------------------------( 1 + 0.00393*(T-25) )
(EQ. 20)
For the G1target = 0.76, the Rntc = 10kΩ with b = 4300,
Rseries = 2610kΩ, and Rpar = 11kΩ, RSEQV = 1825Ω
generates a desired G1, close to the feature specified in
Equation 20. The actual G1 at 25°C is 0.763. For different
G1 and NTC thermistor preference, the design file to
generate the proper value of Rntc, Rseries, Rpar, and
RSEQV is provided by Intersil.
Then, the individual resistors from each phase to the VSUM
node, labeled RS1 and RS2 in Figure 31, are then given by
the following equation.
Rs = 2 • RS EQV
(EQ. 21)
So, Rs = 3650Ω. Once we know the attenuation of the RS
and RN network, we can then determine the droop amplifier
gain required to achieve the load line. Setting Rdrp1 =
1k_1%, then Rdrp2 is can be found using equation
2 • R droop
Rdrp2 = ⎛ ----------------------------------------------- – 1⎞ • R drp1
⎝ DCR • G1 ( 25°C )
⎠
(EQ. 22)
Droop Impedance (Rdroop) = 0.0021 (V/A) as per the Intel
IMVP-6 specification, DCR = 0.0008Ω typical for a 0.36µH
inductor, Rdrp1 = 1kΩ and the attenuation gain (G1) = 0.77,
Rdrp2 is then given by
Note, we choose to ignore the RO resistors because they do
not add significant error.
These designed values in Rn network are very sensitive to
layout and coupling factor of the NTC to the inductor. As only
one NTC is required in this application, this NTC should be
placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should be go
directly to the inductor pads.
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
Rdrp2 to obtain the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 2.1mV/A load line should be adjusted by Rdrp2 based
on maximum current, not based on small current steps like
10A, as the droop gain might vary between each 10A steps.
Basically, if the max current is 40A, the required droop
voltage is 84mV. The user should have 40A load current on
and look for 84mV droop. If the drop voltage is less than
84mV, for example, 80mV. The new value will be calculated
by:
84mV
Rdrp2_new = ---------------- ( Rdrp1 + Rdrp2 ) – Rdrp1
80mV
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the example above, the resistance on the DFB pin is Rdrp1
in parallel with Rdrop2, that is, 1K in parallel with 5.82K or
853Ω. The resistance on the VSUM pin is Rn in parallel with
RSEQV or 5.87K in parallel with 1.825K or 1392Ω. The
mismatch in the effective resistances is 1392 - 853 = 539Ω.
Do not let the mismatch get larger than 600Ω. To reduce the
mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate
factor. The appropriate factor in the example is
1392/853 = 1.632. In summary, the predicted load line with
the designed droop network parameters based on the
Intersil design tool is shown in Figure 35.
2 • R droop
Rdrp2 = ⎛ --------------------------------------- – 1⎞ • 1kΩ ≈ 5.82kΩ
⎝ 0.0008 • 0.763
⎠
23
FN9199.2
May 15, 2006
ISL6262
LOAD LINE (mV/A)
2.25
2.2
2.15
2.1
2.05
0
20
40
60
80
100
INDUCTOR TEMPERATURE (°C)
Dynamic Mode of Operation - Compensation
Parameters
FIGURE 35. LOAD LINE PERFORMANCE WITH NTC
THERMAL COMPENSATION
Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value. This could be
problematic if a load dump were to occur during this time.
This situation would cause the output voltage to rise above
the no load setpoint of the converter and could potentially
damage the CPU.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in the following equation:
R n • RS EQV
L
------------- = --------------------------------- • Cn
DCR
R n + RS EQV
(EQ. 23)
Solving for Cn we now have the following equation:
L
------------DCR
C n = ----------------------------------R n • RS EQV
---------------------------------R n + RS EQV
(EQ. 24)
Note, RO was neglected. As long as the inductor time
constant matches the Cn, Rn and Rs time constants as
given above, the transient performance will be optimum. As
in the static droop case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
example of L = 0.36µH with 0.8mΩ DCR, Cn is calculated
below.
0.36μH
-------------------0.0008
C n = ------------------------------------------------------------------ ≈ 330nF
parallel ( 5.87K, 1.825K )
(EQ. 25)
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the load line, and
slowly increases back to the steady state, the cap is too
small and vice versa. It is better to have the cap value a little
24
bigger to cover the tolerance of the inductor to prevent the
output voltage from going lower than the spec. This cap
needs to be a high grade cap like X7R with low tolerance.
There is another consideration in order to achieve better
time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those caps are only available in
small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10X to
reduce the capacitance by 10X. But attention has to be paid
in balancing the impedance of droop amplifier in this case.
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.1mV/A load line, the impedance
needs to be 2.1mΩ. The compensation design has to target
the output impedance of the converter to be 2.1mΩ. There is
a mathematical calculation file available to the user. The
power stage parameters such as L and Cs are needed as
the input to calculate the compensation component values.
Attention has to be paid to the input resistor to the FB pin.
Too high of a resistor will cause an error to the output voltage
regulation because of bias current flowing in the FB pin. It is
better to keep this resistor below 3K when using this file.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6262 through the
matching of the voltages present on the ISEN pins. The
ISL6262 adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel's inductor. For
optimum performance, RL is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with RL to properly compensate the current balance circuit.
ISL6262 uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL6262 forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly equal. Take DCR current
sensing as example, two errors have to be added to find the
total current imbalance. 1) Mismatch of DCR: If the DCR has
a 5% tolerance then the resistors could mismatch by 10%
worst case. If each phase is carrying 20A then the phase
currents mismatch by 20A*10% = 2A. 2) Mismatch of phase
voltages/offset voltage of ISEN pins. The phase voltages are
within 2mV of each other by current balance circuit. The
error current that results is given by 2mV/DCR. If
DCR = 1mΩ then the error is 2A.
FN9199.2
May 15, 2006
ISL6262
In the above example, the two errors add to 4A. For the two
phase DC/DC, the currents would be 22A in one phase and
18A in the other phase. In the above analysis, the current
balance can be calculated with 2A/20A = 10%. This is the
worst case calculation, for example, the actual tolerance of
two 10% DCRs is 10%*sqrt(2) = 7%.
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for
better thermal management. Customer can put a resistor in
parallel with the current sensing capacitor on the phase of
interest in order to purposely increase the current in that
phase.
Now, the input to the droop amplifier is essentially the
Vrsense voltage. This voltage is given by the following
equation:
R sense
Vrsense EQV = -------------------- • I OUT
2
(EQ. 26)
The gain of the droop amplifier, Kdroopamp, must be adjusted
for the ratio of the Rsense to droop impedance, Rdroop. We
use the following equation:
R droop
K droopamp = -------------------- • I OUT
R sense
(EQ. 27)
In the case the pc board trace resistance from the inductor to
the microprocessor are not the same on two phases, the
current will not be balanced. On the phase that have too
much trace resistance a resistor can be added in parallel
with the ISEN capacitor that will correct for the poor layout.
Solving for the Rdrp2 value, Rdroop = 0.0021(V/A) as per
the Intel IMVP-6 specification, Rsense = 0.001Ω and
Rdrp1 = 1kΩ, we obtain the following:
An estimate of the value of the resistor is:
These values are extremely sensitive to layout. Once the
board has been laid out, some tweaking may be required to
adjust the full load droop. This is fairly easy and can be
accomplished by allowing the system to achieve thermal
equilibrium at full load, and then adjusting Rdrp2 to obtain
the desired droop value.
Rtweak = Risen * Rdcr/(Rtrace-Rmin)
where Risen is the resistance from the phase node to the
ISEN pin; usually 10kΩ. Rdcr is the DCR resistance of the
inductor. Rtrace is the trace resistance from the inductor to
the microprocessor on the phase that needs to be tweaked.
It should be measured with a good microOhm meter. Rmin is
the trace resistance from the inductor to the microprocessor
on the phase with the least resistance.
For example, if the pc board trace on one phase is 0.5mΩ
and on another trace is 0.3mΩ; and if the DCR is 1.2mΩ;
then the tweaking resistor is
Rtweak = 10kΩ * 1.2/(0.5 - 0.3) = 60kΩ.
When choosing current sense resistor, not only the tolerance
of the resistance is important, but also the TCR. And its
combined tolerance at a wide temperature range should be
calculated.
Droop Using Discrete Resistor Sensing - Static/
Dynamic Mode of Operation
Figure 36 shows the equivalent circuit of a discrete current
sense approach. Figure 27 shows a more detailed
schematic of this approach. Droop is solved the same way
as the DCR sensing approach with a few slight
modifications.
First, there is no NTC required for thermal compensation,
therefore, the Rn resistor network in the previous section is
not required. Secondly, there is no time constant matching
required, therefore, the Cn component is not matched to the
L/DCR time constant. This component does indeed provide
noise immunity and therefore is populated with a 39pF
capacitor.
Rdrp2 = ( K droopamp – 1 ) • R drp1 = 3.2kΩ
(EQ. 28)
Fault Protection - Overcurrent Fault Setting
As previously described, the overcurrent protection of the
ISL6262 is related to the droop voltage. Previously we have
calculated that the droop voltage = ILoad * Rdroop, where
Rdroop is the load line slope specified as 0.0021 (V/A) in the
Intel IMVP-6 specification. Knowing this relationship, the
overcurrent protection threshold can be set up as a voltage
droop level. Knowing this voltage droop level, one can
program in the appropriate drop across the Roc resistor.
This voltage drop will be referred to as Voc. Once the droop
voltage is greater than Voc, the PWM drives will turn off and
PGOOD will go low.
The selection of Roc is given in equation. Assuming we
desire an overcurrent trip level, Ioc, of 55A, and knowing
from the Intel Specification that the load line slope, Rdroop is
0.0021 (V/A), we can then calculate for Roc as shown in
equation.
I OC • R droop
55 • 0.0021
R OC = ----------------------------------- = ------------------------------ = 11.5kΩ
–6
10μA
10 • 10
(EQ. 29)
Note, if the droop load line slope is not -0.0021 (V/A) in the
application, the overcurrent setpoint will differ from
predicted.
The RS values in the previous section, RS = 1.5k_1% are
sufficient for this approach.
25
FN9199.2
May 15, 2006
+
ISL6262
10µA
OCSET
Voc Roc
+
VSUM
+
DROOP
-
INTERNAL TO
ISL6262
+
VDIFF
VSUM
DFB
DROOP
+
1 -
Rsense
Vrsense EQV = I OUT × ---------------------2
+
Rdrp2
+
RS
RS EQV = -------2
+
1 -
RTN VSEN
VO'
VN
Cn
-
Rdrp1
OC
VO'
RO
RO EQV = --------2
FIGURE 36. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING
26
FN9199.2
May 15, 2006
ISL6262
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
2X
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C)
0.15 C A
MILLIMETERS
D
A
D/2
2X
6
INDEX
AREA
N
0.15 C B
1
2
3
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
0.30
5, 8
4.45
7, 8
4.45
7, 8
A3
b
0.20 REF
0.18
D
E/2
D2
E
A
/ / 0.10 C
C
0.08 C
SEATING PLANE
A3
SIDE VIEW
A1
4.30
-
7.00 BSC
4.15
e
B
TOP VIEW
-
7.00 BSC
4.15
E
E2
0.23
4.30
-
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
N
48
2
Nd
12
3
Ne
12
3
Rev. 2 5/06
5
NX b
0.10 M C A B
D2
7
D2
2
(DATUM B)
8
NX k
N
(DATUM A)
E2
6
INDEX
AREA
E2/2
(Ne-1)Xe
REF.
8
7
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
3
2
1
NX L
N
e
8
(Nd-1)Xe
REF.
BOTTOM VIEW
A1
NX b
5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
27
FN9199.2
May 15, 2006
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