DATASHEET

ISL6264
®
Data Sheet
May 28, 2009
Features
Ordering Information
PKG.
DWG. #
ISL6264 CRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
ISL6264CRZ-T* ISL6264 CRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
Tape and Reel
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free (RoHS Compliant)
Pinout
VID0
BOOT1
40 39 38 37
VID1
ISL6264
(40 LD QFN)
TOP VIEW
36 35
34
33 32
31
SET
1
30 UGATE1
RBIAS
2
29 PHASE1
OFS
3
28 PGND1
SOFT
4
27 LGATE1
OCSET
5
VW
6
COMP
7
24 PGND2
FB
8
23 PHASE2
VDIFF
9
22 UGATE2
26 PVCC
GND PAD
(BOTTOM)
25 LGATE2
21 BOOT2
15 16
17
18 19
20
GND
ISEN2
ISEN1
VDD
12 13 14
VIN
11
VO
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
VSUM
VSEN 10
*Please refer to TB347 for details on reel specifications.
1
• User Programmable Switching Frequency
DFB
TEMP (°C)
PACKAGE
(Pb-Free)
• Audio Filter Enable/Disable
RTN
ISL6264CRZ*
PART
MARKING
• Adjustable Reference-Voltage Offset
DROOP
PART NUMBER
(Note)
• Microprocessor Voltage Identification Input
- 6-Bit VID Input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
VID2
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per AMD mobile CPU
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or precision resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
• Differential Current Sensing: DCR or Resistor
VID3
A 6-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.375V to 1.55V.
A 0.5% system accuracy of the core output voltage over
temperature at active mode is achieved by the ISL6264.
• Dynamic Phase Adding/Dropping
VID4
To boost battery life, the ISL6264 supports PSI_L for deeper
sleep mode via automatically enabling different operation
modes. At heavy load operation of the active mode, the
regulator commands the two phase continuous conduction
mode (CCM) operation. While the PSI_L is asserted during
the deeper sleep mode, the ISL6264 smoothly disables one
phase and operates in a one-phase diode emulation mode
(DE) to maximize the efficiency at light load.
• Internal Gate Driver with 2A Driving Capability
VID5
The heart of the ISL6264 is the patented
Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multi-phase buck regulator, the R3
Technology™ has the fastest transient response. This is due
to the R3 modulator commanding variable switching
frequency during a load transient.
• Voltage Positioning with Adjustable Load Line and Offset
VR_ON
R3
• Precision Two-phase Core Voltage Regulator
- 0.5% System Accuracy Over-temperature
PSI_L
The ISL6264 is a two-phase buck controller with embedded
gate drivers. The two-phase buck controller uses two
interleaved channels to effectively double the output voltage
ripple frequency and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller real estate area.
ISL6264 can also be configured as single-phase controller
for low power CPU applications.
PGOOD
Two-Phase Core Controller for AMD
Mobile Turion CPUs
FN6359.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6264
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V (<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . PHASE -0.3V (DC) to BOOT
PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
-2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W)
θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 25V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
SYMBOL
VDD = 5V, TA = -10°C to +100°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VR_ON = 3.3V
-
3.1
3.6
mA
VR_ON = 0V
-
-
1
µA
INPUT POWER SUPPLY
IVDD
+5V Supply Current
IVIN
Battery Supply Current at VIN Pin
VR_ON = 0V, VIN = 25V
-
-
1
µA
PORr
POR (Power-On Reset) Threshold
VDD Rising
-
4.35
4.5
V
VDD Falling
3.9
4.1
-
V
No load, closed loop, active mode, TA = +25°C to +100°C,
VID = 0.75V to 1.55V
-0.5
-
0.5
%
VID = 0.425V to 0.75V
-2
-
+2
%
VID = 0.375V to 0.425V
-4
-
+4
%
RBIAS Voltage
RRBIAS = 147kΩ
1.5
1.52
1.54
V
VDD_core
(max)
Maximum Output Voltage
VID = [000000]
-
1.55
-
V
VDD_core
(min)
Minimum Output Voltage
VID = [111111]
-
0.375
-
V
285
300
315
kHz
Adjustment Range
200
-
500
kHz
Droop Amplifier Offset
-0.3
-
0.3
mV
-
90
-
dB
PORf
SYSTEM AND REFERENCES
%Error
(VDD_core)
RRBIAS
System Accuracy
CHANNEL FREQUENCY
fSW
Nominal Channel Frequency
RFSET = 6.81kΩ, 2 Channel operation, VCOMP = 2V
AMPLIFIERS
AV0
GBW
SR
Error Amp DC Gain (Note 3)
Error Amp Gain-Bandwidth Product
(Note 3)
CL = 20pF
-
18
-
MHz
Error Amp Slew Rate (Note 3)
CL = 20pF
-
5.0
-
V/µs
2
FN6359.3
May 28, 2009
ISL6264
Electrical Specifications
SYMBOL
VDD = 5V, TA = -10°C to +100°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Imbalance Voltage
-
-
1
mV
Input Bias Current
-
20
-
nA
-48
-43
-38
µA
±185
±210
±235
µA
ISEN1, ISEN2
SOFT START CURRENT
ISS
I2
Soft Start Current
Soft Current during VID on the Fly
GATE DRIVER DRIVING CAPABILITY
RSRC(UGATE) UGATE Source Resistance (Note 4)
500mA Source Current
-
1
1.5
Ω
ISRC(UGATE) UGATE Source Current (Note 4)
VUGATE_PHASE = 2.5V
-
2
-
A
RSNK(UGATE) UGATE Sink Resistance (Note 4)
500mA Sink Current
-
1
1.5
Ω
ISNK(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
RSRC(LGATE) LGATE Source Resistance (Note 4)
500mA Source Current
-
1
1.5
Ω
ISRC(LGATE)
VLGATE = 2.5V
-
2
-
A
RSNK(LGATE) LGATE Sink Resistance (Note 4)
500mA Sink Current
-
0.5
0.9
Ω
ISNK(LGATE)
VLGATE = 2.5V
-
4
-
A
-
1
-
kΩ
Rp(UGATE)
UGATE Sink Current ((Note 4)
LGATE Source Current (Note 4)
LGATE Sink Current(Note 4)
UGATE to PHASE Resistance
GATE DRIVER SWITCHING TIMING (Refer to“ISL6264 Gate Driver Timing Diagram” on page 4 )
tRU
UGATE Rise Time (Note 3)
PVCC = 5V, 3nF Load
-
8.0
-
ns
tRL
LGATE Rise Time (Note 3)
PVCC = 5V, 3nF Load
-
8.0
-
ns
tFU
UGATE Fall Time (Note 3)
PVCC = 5V, 3nF Load
-
8.0
-
ns
tFL
LGATE Fall Time (Note 3)
PVCC = 5V, 3nF Load
-
4.0
-
ns
tPDHU
UGATE Turn-on Propagation Delay
PVCC = 5V, Outputs Unloaded
23
30
44
ns
tPDHL
LGATE Turn-on Propagation Delay
PVCC = 5V, Outputs Unloaded
7
15
30
ns
0.43
0.58
0.67
V
BOOTSTRAP DIODE
Forward Voltage
VDDP = 5V, Forward Bias Current = 2mA
Leakage
VR = 16V
-
-
1
µA
POWER GOOD and PROTECTION MONITOR
VOL
PGOOD Low Voltage
IPGOOD = 4mA
-
0.11
0.4
V
IOH
PGOOD Leakage Current
PGOOD = 3.3V
-1
-
1
µA
tpgd
PGOOD Delay
VR_ON Enable to PGOOD High when CSOFT = 47nF
6.3
7.6
8.9
ms
OVH
Overvoltage Threshold
VO rising above setpoint >1ms
155
195
235
mV
Severe Overvoltage Threshold
VO rising above setpoint >0.5µs
1.775
1.8
1.825
V
OCSET Reference Current
Rbias = 147kΩ
10
10.2
10.4
µA
OC Threshold Offset
DROOP rising above OCSET >120µs
-3
-
3
mV
Current Imbalance Threshold
Difference between ISEN1-ISEN2 >1ms
-
8
-
mV
Undervoltage Threshold
(VDIFF-SOFT)
VO falling below setpoint for >1ms
-300
-250
-200
mV
OVHS
UVf
3
FN6359.3
May 28, 2009
ISL6264
Electrical Specifications
SYMBOL
VDD = 5V, TA = -10°C to +100°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
33
-
µA
-
33
-
µA
OFFSET FUNCTION
IOFFSET
IFB
OFS Pin Current
36.5kΩ resistor connects OFS pin to GND.
FB Pin Souring Current
LOGIC INPUTS
VIL(3.3V)
VR_ON
-
-
1
V
VIH(3.3V)
VR_ON
2.3
-
-
V
IIL(3.3V)
Leakage current of VR_ON
Logic input is low
-1
0
-
µA
Logic input is high at 3.3V
-
0
1
µA
IIL(3.3V)
VIL(3.3V)
SET
-
-
1
V
VIH(3.3V)
SET
2.3
-
-
V
IIL(3.3V)
Leakage Current of SET
Logic input is low
-1
0
-
µA
Logic input is high at 3.3V
-
0.45
1
µA
-
-
0.3
V
0.7
-
-
V
Logic input is low
-1
0
-
µA
Logic input is high at 1V
-
0.45
1
µA
IIL(3.3V)
VIL(1.0V)
DAC(VID0 - VID5) and PSI_L Input Low
VIH(1.0V)
DAC(VID0 - VID5), PSI_L input High
IIL(1V)
Leakage Current of DAC
(VID0 - VID5) and PSI_L
NOTES:
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
ISL6264 Gate Driver Timing Diagram
PWM
t PDHU
t FU
tt RU
1V
UGATE
LGATE
1V
t RL
t FL
t PDHL
4
FN6359.3
May 28, 2009
ISL6264
40 39 38 37 36 35 34
FB
This pin is the inverting input of the error amplifier.
BOOT1
VID0
VID1
VID2
VID3
VID4
VID5
VR_ON
PSI_L
PGOOD
Functional Pin Description
VDIFF
33 32 31
This pin is the output of the differential amplifier.
SET
1
30 UGATE1
VSEN
RBIAS
2
29 PHASE1
Remote core voltage sense input.
OFS
3
28 PGND1
SOFT
4
27 LGATE1
OCSET
5
VW
6
COMP
7
24 PGND2
FB
8
23 PHASE2
VDIFF
9
22 UGATE2
RTN
Remote core voltage sense return.
26 PVCC
GND PAD
(BOTTOM)
25 LGATE2
VSEN 10
21 BOOT2
DROOP
Output of the droop amplifier. The voltage level at this pin is
the sum of Vo and the programmed droop voltage by the
external resistors.
DFB
ISEN1
ISEN2
VDD
GND
VIN
VO
RTN
VSUM
18 19 20
DFB
12 13 14 15 16 17
DROOP
This pin is the inverting input of the droop amplifier.
11
VO
An input to IC reporting the local output voltage.
VSUM
SET
Logic low enables the audio filter which only allows above
20kHz operation. Logic high disables the audio filter.
RBIAS
147kΩ resistor to GND sets internal current reference,
~10µA, for the overcurrent protection setting.
OFS
This pin is connected to the summation junction of channel
current sensing.
VIN
It is used for input voltage feed forward to improve input line
transient performance.
GND
Signal ground. Connect to local controller ground.
A resistor from this pin to GND programs a DC current
source for generating a positive offset voltage across the
resistor between FB and VDIFF pins. The OFS pin voltage is
1.2V.
VCC
5V bias power supply for the ISL6264 controller.
ISEN2
SOFT
Individual current sharing sensing for channel 2.
A capacitor from this pin to GND pin sets the maximum slew
rate of the output voltage. The SOFT pin is the non-inverting
input of the error amplifier. A 210µA internal current source is
generated to charge or discharge the SOFT pin capacitor to
determine the slew-rate of VID. During the start-up process,
the current source is reduced to 43µA.
ISEN1
OCSET
UGATE2
Overcurrent protection set input. A resistor from this pin to
VO sets DROOP voltage limit for OC trip. A 10µA current
source is connected internally to this pin.
Upper MOSFET gate signal for phase 2.
VW
A resistor from this pin to COMP programs the switching
frequency (for example, 6.81k ~ 300kHz).
Individual current sharing sensing for channel 1.
BOOT2
This pin is the upper gate driver supply voltage for phase 2.
An internal boot strap diode is connected to the PVCC pin.
PHASE2
The phase node of phase 2. This pin should connect to the
source of upper MOSFET. It is the return path for the upper
MOSFET drive.
PGND2
COMP
This pin is the output of the error amplifier.
The return path of the lower gate driver for phase 2.
LGATE2
Lower-side MOSFET gate signal for phase 2.
5
FN6359.3
May 28, 2009
ISL6264
PVCC
5V power supply for gate drivers.
LGATE1
Lower-side MOSFET gate signal for phase 1.
PGND1
The return path of the lower gate driver for phase 1.
PHASE1
The phase node of phase 1. This pin should connect to the
source of upper MOSFET. It is the return path for the upper
MOSFET drive.
UGATE1
Upper MOSFET gate signal for phase 1.
BOOT1
This pin is the upper gate driver supply voltage for phase 1.
An internal boot strap diode is connected to the PVCC pin.
VID0, VID1, VID2, VID3, VID4, VID5
VID input with VID0 is the least significant bit (LSB) and
VID5 is the most significant bit (MSB).
VR_ON
A high level logic signal on this pin enables the ISL6264.
PSI_L
Sleeper mode indicator. When asserted low, ISL6264
initiates the single-phase operation.
PGOOD
Power good open-drain output. Will be pulled up externally
by a resistor to VCCP or 3.3V.
6
FN6359.3
May 28, 2009
Function Block Diagram
RBIAS
PGOOD
ISEN1
ISEN2
VIN
VCC PVCC
VO
VIN
VID0
PGOOD
MONITOR AND
LOGIC
FLT
VID1
FAULT AND
PGOOD
LOGIC
VID2
DAC
VID3
CURRENT
BALANCE
7
PGOOD
DACOUT
VID4
PVCC
I_BALF
PVCC
VID5
MODE CHANGE
REQUEST
CH1 OC VIN VSOFT
PHASE
CONTROL
LOGIC
VO
FLT
DRIVER
LOGIC
MODULATOR
MODE
CONTROL
SOFT
PHASE1
PVCC
SINGLE
PHASE
LGATE1
ULTRASONIC
TIMER
PHASE
SEQUENCER
0.5
PGND1
PVCC
BOOT2
CH2
OCSET
+
VO
DFB
DROOP
+
DROOP
FILTER
FLT
VW
MODULATOR
VSOFT
+
1
-
E/A
+
1
-
+
1
VW
VDIFF SET SOFT FB
COMP
VW
OFS
UGATE2
DRIVER
LOGIC
+
1
+
VSEN RTN
VIN VO
AUDIO
VO
OC
OC VIN VSOFT
GND
FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6264
+
-
+
-
PHASE2
PVCC
LGATE2
1.2V
VCC
PGND2
ISL6264
SINGLE
PHASE
10uA
UGATE1
CH2
VR_ON
PSI_L
BOOT
CH1
FN6359.3
May 28, 2009
ISL6264
Simplified Application Circuit for DCR Current Sensing
PVCC
VDD
R 12
RBIAS
VIN
V IN
V +5
V IN
C7
ISL6264
C8
UGATE1
BOOT1
SOFT
VID<0:5>
VIDs
PHASE
LO
C6
ROFS
R
OFS
LGATE1
PSI_L
PSI_L
R8
PGND1
CL
L
DNP
ISEN1
ISEN2
VO
VSUM
ISEN1
VO
SET
SET
CO
Cf
VR_ON
V IN
VR_ON
C8
PGOOD
CPU_PWRGD
VSEN
REMOTE
SENSE
UGATE2
RTN
R2
VDIFF
R3
LO
BOOT2
PHASE
C3
C5
DNP
RL
LGATE2
FB
C1
COMP
R FSET
DROOP
DFB
GND
ISEN1
VO
VSUM
VSUM
VW
ISEN2
9
VSUM
ISEN2
C2
C9
R
PGND2
R1
CL
OCSET
R5
R6
R4
C4
RN
NTC
Network
C CS
VO
FIGURE 2. ISL6264 BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
8
FN6359.3
May 28, 2009
ISL6264
Simplified Application Circuit for Resistor Current Sensing
PVCC
VDD
R 12
RBIAS
VIN
V IN
V +5
V IN
C7
ISL6264
C8
UGATE1
BOOT1
SOFT
VIDs
VID<0:5>
PHASE
1
LO
R SENSE
C6
R OFS
R
OFS
LGATE1
PSI_L
PSI_L
R8
PGND1
CL
L
ISEN1
VO
VSUM
ISEN1
VO
SET
SET
CO
Cf
V IN
VR_ON
VR_ON
C8
PGOOD
CPU_PWRGD
VSEN
REMOTE
SENSE
UGATE2
BOOT2
RTN
R2
VDIFF
R3
PHASE
C3
LO
R SENSE
C5
RL
LGATE2
FB
C1
COMP
RFSET
DROOP
DFB
GND
VO
VSUM
VSUM
VW
ISEN2
VSUM
ISEN2
C2
C9
R9
PGND2
R1
CL
OCSET
R5
R6
R4
C CS
RN
C4
VO
FIGURE 3. ISL6264 BASED TWO-PHASE BUCK CONVERTER WITH RESISTOR CURRENT SENSING
9
FN6359.3
May 28, 2009
ISL6264
Typical Performance Curves
(0.36µH filter inductor, 4x330µF output SP caps and 32x22µF ceramic caps)
100
1.16
90
1.15
VIN = 12.6V
70
1.14
VIN = 8.0V
50
40
1.10
20
1.09
10
1.08
0
5
10
15
20
IOUT (A)
25
30
35
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
IOUT (A)
FIGURE 5. ACTIVE MODE LOAD LINE, 2 PHASE, CCM,
PSI_L = HIGH, VID = 1.15V
100
1.155
90
1.150
80
70
VIN = 12.6V
1.145
VIN = 19.0V
VOUT (V)
VIN = 8.0V
60
50
40
1.140
1.125
1.120
10
1.115
5
10
IOUT (A)
15
20
FIGURE 6. ACTIVE MODE EFFCIENCY, 1 PHASE, DE,
PSI_L = LOW, VID = 1.15V
VIN = 12.6V
1.130
20
0
VIN = 8.0V
1.135
30
0
VIN = 19.0V
1.07
40
FIGURE 4. ACTIVE MODE EFFICIENCY, 2 PHASE, CCM,
PSI_l = HIGH, VID = 1.15V
EFFICIENCY (%)
1.12 VIN = 12.6V
1.11
30
0
VIN = 8.0V
1.13
VIN = 19.0V
60
VOUT (V)
EFFICIENCY (%)
80
VIN = 19.0V
1.110
0
2
4
6
8
10
12
IOUT (A)
14
16
18
20
FIGURE 7. ACTIVE MODE LOAD LINE, 1 PHASE, DE,
PSI_L = LOW, VID = 1.15V
100
0.964
90
0.954
70
60
VIN = 12.6V
VIN = 19.0V
VIN = 8.0V
VOUT (V)
EFFICIENCY (%)
80
50
0.944
VIN = 19.0V
0.934
VIN = 8.0V
40
0.924
30
20
VIN = 12.6V
0.914
10
0
0.904
0.1
1
IOUT (A)
FIGURE 8. EFFICIENCY OF 1-PHASE DE MODE,
PSI_l = LOW. DCM MODE, VID = 0.9V,
OFFSET = 33mV
10
10
0
2
3
IOUT (A)
4
5
6
FIGURE 9. 1-PHASE DE MODE LOAD LINE, PSI_l = LOW,
VID = 0.9V, OFFSET = 33mV
FN6359.3
May 28, 2009
ISL6264
Typical Performance Curves
(0.36µH filter inductor, 4x330µF output SP caps and 32x22µF ceramic caps) (Continued)
VR_ON
VR_ON
VR_ON
VR_ON
VO
Vo
VVo
O
PGOOD
PGOOD
PGOOD
PGOOD
FIGURE 10. SOFT START WAVEFORM AT VID = 1.55V,
ILOAD = 0A
FIGURE 11. PRE-BIASED VO SOFT START AT VID = 1.55V,
ILOAD = 0A
IL1
IL1
VO
Vo
IL2
IL2
IL1, IL2
IL1,
IL2
VO
Vo
PHASE1
Phase1
FIGURE 12. SOFT START WAVEFORM SHOWING CURRENT
SHARING AT VIN = 12.6V, VID = 1.2V AND
ILOAD = 36A
VO
Vo
PHASE11
Phase
FIGURE 13. PHASE CURRENT BALANCE, ILOAD = 36A AND
VID = 1.55V
VO
Vo
PHASE11
Phase
VIN
Vin
VIN
Vin
FIGURE 14. 8V TO19V INPUT LINE TRANSIENT RESPONSE
AT ILOAD = 5A AND VID = 1.15V
11
FIGURE 15. 19V TO >8V INPUT LINE TRANSIENT RESPONSE
AT ILOAD = 5A AND VID = 1.15V
FN6359.3
May 28, 2009
ISL6264
Typical Performance Curves
(0.36µH filter inductor, 4x330µF output SP caps and 32x22µF ceramic caps) (Continued)
IO
Io
IO
Io
COMP
COMP
VO
Vo
VO
Vo
COMP
COMP
PHASE1
Phase1
PHASE1
Phase1
FIGURE 16. LOAD APPLICATION RESPONSE AT 2-PHASE
CCM, VIN = 19V, ILOAD = 10A→46A, AND
VID = 1.15V
FIGURE 17. LOAD RELEASE RESPONSE AT 2-PHASE CCM,
VIN = 19V, ILOAD = 46A→10A, AND VID = 1.15V
VO
Vo
VO
Vo
COMP
COMP
PHASE1
Phase1
COMP
COMP
FIGURE 18. LOAD APPLICATION RESPONSE AT 1-PHASE DE
MODE, ILOAD = 4A→19A, PSI_L = 0, AND VID = 1V
PHASE1
Phase1
FIGURE 19. LOAD RELEASE RESPONSE AT 1-PHASE DE
MODE, ILOAD = 19A→4A, PSI_L = 0, AND VID = 1V
UGATE
Ugate
CH1:SOFT
Ch1:soft
CH2:VOVo
Ch2:
LGATE
Lgate
VID4
VID4
PGOOD
PGOOD
FIGURE 20. VID TRANSITION RESPONSE AT 2-PHASE CCM
MODE, VIN = 12.6V AND VID = 1.55V←→ 1.15V
12
FIGURE 21. GATE DRIVER WAVEFORMS AT VIN = 8V,
ILOAD = 40A, 2-PHASE MODE. 2 X IRF7821 AS
UPPER DEVICE AND 2 X IRF7832 AS LOWER
DEVICE
FN6359.3
May 28, 2009
ISL6264
Typical Performance Curves
(0.36µH filter inductor, 4x330µF output SP caps and 32x22µF ceramic caps) (Continued)
LGATE
Lgate
UGATE
Ugate
PHASE1
Phase1
FIGURE 22. GATE DRIVER WAVEFORMS AT VIN = 8V,
ILOAD = 40A, 2 X IRF7821 AS UPPER MOSFET
AND 2 X IRF7832 AS LOWER MOSFET
FIGURE 23. PHASE NODE JITTER PERFORMANCE AT
VIN = 19V, ILOAD = 40A AND VID = 1.55V
VO
Vo
VO
Vo
PSI_L
PSI_L
PSI_L
PSI_L
PHASE1
Phase1
PHASE1
Phase1
PHASE2
Phase2
PHASE2
Phase2
FIGURE 24. DEEPER SLEEP MODE ENTRY WITH PSI_L
TOGGLING FROM HIGH TO LOW AND VID FROM
1.15V TO 0.95V
FIGURE 25. DEEPER SLEEP MODE EXIT WITH PSI_L
TOGGLING FROM LOW TO HIGH AND VID FROM
0.95V TO 1.15V
VO
Vo
VO
Vo
PSI_L
PSI_L
PSI_L
PSI_L
PHASE1
Phase1
PHASE1
Phase1
PHASE2
Phase2
PHASE2
Phase2
FIGURE 26. TRANSITION FROM 1-DE TO 2-CCM VIA PSI_L
TOGGLING FROM LOW TO HIGH AND
ILOAD = 2A
13
FIGURE 27. TRANSITION FROM 2-CCM TO 1-DE VIA PSI_L
TOGGLING FROM HIGH TO LOW AND
ILOAD = 2A
FN6359.3
May 28, 2009
ISL6264
Theory of Operation
The ISL6264 is a two-phase regulator providing the power to
AMD Mobile CPUs such as the Turion processor and
includes integrated gate drivers for reduced system cost and
board area. The regulator provides optimum steady-state
and transient performance for microprocessor core
applications up to 50A. System efficiency is enhanced by
idling a phase at low-current and implementing automatic
DCM-mode operation when PSI_L is asserted to logic low.
The heart of the ISL6264 is the R3 Technology™, Intersil's
Robust Ripple Regulator modulator. The R3 modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. The ISL6264 modulator internally synthesizes
an analog of the inductor ripple current and uses hysteretic
comparators on those signals to establish PWM pulse
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL6264 to achieve lower
output ripple and lower phase jitter than either conventional
hysteretic or fixed frequency PWM controllers. Unlike
conventional hysteretic controllers, the ISL6264 has an error
amplifier that allows the controller to maintain a 0.5% voltage
regulation accuracy throughout the VID range from 0.75V to
1.55V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
Start-up Timing
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
100ms later, SOFT and VOUT begin ramping toward the final
VID voltage. At startup, the regulator always operates in a
2-phase CCM mode, regardless of PSI_L control signal
assertion levels. During this interval, the SOFT cap is
charged by a 43µA current source. If the SOFT capacitor is
selected to be 47nF, the SOFT ramp will be at 0.9mV/s slew
rate. Once VOUT is within 10% of the VID voltage,
approximately 7ms later, PGOOD is asserted HIGH. Typical
start-up timing is shown in Figure 28. The SOFT cap is
charged/discharged by approximate 200µA after the
start-up. Therefore, VOUT slews at about 4mV/s to the
voltage set by the VID pins.
14
VDD
VR_ON
dV 43μA
-------- ª ---------------dt C soft
100µs
SOFT AND VO
~7.6ms
PGOOD
FIGURE 28. SOFT START WAVEFORMS
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs per Table 1. The entire VID
table is presented in the AMD specification. The ISL6264 will
control the no-load output voltage to an accuracy of ±0.5%
over the range of 0.75V to 1.5V.
TABLE 1. VID TABLE FOR AMD 6-BIT VID CPU
VID5
VID4
VID3
VID2
VID1
VID0
VOUT
(V)
0
0
0
0
0
0
1.5500
0
0
0
0
0
1
1.5250
0
0
0
0
1
0
1.5000
0
0
0
0
1
1
1.4750
0
0
0
1
0
0
1.4500
0
0
0
1
0
1
1.4250
0
0
0
1
1
0
1.4000
0
0
0
1
1
1
1.3750
0
0
1
0
0
0
1.3500
0
0
1
0
0
1
1.3250
0
0
1
0
1
0
1.3000
0
0
1
0
1
1
1.2750
0
0
1
1
0
0
1.2500
0
0
1
1
0
1
1.2250
0
0
1
1
1
0
1.2000
0
0
1
1
1
1
1.1750
0
1
0
0
0
0
1.1500
0
1
0
0
0
1
1.1250
0
1
0
0
1
0
1.1000
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.9750
0
1
1
0
0
0
0.9500
0
1
1
0
0
1
0.9250
0
1
1
0
1
0
0.9000
FN6359.3
May 28, 2009
ISL6264
TABLE 1. VID TABLE FOR AMD 6-BIT VID CPU (Continued)
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the microprocessor die. The
inputs to the amplifier are the VSEN and RTN pins.
VID5
VID4
VID3
VID2
VID1
VID0
VOUT
(V)
0
1
1
0
1
1
0.8750
0
1
1
1
0
0
0.8500
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
1
0
1
0
1
0
0.6375
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
High Efficiency Operation Mode
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
The ISL6264 has two operating modes to optimize efficiency.
The controller's operational modes are designed to work in
conjunction with the PSI_L control signal to maintain the
optimal system configuration. These operating modes are
established as shown in Table 2. At high current levels, the
system will operate with both phases fully active, responding
rapidly to transients and deliver the maximum power to the
load. At reduced load current levels, one of the phases may
be idled. This configuration will minimize switching losses,
while still maintaining transient response capability. At the
lowest current levels, the controller automatically configures
the system to operate in single-phase automatic-DCM mode,
thus achieving the highest possible efficiency. In this mode of
operation, the lower FET will be configured to automatically
detect and prevent discharge current flowing from the output
capacitor through the inductors, and the switching frequency
will be proportionately reduced, thus greatly reducing both
conduction and switching losses.
15
As the load current increases from zero, the output voltage will
droop from the VID table (Table 1) value by an amount
proportional to current to achieve the proper load line. The
ISL6264 provides for current to be measured using either
resistors in series with the channel inductors as shown in the
application circuit of Figure 3, or using the intrinsic series
resistance of the inductors as shown in the application circuit
of Figure 2. In both cases signals representing the inductor
currents are summed at VSUM, which is the non-inverting
input to the DROOP amplifier shown in the block diagram of
Figure 1. The voltage at the DROOP pin minus the output
voltage, VO, is a high-bandwidth analog of the total inductor
current. This voltage is used as an input to a differential
amplifier to achieve the load line, and also as the input to the
overcurrent protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the load-line
accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to cause
the voltages presented at the ISEN pins to be equal.
The ISL6264 controller can be configured for two-channel
operation, with the channels operating 180° apart. The
channel PWM frequency is determined by the value of RFSET
connected to pin VW as shown in Figure 2 and Figure 3. Input
and output ripple frequencies will be the channel PWM
frequency multiplied by the number of active channels.
FN6359.3
May 28, 2009
ISL6264
Dynamic Operation
TABLE 2.
PSI_L = LOGIC HIGH
PSI_L = LOGIC LOW
2-CCM
1-DE (diode emulation)
Operation
Smooth mode transitions are facilitated by the R3
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
regulator is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms which robustly
maintain voltage-regulation for all control signal input
sequences and durations.
Mode-transition sequences will often occur in concert with VID
changes; therefore the timing of the mode transition of
ISL6264 has been carefully designed to work in concert with
VID changes. For example, transitions into single-phase
mode if PSI_L and VID toggles at the same time will be
delayed until the VID induced voltage ramp is complete, to
allow the associated output capacitor charging current is
shared by both inductor paths. While in single-phase
automatic-DCM mode with PSI_L = logic low, VID changes
will initiate an immediate return to two-phase CCM mode
during the VID transition. This ensures that both inductor
paths share the output capacitor charging current and are fully
active for the subsequent load current increases.
The controller contains internal counters which prevent
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling. Signals of less than
seven switching periods do not result in implementation of
automatic-DCM mode.
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into automatic-DCM or
forced-CCM mode, the timing is carefully adjusted to eliminate
output voltage excursions. When a phase is added, the
current balance between phases is quickly restored.
The ISL6264 responds to changes in VID command voltage
by slewing to new voltages with a dV/dt set by the SOFT
capacitor. The internal current source of 230µA is used to
charge or discharge the SOFT capacitor.
Intersil's R3 Technology™ has intrinsic voltage feed forward.
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6264 will transiently raise the
switching frequency so that response time is decreased and
current is shared by two channels.
Protection
The ISL6264 provides overcurrent, overvoltage, and
undervoltage protection as shown in Table 3.
Overcurrent protection is tied to the voltage droop which is
determined by the resistors selected as described in the
"Component Selection and Application" section on page 17.
After the load-line is set, the OCSET resistor can be selected
to detect overcurrent at any level of droop voltage. An
overcurrent fault will occur when the load current exceeds
the overcurrent setpoint voltage while the regulator is in a
2-phase mode. While the regulator is in a 1-phase mode of
operation, the overcurrent setpoint is automatically reduced
by half. For overcurrents less than 2.5 times the OCSET
level, the over-load condition must exist for 120µs in order to
trip the OC fault latch.
For overloads exceeding 2.5 times the set level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection due to hard shorts.
In addition, excessive phase unbalance, for example, due to
gate driver failure, will be detected in two-phase operation
and the controller will be shut-down after one millisecond's
detection of the excessive phase current unbalance. The
phase unbalance is detected by the voltage on the ISEN
pins if the difference is greater than 9mV.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6264
FAULT DUATION
PRIOR TO
PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurrent fault
<2µs
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
Low-side FET on until Vcore <0.85V, then PWMs
three-state, PGOOD latched low (OV-1.8V always)
VDD toggle
Overvoltage fault (1.8V)
immediately
Overvoltage fault (+200mV)
1ms
ISL6264 still tries to regulate VCORE, PGOOD latched low VR_ON toggle or VDD toggle
Undervoltage fault (-300mV)
1ms
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
Unbalance fault (9mV)
1ms
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
16
FN6359.3
May 28, 2009
ISL6264
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after one millisecond in that
condition. The PWM outputs will turn off and PGOOD will go
low. Note that most practical core regulators will have the
overcurrent set to trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
For output voltage exceeding the set value by +200mV for
1ms, a fault is declared. All of the above faults have the
same action taken except 200mV overvoltage fault: PGOOD
is latched low and the upper and lower power FETs are
turned off so that inductor current will decay through the FET
body diodes. This condition can be reset by bringing VR_ON
low or by bringing VDD below 4V. When these inputs are
returned to their high operating levels, a soft-start will occur.
Under 200mV overvoltage fault, PGOOD is latched low but
the ISL6264 still tries to regulate the output voltage.
The second level of overvoltage protection behaves
differently. If the output exceeds 1.8V, an OV fault is
immediately declared, PGOOD is latched low and the
low-side FETs are turned on. The low-side FETs will remain
on until the output voltage is pulled down below about 0.85V
at which time all FETs are turned off. If the output again rises
above 1.7V, the protection process is repeated. This affords
the maximum amount of protection against a shorted
high-side FET while preventing output ringing below ground.
The 1.8V OV is not reset with VR_ON, but requires that VDD
be lowered to reset. The 1.8V OV detector is active at all
times that the controller is enabled including after one of the
other faults occurs so that the processor is protected against
high-side FET leakage while the FETs are commanded off.
1.2V
OFFSET ≡ ---------------- R CIN
R OFS
(EQ. 1)
Normally we chose RCIN as 1kΩ for the convenience of
design, then ROFS of 36.5kΩ will result in a positive
OFFSET voltage of 33mV.
Component Selection and Application
Soft-Start and VID Transition Slew Rates
The ISL6264 uses two different slew rates for start-up and
the normal operation mode. The first is a slow slew rate in
order to reduce inrush current during start-up. Note that the
SOFT cap current is bidirectional. The current is flowing into
the SOFT capacitor when the output voltage is commanded
to rise, and out of the SOFT capacitor when the output
voltage is commanded to fall.
The two slew rates are determined by commanding one of
two current sources onto the SOFT pin. As can be seen in
Figure 30, the SOFT pin has a capacitance to ground. Also,
the SOFT pin is the input to the error amplifier and is,
therefore, the commanded system voltage. Depending on
the state of the system, i.e. Start-Up or After Start-up, one of
the two currents shown in Figure 30 will be used to charge or
discharge this capacitor, thereby controlling the slew rate of
the commanded voltage. These currents can be found under
the “Soft-Start Current“ section of theTable Electrical
Specifications on page 2.
ISL6264
I SS
Offset Voltage
The reference voltage at OFS pin is 1.2V. A resistor (ROFS)
connecting the OFS pin to GND will setup a current flowing
out of OFS pin. This current is internally mirrored out of FB
pin. Therefore, a voltage drop is established across the
resistor between FB and VDIFF pin. For the convenience of
illustration, name the compensation network resistor
between FB and VDIFF as RCIN.
I2
ERROR
AMPLIFIER
+
SOFT
+
CSOFT
VREF
VO (V)
FIGURE 30. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
OFFSET
VID
0
IO (A)
FIGURE 29. LOAD LINE AND OFFSET
17
The first current, labelled ISS, is given in the Specification
Table as 43A. This current is used during Soft-Start. The
second current, I2 sums with ISS to get the larger of the two
currents, labeled IGV in the Electrical Specification Table.
This total current is typically 210A with a minimum of 185A.
The symbol, SLEWRATE, will determine the choice of the
SOFT capacitor, CSOFT, by Equation 2:
I2
C SOFT ≡ -----------------------------------SLEWRATE
(EQ. 2)
FN6359.3
May 28, 2009
ISL6264
Static Mode of Operation - Processor Die Sensing
Using a SLEWRATE of 4.2mV/µs, and the typical I2 value,
given in the Electrical Specification table of 230µA, CSOFT is
shown in Equation 3:
C SOFT ≡ ( 230μA ) ⁄ ( 4.2 )
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
(EQ. 3)
A choice of 0.047µF would guarantee a SLEWRATE of
3.7mV/µs is met for minimum I3 value, given in the
Table Electrical Specifications on page 2. This choice of
CSOFT will then control the Start-Up slew rate as well. One
should expect the output voltage to slew to the VID value of
1.2V at a rate given by Equation 4:
I SS
mV
43μA
dV
- = ----------------------- = 0.9
------- = -----------------⁄ ( μS )
0.047μF
C SOFT
dt
The VSEN and RTN pins of the ISL6264 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are VCC_SENSE and
VCC_SENSE respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
(EQ. 4)
Selecting RBIAS
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode capacitor filters to analog ground on VSEN and RTN.
Whether to need these capacitors really depends on the
actual board layout and noise environment.
To properly bias the ISL6264, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10A current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Due to the fact that the voltage feedback to the switching
regulator is sensed at the processor die, there exists the
potential of an over voltage due to an open circuited
feedback signal, should the regulator be operated without
the processor installed. Due to this fact, we recommend the
use of the Ropn1 and Ropn2 connected to VOUT and ground
(illustrated in Figure 31). These resistors will provide voltage
feedback in the event that the system is powered up without
a processor installed. These resistors may typically range
from 20Ω to 100Ω.
Start-up Operation - PGOOD
The internal timer allows PGOOD to go high approximately
7.6ms after Vout reaches the target VID voltage during the
start-up.
ISEN1
ISEN2
ISEN2
10µA
OCSET
+
ROCSET
VSUM
INTERNAL TO
ISL6264
DFB
+
+
1 VSEN
RTN
VDIFF
VO'
RNTC
S
CN
DROOP
+
1 -
RDRP2
+
VSUM
ROCSET
0.018µF
10
VCC_SENSE
VSS_SENSE
ROPN2
RL1
IPHASE2
VO'
ROPN1
DCR
RS
VSUM
ISEN1
L2
RL2
ISEN2
0.018µF
0.018µF
VSUM
+ VDCR-1
L1
RS
RSERIES
+
DROOP
-
IPHASE1
VO'
RDRP1
OC
RPAR
ISEN1
CL1
RO1
VO'
VOUT
DCR
VDCR
+
2RO2
CBULK
CL2
VO'
ESR
TO VOUT
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
FIGURE 31. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
18
FN6359.3
May 28, 2009
ISL6264
10µA
OC SE T
RS
+
OC
VSUM
+
DROOP
-
INTERNAL TO
ISL6264
VD IFF
+
VSEN
RTN
CN
+
1 -
RD RP1
S
+
VSUM
RD RP2
+
RS
= -------2
DFB
DR OOP
+
1 -
EQV
VO'
Vdcr
EQV
= I
OUT
DCR
× ------------2
VN
-
VO '
FIGURE 32. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM
architecture. The switching frequency can increase during
the application of a load to improve transient performance.
It also varies slightly due changes in input and output voltage
and output current, but this variation is normally less than
10% in continuous conduction mode.
Refer to Figure 2. The resistor connected between the VW
and COMP pins of the ISL6264 adjusts the switching
window, and therefore adjusts the switching frequency. The
RFSET resistor that sets up the switching frequency of the
controller operating in CCM can be determined using the
following relationship, where RFSET is in kΩ and the
switching period is in µs. 6.81kΩ sets about 300kHz
switching frequency (see Equation 5).
R FSET ( kΩ ) ∼ ( period ( μs ) – 0.4 ) ⋅ 2.33
(EQ. 5)
In discontinuous conduction mode (DCM), the ISL6264 runs
into period stretching mode. The switching frequency is
dependent on the load current level. In general, the lighter
load, the slower switching frequency. Therefore, the
switching loss is much reduced for the light load operation,
which is important for conserving the battery power in the
portable application.
Static Mode of Operation - Static Droop Using DCR
Sensing
As previously mentioned, the ISL6264 has an internal
differential amplifier which provides very accurate voltage
regulation at the die of the processor. The load line
regulation is also accurate for both two-phase and
single-phase operation. The process of selecting the
components for the appropriate load line droop is explained
here.
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired load line droop
has several steps and is somewhat iterative.
19
The two-phase solution using DCR sensing is shown in
Figure 31. There are two resistors connecting to the
terminals of inductor of each phase. These are labeled RS
and RO. These resistors are used to obtain the DC voltage
drop across each inductor. Each inductor will have a certain
level of DC current flowing through it, and this current when
multiplied by the DCR of the inductor creates a small DC
voltage drop across the inductor terminal. When this voltage
is summed with the other channels DC voltages, the total DC
load current can be derived.
RO is typically 1Ω to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS tied
together, the simplified model for the droop circuit can be
derived. This is presented in Figure 32.
Essentially one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by:
I OUT ⋅ DCR
V DCR_EQU = -------------------------------2
(EQ. 6)
For the convenience of analysis, the NTC network
comprised of Rntc, Rseries and Rpar, given in Figure 31, is
labelled as a single resistor Rn in Figure 32.
The first step in droop load line compensation is to adjust Rn,
ROEQV and RSEQV such that sufficient droop voltage exists
even at light loads between the VSUM and VO' nodes. As a
rule of thumb we start with the voltage drop across the Rn
network, VN, to be 0.5-0.8 times VDCR_EQU. This ratio
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
FN6359.3
May 28, 2009
ISL6264
The resultant NTC network resistor value is dependent on
the temperature and given by Equation 7:
( R series + R ntc ) ⋅ R par
R n ( T ) = ------------------------------------------------------------R series + R ntc + R par
(EQ. 7)
For simplicity, the gain of VN to the VDCR_EQU is defined by
G1, also dependent on the temperature of the NTC
thermistor (see Equation 8).
Rn ( T )
G 1 ( T ) = ---------------------------------------R n ( T ) + R sequ
(EQ. 8)
DCR ( T ) = DCR 25C ⋅ ( 1 + 0.00393*(T-25) )
(EQ. 9)
Therefore, the output of the droop amplifier divided by the
total load current can be expressed in Equation 10:
DCR 25
R droop = G 1 ( T ) ⋅ ------------------- ⋅ ( 1 + 0.00393*(T-25) ) ⋅ k droop
2
(EQ. 10)
where RDROOP is the realized load line slope and 0.00393 is
the temperature coefficient of the copper. To achieve the
droop value independent from the temperature of the
inductor, it is equivalently expressed by Equation 11:
G 1 ( T ) ⋅ ( 1 + 0.00393*(T-25) ) ≅ G 1t arg et
(EQ. 11)
The non-inverting droop amplifier circuit has the gain
kdroopamp expressed as shown in Equation 12:
R drp2
k droopamp = 1 + ---------------R drp1
(EQ. 12)
G1target is the desired gain of Vn over IOUT. DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described in Equation 13:
1 1t arg et
G 1 ( T ) = ------------------------------------------------------( 1 + 0.00393*(T-25) )
(EQ. 13)
For the G1 target = 0.76, the Rntc = 10kΩ with b = 4300,
Rseries = 2610kΩ, and Rpar = 11kΩ, Rseqv = 1825Ω generates
a desired G1, close to the feature specified in Equation 20.
The actual G1 at +25°C is 0.769. For different G1 and NTC
thermistor preference, the design file to generate the proper
value of Rntc, Rseries, Rpar, and Rseqv is provided by Intersil.
Then, the individual resistors from each phase to the VSUM
node, labeled RS1 and RS2 in Figure 31, are then given by
Equation 14.
Rs = 2 ⋅ R seqv
(EQ. 14)
So, RS = 3650Ω. Once we know the attenuation of the RS and
Rn network, we can then determine the droop amplifier gain
required to achieve the load line. Setting Rdrp1 = 1k_1%,
then Rdrp2 is can be found using Equation 15:
2 ⋅ R droop
R drp2 = ⎛ ---------------------------------------------- – 1⎞ ⋅ R drp1
⎝ DCR ⋅ G1 ( 25°C )
⎠
20
Droop Impedance (RDROOP) = 0.002 (V/A) as per the AMD
specification, DCR = 0.0008Ω typical for a 0.36µH inductor,
Rdrp1 = 1kΩ and the attenuation gain (G1) = 0.77, Rdrp2 is
then:
2 ⋅ R droop
R drp2 = ⎛ ------------------------------------- – 1⎞ ⋅ 1kΩ = 5.62kΩ
⎝ 0.0008 ⋅ 0.769
⎠
(EQ. 16)
Note, we choose to ignore the RO resistors because they do
not add significant error.
These designed values in Rn network are very sensitive to
layout and coupling factor of the NTC to the inductor. As only
one NTC is required in this application, this NTC should be
placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should be go
directly to the inductor pads.
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
Rdrp2 to obtain the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 2mV/A load line should be adjusted by Rdrp2 based on
maximum current, not based on small current steps like 10A,
as the droop gain might vary between each 10A steps.
Basically, if the max current is 40A, the required droop
voltage is 84mV. The user should have 40A load current on
and look for 84mV droop. If the drop voltage is less than
84mV, for example, 80mV. the new value will be calculated
by:
84mV
R drp2 = ---------------- ( R drp1 + R drp2 ) – R drp1
80mV
(EQ. 17)
Do not let the mismatch get larger than 600Ω. To reduce the
mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate
factor. The appropriate factor in the example is
1404/853 = 1.65. In summary, the predicted load line with
the designed droop network parameters based on the
design tool is shown in Figure 33.
(EQ. 15)
FN6359.3
May 28, 2009
ISL6264
LOAD LINE (mV/A)
2.25
2.2
2.15
2.1
2.05
0
20
40
60
80
100
INDUCTOR TEMPERATURE (°C)
Dynamic Mode of Operation - Compensation
Parameters
FIGURE 33. LOAD LINE PERFORMANCE WITH NTC
THERMAL COMPENSATION
Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value. This could be
problematic if a load dump were to occur during this time.
This situation would cause the output voltage to rise above
the no load setpoint of the controller and could potentially
damage the CPU.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in Equation 18:
R n ⋅ RS EQV
L
------------- = ---------------------------------⋅ Cn
R n + RS EQV
DCR
(EQ. 18)
Solving for Cn, we now have Equation 19:
L
------------DCR
C n = ----------------------------------R n ⋅ RS EQV
---------------------------------R n + RS EQV
(EQ. 19)
Note, RO was neglected. As long as the inductor time
constant matches the Cn, Rn and RS time constants as given
above, the transient performance will be optimum. As in the
Static Droop Case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
example of L = 0.36 H with 0.8mΩ DCR, Cn is calculated as
shown in Equation 20:
0.36μH
-------------------0.0008
C n = ------------------------------------------------------------------- = 330nF
parallel ( 5.823k, 1.825k )
(EQ. 20)
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip (lower than the voltage required by the load line) and
slowly increases back to the steady state, the cap is too
small and vice versa. It is better to have the cap value a little
bigger to cover the tolerance of the inductor to prevent the
output voltage from going lower than the spec. This cap
21
needs to be a high grade cap like X7R with low tolerance.
There is another consideration in order to achieve better
time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those caps are only available in
small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10X to
reduce the capacitance by 10X. But attention has to be paid
in balancing the impedance of droop amplifier in this case.
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.0mV/A load line, the impedance
needs to be 2.0mΩ. The compensation design has to target
the output impedance of the controller to be 2.0mΩ. There is
a mathematical calculation file available to the user. The
power stage parameters such as L and Cs are needed as the
input to calculate the compensation component values.
Attention has to be paid to the input resistor to the FB pin. It
is better to keep this resistor at 1kΩ for the convenience of
OFFSET design.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6264 through the
matching of the voltages present on the ISEN pins. The
ISL6264 adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel's inductor. For
optimum performance, RL is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with RL to properly compensate the current balance circuit.
ISL6264 uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL6264 forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly equal. Take DCR current
sensing as example, two errors have to be added to find the
total current imbalance.
1. Mismatch of DCR: If the DCR has a 5% tolerance then
the resistors could mismatch by 10% worst case. If each
phase is carrying 20A then the phase currents mismatch
by 20A*10% = 2A.
2. Mismatch of phase voltages/offset voltage of ISEN pins.
The phase voltages are within 2mV of each other by
current balance circuit. The error current that results is
given by 2mV/DCR. If DCR = 1mΩ then the error is 2A.
FN6359.3
May 28, 2009
ISL6264
In the above example, the two errors add to 4A. For the two
phase DC/DC, the currents would be 22A in one phase and
18A in the other phase. In the above analysis, the current
balance can be calculated with 2A/20A = 10%. This is the
worst case calculation, for example, the actual tolerance of
two 10% DCRs is 10%*sqrt(2) = 7%.
Fault Protection - Overcurrent Fault Setting
As previously described, the Overcurrent protection of the
ISL6264 is related to the Droop voltage. Previously we have
calculated that the Droop Voltage = ILoad * Rdroop, where
Rdroop is the load line slope specified as 2mV/A in the AMD
specification. Knowing this relationship, the over current
protection threshold can be set up as a voltage Droop level.
Knowing this voltage droop level, one can program in the
appropriate drop across the Roc resistor. This voltage drop
will be referred to as Voc. Once the droop voltage is greater
than Voc, the PWM drives will turn off and PGOOD will go
low.
The selection of Roc is given in Equation 21. Assuming we
desire an overcurrent trip level (Ioc) of 55A, and knowing
from the Intel Specification that the load line slope (Rdroop) is
0.0021 (V/A), we can then calculate for Roc as shown in
Equation 21.
I OC ⋅ R droop
55 ⋅ 0.002
R OC = ---------------------------------- = -------------------------- = 11.5kΩ
–6
10μA
10 ⋅ 10
(EQ. 21)
Note, if the droop load line slope is not -0.002 (V/A) in the
application, the over current setpoint will differ from
predicted.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN6359.3
May 28, 2009
ISL6264
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X 4.5
6.00
36X 0.50
A
B
31
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
30
1
6.00
4 . 10 ± 0 . 15
21
10
0.15
(4X)
11
20
0.10 M C A B
TOP VIEW
40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
(
C
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
C
0 . 2 REF
5
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
23
FN6359.3
May 28, 2009
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