5 4 3 2 1 NOTES, UNLESS OTHERWISE SPECIFIED: D 1. RESISTANCE VALUES IN OHMS. 2. CAPACTITANCE VALUES IN MICROFARADS. 3. REFERENCE DESIGNATORS USED: D 4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED CIRCUITS THEY SHOULD BE PLACED NEAR. 5. NHET1xx means NHET1_[xx]. 6. OBSERVE THE LAYOUT NOTES IN SCHEMATIC. RevB Changes: SCHEMATIC CONTENTS 1. Changed JP1: In RevA, Y1 is connected to Pin2 of JP1. In RevB, Y1 is connected to Pin1. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 C B A Proprietary & Confidential TITLE SHEET MCU ADC MCU SPI and DCAN Transceivers MCU JTAG and OSC MCU NHET and GIO MCU Power and GND Sensors, LEDs, and Pushbutton JTAG Connector XD100V2 FTDI2232 XDS100V2 CPLD RESET Power Supply Power Input EXP P1 and EXP P2 EXP P3 4 B Texas Instruments Inc A Title RM42 HDK Size A Date: 5 C 3 Document Number TITLE Tuesday, August 14, 2012 2 Rev B Sheet 1 of 1 15 5 4 ADIN0 14 ADIN1 14 ADIN2 14 ADIN3 14 ADIN4 14 ADIN5 C 14 ADIN6 14 ADIN7 7,14 ADIN8 7,14 ADIN9 14 ADIN10 14 ADIN11 14 ADIN16 14 ADIN17 14 ADIN20 14 ADIN21 C2 NO-POP C3 NO-POP C4 NO-POP C5 NO-POP C6 NO-POP C7 NO-POP C8 D U1A R1 0 AD0 42 R3 0 AD1 49 AD2 51 R2 0 R5 0 AD3 52 R6 0 AD4 54 R7 0 AD5 55 R8 0 AD6 56 R9 0 AD7 43 R10 0 AD8 57 R13 0 AD9 48 R14 0 AD10 50 R16 0 R17 0 1 AD11 AD16 53 40 R18 0 AD17 41 R20 0 AD20 44 R21 0 AD21 45 ADIN0 ADIN1 ADEVT/NHET28# 58 R4 0 ADEVT_NHET28# 14,15 ADIN2 ADIN3 ADIN4 For probing ADC current ADIN5 C ADIN6 ADIN7 TP22 ADIN8 TP23 VCC_ADC ADIN9 ADIN10 ADREFHI 46 VCCAD 0.02 ADIN11 C46 ADIN16 0.1uF ADIN17 ADREFLO ADC Supply Voltage (VCCAD): 3.0V – 3.6V 1 14 C1 NO-POP 2 1 D NO-POP 3 R67 + C47 22uF 47 ADIN20 ADIN21 B B NO-POP C11 NO-POP C12 NO-POP C13 NO-POP C14 NO-POP C15 NO-POP C16 NO-POP C17 NO-POP C18 Corona MibADC: 144 paqkage: 24 Input Channels 100A paqkage: 16 Input Channels A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number MCU ADC Tuesday, August 14, 2012 Rev A Sheet 1 2 of 15 5 4 3 2 1 VCC_5V VCC_3V3 R34 360 R37 360 SCI1RX 9 SCI1TX R31 NP R32 10k 9 VCC_5V J1 U2 1 D R24 R25 R26 R29 R36 2 3 10K 10K 10K 10K 10K 4 U1C 14 3 4 14 4 14 14 14 73 93 27 39 SPI1CS0 SPI1CS1_EQEPS SPI1CS2_NHET20#_NHET19# SPI1CS3_NHET26# SPI1ENA_NHET30#_NHET23# SPI1SOMI SPI1SIMO SPI1CLK R38 R39 R40 68 66 65 67 33 33 33 SPI1CS0 SPI1CS1/EQEPS SPI1CS2 SPI1CS3/NHET26 SPI1ENA/NHET30# SPI1SOMI SPI1SIMO SPI1CLK LIN1TX_SCI1TX LIN1RX_SCI1RX CAN1TX CAN1RX 95 R61 94 NOP R56 62 NOP LIN1TX 15 C20 LIN1RX 15 0.1uF CAN1TX 63 TXD STB GND CANH VCC CANL RXD VIO 1 2 3 R41 62 8 7 D C19 CON3 6 5 VCC_3V3 R46 62 SN65HVDA541 4.7nF C21 0.1uF 15 CAN1RX 15 VCC_5V 7,14 SPI2CS0 7,14 SPI2SOMI SPI2SIMO SPI2CLK C7,14 7,14 3 3 3 23 R47 R48 R49 R35 SPI3CLK_EQEPA SPI3CS0_EQEPI SPI3ENA_EQEPB SPI3SIMO SPI3SOMI 15 15 33 33 33 33 R44 R45 33 33 69 70 71 36 38 37 35 34 SPI2CS0 SPI2SOMI SPI2SIMO SPI2CLK R51 CAN2TX 91 CAN2TX 15 R50 R52 10k C J2 CAN2RX 92 CAN2RX 15 U3 SPI3CLK/EQEPA SPI3CS0/EQEPI SPI3ENA/EQEPB SPI3SIMO SPI3SOMI 1 2 3 4 R42 NP VCC_5V R43 C23 TXD STB GND CANH VCC CANL RXD VIO 1 2 3 R53 62 8 7 C22 CON3 6 5 VCC_3V3 SN65HVDA541 R54 62 4.7nF C24 0.1uF 10K 0.1uF 10K 10K VCC_3V3 B B VCC_3V3 MibSPI1: Up to 4 chip selects, 1 enable C140 SPI2: Up to 4 chip selects, 1 enable 0.1uF SPI3: Up to 4 chip selects, 1 enable U43 16 3 SPI3CLK_EQEPA 3 SPI3CS0_EQEPI 3 SPI3ENA_EQEPB 3 A 8 SPI1CS1_EQEPS 4 7 9 12 1 EQEP_CTL 15 R149 2.2K VCC 1A 1B1 1B2 2B1 2B2 2 3 5 6 LIN: 1 SPI3CLK EQEPA SPI3CS0 EQEPI 15 DCAN: 2 15 15 15 2A 3A 4A 4B1 4B2 3B1 3B2 S /OE GND PAD 14 13 11 10 SPI1CS1 EQEPS SPI3ENA EQEPB 14 15 15 15 8 17 A SN74CBTLV3257RGYR Title RM42 HDK Size B Date: 5 4 3 2 Document Number MCU MibSPIs and DCAN Transceivers Tuesday, August 14, 2012 Rev A Sheet 1 3 of 15 5 4 S4 3 Is there nTRST issue on Corona RevA? Change C value based on the Cload of the crystal 1K R59 JUMPER_3PINS D TEST D 3 Y1 R55 NOP 2 JP1 Y3 24 OSCIN TEST TRSTn C25 18pF 14 Y3 16 MHz OSCIN 1K KELVIN_GND TCK 16 OSCOUT OSCOUT crystal socket 2 14 TDO RTCK 82 nERROR TDI TMS 15 C26 18pF DS6 R58 NOP 76 MCU_TRSTn 77 MCU_TDI 75 79 78 R86 0 80 R85 0 8,10 MCU_TDI 8,10 MCU_TMS 8,10 MCU_TCK 8,10 MCU_TDO 8,10 MCU_RTCK 8,10 nERROR nERROR 11,14 R57 NOP U1D 1 Y1 Socket R145 VCC_3V3 0 TP19 31 POR_RESETn PORRSTn ECLK 1 Push Button 1 1 R146 For LPO test VCC_3V3 2 84 ECLK 14 C C 81 WARM_RSTn RSTn TP2 1 8,10,11,14 3 FLTP1 FLTP1 4 VCC_3V3 FLTP2 VCC_3V3 1 TP18 C28 R144 10K U4 0.1uF 5 Vcc NC A 15 RSTn 4 Y GND 1 R63 0 2 REVB: 3 Changed JP1: In RevA, Y1 is connected to Pin2 of JP1. SN74LVC1G07DCK B nRESET output B 2 VCC_3V3 1 T1 MCU_TDI 3 IRLML6302 R64 100 A D1 1 A BLUE Title 2 RM42 HDK Size B Date: 5 4 3 2 Document Number MCU JTAG & OSC Tuesday, August 14, 2012 Rev B Sheet 1 4 of 15 5 4 3 2 1 D D U1B 15 15 7,15 7,15 7,15 15 7,15 7,15 C 1 2 5 8 GIOA0_SPI3CS3 GIOA1_SPI3CS2 GIOA2_SPI3CS1 GIOA3_SPI2CS3 9 10 12 18 GIOA4_SPI2CS2 GIOA5_EXTCLKIN GIOA6_SPI2CS1_NHET31 GIOA7_NHET29 GIOA0/SPI3CS3 GIOA1/SPI3CS2 GIOA2/SPI3CS1 GIOA3/SPI2CS3 GIOA4/SPI2CS2 GIOA5/EXTCLKIN GIOA6/SPI2CS1/NHET31 GIOA7/NHET29 19 22 25 26 74 83 89 90 97 98 NHET00 NHET02 NHET04 NHET06 NHET08 NHET10 NHET12 NHET14 NHET16 NHET18 11 NHET22 64 NHET24 NHET00 NHET02 NHET04 NHET06 NHET08 NHET10 NHET12 NHET14 NHET16 NHET18 15 15 15 15 15 15 15 15 15 15 NHET22 15 NHET24 15 C NHET: GPIO: 8 dedicated GIO pins 144 Package: 31 NHET channels 100A Package: 18 NHET channels B B A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number MCU NHET and GIO Tuesday, August 14, 2012 Rev A Sheet 1 5 of 15 5 4 3 2 1 Operating Conditions: Core Supply Voltage (VCC): 1.08V – 1.38V I/O Supply Voltage (VCCIO): 3.0V – 3.6 V ADC Supply Voltage (VCCAD): 3.0V – 3.6V Vdd_pgm (eFuse) is bonded to Vcc pad Vcc_sram: is bonded to Vcc pad Vnwa (SRAM): is also bounded to Vcc pad D TP11 R74 1 + TP12 0.02 + C94 22uF CORE_VCC 1 VCC_1V2 D C96 22uF C95 C29 C30 C31 C32 C33 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF IO_VCC U1E 13 21 30 32 61 88 99 C VCC VCC VCC_SRAM VNMA VCC VCC VCC + C34 22uF C35 C36 C37 C38 0.1uF 0.1uF 0.1uF 0.1uF C TP3 TP4 R65 0.02 1 1 VCC_3V3 IO_VCC + 6 28 60 85 C41 22uF Flash external pump voltage (3.3 V). This terminal is required for both Flash read and Flash program and erase operations. B 96 C43 VCCIO VCCIO VCCIO VCCIO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCCP 7 17 20 29 33 59 72 86 87 100 0.1uF B TP7 TP8 TP9 TP10 1 1 1 1 4 GND test points at the board's 4 corners A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number Rev A POWER and GND Tuesday, August 14, 2012 Sheet 1 6 of 15 5 4 3 2 VCC_3V3 4 Demo LEDs will be placed at 4 corners C48 R68 5,15 0.1uF R71 5,15 GIOA4_SPI2CS2 5,7,15 GIOA3_SPI2CS3 5,15 GIOA2_SPI3CS1 680 D2 1 2 D4 1 2 D5 1 2 D7 1 2 D R69 R72 Digikey No: 490-2430-1-ND At 25degree, R254=100k, at 80degree, R254 is around 1/10*100K=10K So no amplifier is needed 0603 2,14 680 GIOA6_SPI2CS1_NHET31 D Thermal Resistor 1 R75 680 680 ADIN8 C49 R73 100pF 100K C C VCC_3V3 VCC_3V3 C50 C97 3 0.1uF 0.1uF 2 SHIELD1 C51 B R76 4.99k 9 100pF R256 0 10 SHIELD2 ADIN9 J15 CD SHIELD3 2,14 12 11 U5 TEMT6000 1 Light Sensor Digikey NO: 751-1055-1-ND 1 2 3 4 5 6 7 8 D2-NC D3-CD CMD-MOSI VDD CLK VSS D0-MISO D1-NC SPI2CS0 SPI2SIMO 3,14 3,14 SPI2CLK 3,14 SPI2SOMI MicroSD Slot GIOA3_SPI2CS3 VCC_3V3 B 3,14 5,7,15 CD is the Right-Bottom Leg (top view) R77 10K S1 R78 A 5,15 0 A GIOA7_NHET29 Push Button This push button can be used for bootloader ForceUpdate Title RM42 HDK Size B Date: 5 4 3 2 Document Number SENSOR, LED, PB Tuesday, August 14, 2012 Rev A Sheet 1 7 of 15 5 4 D 3 2 XDS100_TRSTn XDS100_TDI XDS100_TMS XDS100_TCK XDS100_RTCK XDS100_TDO VCC_3V3 VCC_3V3 R80 0 J3 R79 10k 2 4 6 8 10 12 14 16 18 20 JTAG_SELn VCC_3V3 C52 0.1uF R148 R147 1K 1K VSupply VTRef GND TRSTn GND TDI GND TMS GND TCK GND RTCK GND TDO GND SRSTn GND DBGREQ GND DBGACK 1 3 5 7 9 11 13 15 17 19 R81 R82 R83 R84 0 0 0 0 R87 0 MCU_TRSTn MCU_TDI MCU_TMS MCU_TCK MCU_RTCK MCU_TDO JTAG_RESETn 1 4,10 4,10 4,10 4,10 4,10 4,10 D 4,10 4,10 4,10 4,10 4,10 4,10 4,10,11,14 ARM_20PIN_JTAG S5 C ARM-JTAG 1 2 1 2 C 4 TI-JTAG 3 EQEP_CTL 3 DIP_SWITCH_2 R88 2.2K S5: default is OFF VCC_3V3 VCC_3V3 VCC_3V3 C53 B JTAG_SELn C54 0.1uF J5 2 4 6 8 10 12 14 16 18 20 TRST TDIS KEY GND GND GND EMU1 GND EMU3 GND U6 TMS TDI VTRef TDO RTCK TCK EMU0 SYSRSTn EMU2 EMU4 1 3 5 7 9 11 13 15 17 19 R92 R93 R94 10K 10K 10K JTAG_SELn 0.1uF 2 1 4 T_DIS 10 B SN74AHC1G14 220 1 R91 10k 5 R90 10k 3 R89 10k JTAG_DIS TI_20PIN_JTAG 2 DS1 20 PIN ARM JTAG INTERFACE JTAG_SELn = HIGH JTAG_SELn = LOW --> XDS100 --> ARM or TI JTAG A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number JTAG & MIPI Connectors Tuesday, August 14, 2012 Rev A Sheet 1 8 of 15 5 4 3 2 VCCUSB VCC_3V3XDS U8 5 0.1uF 4 D NC EN K1 TPS73433 C59 2 NR C60 GND C56 1 OUT GNDP C55 22uF IN C58 0.1uF 0.1uF C61 0.1uF C57 D 0.1uF 3 6 VCCUSB + 1 VCC_1V8XDS 0.01uF VCC_3V3XDS Ferrite Bead: 240-1018-1 VCCUSB L1 C67 5 IO2 2 3 4 7 8 VREGOUT 20 31 42 56 VCCIO VCCIO VCCIO VCCIO 12 37 64 VCORE VCORE VCORE 4 1.8V Output 1 VREGIN 9 4 50 VCC_1V8XDS VPLL VCC_3V3XDS USBDM U10 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 16 17 18 19 21 22 23 24 FTDI_TCK FTDI_TDI FTDI_TDO FTDI_TMS GPIOL0 GPIOL1 GPIOL2 GPIOL3 10 10 10 10 10 10 10 10 VCC_3V3XDS C USBDP R98 R99 R100R96 5 6 REF VCC_3V3XDS R101 0.1uFFerrite 4.7K 14 VCC_3V3XDS 63 R102 R103 R104 62 61 4.7K B 8 7 6 5 U11 VCC NC ORG GND CS SK DIN DOUT 4.7K 4.7K 1 2 3 4 R106 RESET# EECS BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 EECLK EEDATA 2.2K 2 93LC56C-I/SN 3 BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 XTIN XTOUT 2 C70 A XTO GND GND 3 4 ABM8G-12.000MHZ-B4Y-T 27pF TEST GND GND GND GND GND GND GND GND XTI 10 1 13 1 5 11 15 25 35 47 51 Y2 AGND PWREN# SUSPEND 38 39 40 41 43 44 45 46 GPIOH0 GPIOH1 PWR_DET GPIOH3 10 10 1K 10 1K 1K 1K 10 SPARE0 SPARE1 SPARE2 SPARE3 SCI1RX SCI1TX R105 48 52 53 54 55 57 58 59 60 36 3 VCC_3V3XDS 3 TXB 0 RXB LED D8 R107 R108 B LED D9 360 360 PWRENn 10 10 10 10 1 12K, 1% 2 R97 C69 26 27 28 29 30 32 33 34 1 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 USBMINI_B L3 0.1uF 2 SHIELD1 DSHIELD2 D+ SHIELD3 ID SHIELD4 USBVSS C66 0.1uF 0.1uF 49 USBVDD C65 0.1uF NC.2 TPD2E001 6 7 8 9 C64 0.1uF 4.7uF J4 C 4.7uF C68 GND 2 IO1 VCC_1V8XDS C62 VPHY 3 VCC_3V3XDS Ferrite Ferrite C63 VCC U9 1 L2 CPLD_TCK CPLD_TDI 10 10 CPLD_TDO CPLD_TMS 10 10 10 SUSPENDn 10 FT2232HL C71 A 27pF Title RM42 HDK Size B Date: 5 4 3 2 Document Number XDS100V2 FTDI2232 Tuesday, August 14, 2012 Rev A Sheet 1 9 of 15 5 4 SUSPENDn GPIOH3 PWR_DET PWRENn GPIOH1 GPIOH0 H6 H8 CPLD_TDI CPLD_TMS CPLD_TCK D1 A8 D3 VCCAUX IO21_4 NC10 F1 E3 E1 K1 J1 G3 H1 F3 G1 IO12_12 J10 K9 K10 K6 K7 NC2 NC3 TDO IO21_12 H7 K8 H10 G10 C VCCIO2 GND XC2C32A CP56 TDI TMS TCK XC2C32A_CPG56 NC7 A5 D8 VCC_1V8XDS VCC_3V3 C1 A3 A2 B1 A1 C4 C5 R110 0 R111 R112 R113 R114 0 0 0 0 XDS100_TMS 4,8 XDS100_TRSTn XDS100_TDI T_DIS XDS100_TDO C6 C7 4,8 4,8 D11 8 D12 4,8 VCCIO2 A6 CPLD_TDO 9 C8 A9 C R115 R116 9 9 9 9 9 9 NC5 NC6 FTDI_TDO NC9 NC8 E10 A7 9 0.1uF 9 9 9 VCCIO1 IO21_16 IO21_15 IO21_14 IO21_13 C72 1 D IO21_5 IO21_6 IO21_7 IO21_8 IO21_9 IO21_10 IO21_11 GND I_2 GPIOL0 FTDI_TMS NC1 IO12_7 IO12_8 IO12_9 GND IO12_10 IO12_11 E8 C10 B10 A10 9 K4 K2 K3 H3 H4 K5 H5 IO12_16 9 GPIOL3 GPIOL2 GPIOL1 F8 D10 LED 9 9 9 IO21_1 IO21_2 IO21_3 2 VCC18 1 NC12 NC11 360 IO12_6 IO12_5 IO12_4 IO12_3 IO12_2 IO12_1 D10 R109 VCC_3V3XDS C3 A4 U12 VCC_3V3XDS D 2 SPARE0 SPARE1 SPARE2 SPARE3 G8 9 9 9 F10 9 9 NC4 IO12_13 IO12_14 IO12_15 9 3 VCC_3V3XDS 360 0 XDS100_TCK XDS_JTAG_RESETn 4,8 4,8,11,14 FTDI_TDI FTDI_TCK 1 TP17 SHDNn R117 0 XDS100_RTCK 4,8 VCC_1V8XDS B B R118 C73 0.1uF 22 VCC_3V3 This is JTAG PD power. We pull PD to VCC_3V3 R119 VCC_3V3XDS U13 PWGOOD 5.1K 4 2 1 R121 OUT R120 V+ GND SHDNn IN+ VCC_3V3XDS IN- 6 5 SHDNn 120K 3 LMV341IDCKR R122 C74 120K A 0.1uF A 120K Title RM42 HDK Size B Date: 5 4 3 2 Document Number XDS100V2 CPLD Tuesday, August 14, 2012 Rev A Sheet 1 10 of 15 5 4 3 2 1 VCC_3V3 R123 10k S2 D R124 22 WARM_RSTn D 4,8,10,14 WARM_RESET Button C75 1uF 4,8,10,14 JTAG_RESETn 4,8,10,14 XDS_JTAG_RESETn JTAG System Reset goes to warm reset instead of nPORRST VCC_3V3 VCC_3V3 VCC_3V3 C76 R129 R125 U14 25.5K 5 C 4 R130 10k 3 C77 NO-POP 0.1uF SENSE1 VDD CT RESET MR GND 6 C 2.2K 1 0 R127 POR_RESETn 4,14 2 TPS3808G09DBVR If VCC_3.3V below 3.0V --> RESET If VCC_1.2V below 1.0V --> RESET VCC_1V2 VCC_3V3 VCC_3V3 B B C145 R285 U34 5 2.2K VCC_3V3 R286 10k 4 C146 NO-POP R131 10k S3 22 3 0.1uF SENSE1 VDD CT RESET MR GND 6 R284 10k 1 2 TPS3808G09DBVR SENSE THRESHOLD FOR TPS3808G09 IS 0.840 VOLTS R132 POR_RESET Button C78 1uF A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number RESET Tuesday, August 14, 2012 Rev A Sheet 1 11 of 15 5 4 D 6 R133 1K 5 OUT NC3 NC1 NC2 NR/FB EN GND 1 VCC_ADC + C80 10uF C79 3 D 220 560 1uF 4 C82 L4 L5 HZ0603B112R-10 Choke R135 10nF 3V3 9 TPS73733QDRBRQ1 R134 VCC_3V3 2 PAD + C81 10uF IN VCC_5V VCC_3V3 1 7 1 VCC_3V3 U15 8 2 1 VCC_5V 3 V5.0 DS3 2 2 DS2 C C VCC_5V VCC_1V2 VCC_3V3 U35 8 1K 7 R294 C148 + 10uF 5 NC3 NC1 NC2 NR/FB EN GND 1 2 C149 3 R291 0 C151 C150 + 10uF 0.1uF 4 1uF DS5 3 9 VCC_1V2 6 OUT PAD 1V2 R290 1k IN R295 B 1 B R293 NOP NOP 2 1K TPS73701DRB R292 Q1 FJV3109R Vout = (1+R1/R2)*1.204 For Vout=1.2V, R291 shorted, and R293 Open For Vout=1.5, R291=23.2Kohms, and R293=95.3Kohms R281: ERJ-2RKF2322X A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number Power Supply Tuesday, August 14, 2012 Rev A Sheet 1 12 of 15 5 4 3 VCC_12V EXP_12V L6 2 1 Accept 12V from daughter card HI1806N910R-10 L7 D D HI1806N910R-10 12V Input Connect at pin 10 P1 DC8 1 3 2 F1 2 C84 C83 R138 + 5V @ 3Amp Max 3.3 sq in AGND, min thermal pad 5.6K C85 1uF 2 0.01uF C86 U16 5 6 7 12 V12.0 DS4 L8 2 1 C 5.90K, 1% AGND 1 22uF,50V R137 NP R136 HI1806N910R-10 + C91 C89 22uF,25V 3 11 VIN2 VIN1 UVLO PGND1 AGND COMP VSENSE PWRGD BOOT 17 0.1uF RT SYNC ENA VBIAS PH1 PH2 10 8 9 4 16 10pF C87 R139 7.5K, 1% R140 4.64K, 1% 1 4700pF VCC_5V TP15 C88 L10 0.1uF 14 15 L9 10 uH C HI1806N910R-10 C92 + LSG TP16 1 PolySwitch D13 SMCJ18A POWERPAD 1 C93 + C90 13 R141 0.1uF 220uF 22uF,25V D14 TPS54350PWP 1K, 1% MURS120T3 R142 49.9K R143 VCCUSB 10k 5uA * 10k = 0.05V B S B Circuitry for using either 5V USB power or 12V power U17 1 2 3 G 4 VCC_5V From 12V OFF From 12V OFF ON From VBUS 3 ON ON 1 ON G1 D1.1 S2 D2.2 G2 D2.1 8 7 6 5 QS8J1 Anode Cathode NC VBUS_5V D1.2 VCC_5V D15 MMBZ5233BLT1G 2 12V S1 A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number Power Input Tuesday, August 14, 2012 Rev A Sheet 1 13 of 15 5 4 3 2 EXP_12V 1 EXP_12V J9 D 3 3 3 3 SPI1ENA_NHET30#_NHET23# SPI1CS1 SPI1CS3_NHET26# SPI1SIMO 2 2 2 2 ADIN1 ADIN3 ADIN5 ADIN7 2 ADIN17 2 ADIN21 2,7 2 ADIN9 ADIN11 C 2,15 ADEVT_NHET28# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 J10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 4 4,8,10,11 SPI1CLK 3 SPI1CS0 3 SPI1CS2_NHET20#_NHET19# SPI1SOMI 3 ADIN0 ADIN2 ADIN4 ADIN6 ECLK WARM_RSTn 3 2 2 2 2 ADIN16 2 ADIN20 2 ADIN8 ADIN10 2,7 2 POR_RESETn 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 4,11 3,7 3,7 3,7 SPI2SOMI SPI2SIMO SPI2CS0 EXP_P1 D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 nERROR 4 C SPI2CLK 3,7 EXP_P2 B B A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number Expansion Connector 1 Tuesday, August 14, 2012 Rev A Sheet 1 14 of 15 5 4 3 2 1 D D EXP_12V J11 3 3 3 LIN1RX CAN1RX CAN2RX C 5,15 5,7 5 5,7,15 GIOA1_SPI3CS2 GIOA3_SPI2CS3 GIOA5_EXTCLKIN GIOA7_NHET29 3 3 3 3 B EQEPA EQEPI EQEPB EQEPS 5,7,15 5,7,15 GIOA7_NHET29 GIOA6_SPI2CS1_NHET31 5,15 3 5,7,15 3 GIOA0_SPI3CS3 SPI3SIMO GIOA2_SPI3CS1 SPI3ENA 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 LIN1TX CAN1TX CAN2TX 3 3 3 C GIOA0_SPI3CS3 GIOA2_SPI3CS1 GIOA4_SPI2CS2 GIOA6_SPI2CS1_NHET31 5,15 5,7,15 5,7 5,7,15 NHET00 NHET02 NHET04 NHET06 NHET08 NHET10 NHET12 NHET14 NHET16 NHET18 5 5 5 5 5 5 5 5 5 5 NHET22 NHET24 5 5 B ADEVT_NHET28# RSTn GIOA1_SPI3CS2 SPI3SOMI SPI3CS0 SPI3CLK 2,14 4 5,15 3 3 3 EXP P3 A A Title RM42 HDK Size B Date: 5 4 3 2 Document Number Expansion Connector 2 Tuesday, August 14, 2012 Rev A Sheet 1 15 of 15