DATASHEET

ISL59837
®
Data Sheet
March 5, 2007
200MHz Single Supply Video Driver With
Charge Pump and Power Down
The ISL59837 is a revolutionary device that allows true singlesupply operation of video amplifiers. Designed for systems
requiring output swing below ground but lacking a negative
power supply, the ISL59837 generates the required negative
rail internally from a +3.3V power supply. This allows for
DC-accurate coupling of video onto a 75Ω double-terminated
line. The buffers have an integrated 6dB, eliminating the need
for external gain-setting resistors. An external reference
voltage can be applied to the REF pin to shift the analog video
level down by the desired amount. The charge pump and
amplifiers can be placed in a power down mode, consuming
less than 1mA of current.
FN6335.1
Features
• Triple single-supply buffer
• Generates negative rail from from single +3.3V supply
• No output DC blocking capacitor needed
• 200MHz -3dB bandwidth
• 50MHz 0.1dB bandwidth
• Fixed gain of 2 output buffer
• Charge pump power down function (0.1mA typical)
• Outputs are high impedance in power-down mode
• Amplifier enable/disable function control
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
Applications
PART NUMBER
(Note)
PART
TAPE &
MARKING REEL
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL59837IAZ
59837 IAZ
-
16 Ld QSOP MDP0040
ISL59837IAZ-T7 59837 IAZ
7”
16 Ld QSOP MDP0040
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Driving video
Pinout
ISL59837
(16 LD QSOP)
TOP VIEW
RIN 1
16 ROUT
GIN 2
15 GOUT
BIN 3
14 BOUT
REF 4
13 VCC
VEE 5
12 EN
GND 6
11 VCC
VEEOUT 7
DGND 8
1
10 PD
9 DVCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59837
Absolute Maximum Ratings
Thermal Information
VCC, Supply Voltage between VS and GND . . . . . . . . . . . . . . . . .5V
VIN, VREF . . . . . . . . . . . . . . . . . . . . . . . . . .VCC + 0.3V, VEE - 0.3V
Voltage between VIN and VREF . . . . . . . . . . . . . . . . . . . . . . . . . .±2V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
AC Electrical Specifications
PARAMETER
BW - 3dB
VCC = DVCC = +3.3V, REF = GND, TA = +25°C, RL = 150Ω, unless otherwise specified.
DESCRIPTION
3dB Bandwidth
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT = 200mVPP
200
MHz
VOUT = 2VPP
100
MHz
50
MHz
BW 0.1dB
0.1dB Bandwidth
VOUT = 2VPP
SR
Slew Rate
VIN = 2VPP
dG
Differential Gain
0.07
%
dP
Differential Phase
0.06
°
XT
Hostile Crosstalk
6MHz
-90
dB
I
Input to Output Isolation
6MHz
-70
dB
VN
Input Noise Voltage
20
nV/√Hz
fCP
Charge Pump Switching Frequency
168
MHz
Load Reg
VEE Load Regulation
VRIPPLE
Output Amp Ripple Voltage
500
IEE = 0mA to 10mA
9
With Bead Core to DVCC
DC Electrical Specifications
PARAMETER
V/µs
30
mV
30
mV
10
mV
VCC = DVCC = +3.3V, REF = GND, TA = +25°C, RL = 150Ω, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
UNIT
3.6
V
1.5
%
V+
Supply Range
VG%
Gain Error
RL = 150Ω, VOUT = -1V to +2.5V
ΔG
Gain Matching
RL = 150Ω
0.5
IIN
Analog Input Leakage Current
VIN = 0V to 1.5V
±0.1
±1
µA
VOS
Output Offset Voltage
VREF = 0
-25
7
+25
mV
VOUT+
Maximum Output Voltage
RL = 75Ω
2.4
2.5
V
RL = 150Ω
2.7
2.9
V
VOUT-
3.0
MAX
Minimum Output Voltage
RL = 75Ω
-1
V
RL = 150Ω
-1.2
V
IOUT +
Output Current
RL = 10Ω, VIN = 1.2V
IOUT -
Output Current
RL = 10Ω, VIN = -0.3V
-40
ZOUT
Disabled Output Impedance
EN = 3.3V and/or PD = 3.3V
(Amp Disabled)
500
IREF
Reference Input Leakage Current
1
2.3
PSRR
Power Supply Rejection Ratio
50
62
2
%
50
80
mA
-18
mA
kΩ
3.5
µA
dB
FN6335.1
March 5, 2007
ISL59837
DC Electrical Specifications
PARAMETER
IS
VCC = DVCC = +3.3V, REF = GND, TA = +25°C, RL = 150Ω, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
Supply Current
IS_PD
Power Down Supply Current
MIN
TYP
MAX
UNIT
EN = PD = GND (Amp Enabled)
97
130
mA
EN = 3.3V (Amp Disabled)
60
90
mA
EN = PD = 3.3V
0.1
1
mA
Pin Descriptions
PIN NUMBER
PIN NAME
1
RIN
PIN FUNCTION
EQUIVALENT CIRCUIT
Analog input
VCC
VEE
CIRCUIT 1
2
GIN
Analog input
Reference Circuit 1
3
BIN
Analog input
Reference Circuit 1
4
REF
Reference input
High impedance input controlling
offset of amplifiers
RIN
GIN
BIN
VCC
3
x1
REF
ROUT
GOUT
BOUT
+
-
VEE
CIRCUIT 2
5
VEE
Chip substrate (negative power supply
for amplifiers)
VCC
VEE OUT
- +
DVCC
VEE
CHARGE
PUMP
DGND
CIRCUIT 3
6
GND
Analog ground
7
VEE OUT
Charge pump output
Reference Circuit 3
8
DGND
Charge pump ground
Reference Circuit 3
9
DVCC
Charge pump supply voltage
Reference Circuit 3
10
PD
Power-down Input
Low: Normal Operation
High: Power-down Charge Pump and
Amplifiers
VCC
VEE
CIRCUIT 4
3
FN6335.1
March 5, 2007
ISL59837
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
11, 13
VCC
12
EN
14
BOUT
PIN FUNCTION
EQUIVALENT CIRCUIT
Positive power supply
Reference Circuit 4
Chip Enable
Low: Normal Operation
High: Power Down Amplifiers
Analog output
VCC
VEE
CIRCUIT 5
15
GOUT
Analog output
Reference Circuit 5
16
ROUT
Analog output
Reference Circuit 5
Typical Performance Curves
2
5
AV = +2
CL = 0pF
AV = +2
RL = 500Ω
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
1kΩ
0
500Ω
-1
-2
150Ω
75Ω
-3
1M
10M
100M
3
2.2pF
1
0pF
-1
-3
-5
100k
1G
100M
1G
FREQUENCY (Hz)
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD
5
300
AV = +2
CL = 0pF
RL = 500Ω
0
-5
-10
-15
-20
-25
AV = +2
RL = 500Ω
GAIN ROLL-OFF (MHz)
NORMALIZED OUTPUT (dB)
10M
1M
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD
240
-3dB ROLL-OFF
180
120
60
-0.1dB ROLL-OFF
-30
-35
1M
9pF
4.7pF
100M
200M
300M
400M
500M
FREQUENCY (Hz)
FIGURE 3. VREF PIN OUTPUT FREQUENCY RESPONSE
4
0
2.25
2.80
3.35
3.90
4.45
5.00
SUPPLY VOLTAGE (V)
FIGURE 4. GAIN ROLL-OFF vs FREQUENCY
FN6335.1
March 5, 2007
ISL59837
Typical Performance Curves (Continued)
-30
-20
AV = +2
RL = 500Ω
-40
-30
-40
ISOLATION (dB)
CROSS TALK (dB)
-50
AV = +2
RL = 500Ω
-60
ENABLED
-70
-80
DISABLED
-90
-50
ENABLED
-60
-70
DISABLED
-80
-100
-90
-110
-120
100k
1M
100M
10M
-100
100k
1G
10M
1M
FREQUENCY (Hz)
FIGURE 6. INPUT TO OUTPUT ISOLATION vs FREQUENCY
120
200
AV = +2
RL = 500Ω
-3dB
160
BANDWIDTH (MHz)
SUPPLY CURRENT (mA)
1G
FREQUENCY (Hz)
FIGURE 5. CROSS TALK CHANNEL TO CHANNEL (TYPICAL)
100
100M
80
60
40
AV = +2
RL = 500Ω
120
80
40
20
-0.1dB
0
1.0
1.5
2.5
2.0
3.0
0
27
3.5
SUPPLY VOLTAGE (V)
68
47.5
88.5
109
129.5
150
TEMPERATURE (°C)
FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 8. BANDWIDTH vs TEMPERATURE
95
100
10
90
IMPEDANCE (Ω)
SUPPLY CURRENT (mA)
AV = +2
RL = 500Ω
85
0.1
80
75
27
1
55.6
84.2
112.8
141.4
170
TEMPERATURE (°C)
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
5
0.01
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY
FN6335.1
March 5, 2007
ISL59837
Typical Performance Curves (Continued)
1k
0
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
PSRR (dB)
VCC = DVCC = 3.3V
-10 VAC = 100mVP-P
RL = 150Ω
-20
-30
-40
-50
-60
100
eN
10
IN+
1
IN-
-70
-80
10k
100k
1M
0.1
10
10M
100
-40
10M
-40
THD
-50
-50
THD (dBc)
HARMONIC DISTORTION (dBc)
1M
-30
-60
2ND HD
-70
THD
FIN = 10MHz
-60
-70
3RD HD
THD
FIN = 1MHz
-80
-90
10M
20M
30M
-90
0.5
40M
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (VP-P)
FUNDAMENTAL FREQUENCY (Hz)
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY
FIGURE 14. THD vs OUTPUT VOLTAGE
0
0
DIFFERENTIAL
PHASE (°)
DIFFERENTIAL
GAIN (%)
100k
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
-30
-100
0M
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
-80
1k
-0.02
-0.04
-0.02
-0.04
-0.06
-0.06
-0.08
-0.08
IRE
FIGURE 15. DIFFERENTIAL GAIN
6
IRE
FIGURE 16. DIFFERENTIAL PHASE
FN6335.1
March 5, 2007
ISL59837
VOLTS (500mV/DIV)
VOLTS (500mV/DIV)
Typical Performance Curves (Continued)
TIME (200ns/DIV)
TIME (200ns/DIV)
FIGURE 18. ENABLE TIME
VOLTS (50mV/DIV)
VOLTS (500mV/DIV)
FIGURE 17. DISABLE TIME
TIME (10ns/DIV)
FIGURE 19. SMALL SIGNAL RISE AND FALL TIME
TIME (10ns/DIV)
FIGURE 20. LARGE SIGNAL RISE AND FALL TIMES
0
3.25
-10
OUTPUT RANGE (V)
NOISE (dBV)
-20
-30
-40
-50
-60
-70
3.00
2.75
-80
-90
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (Hz)
FIGURE 21. NOISE FLOOR WITH CHARGE PUMP HARMONICS
7
2.50
50
AV = +2
CL = 3.9pF
250
450
650
850
1050
LOAD RESISTANCE (Ω)
FIGURE 22. MAXIMUM OUTPUT MAGNITUDE vs LOAD
RESISTANCE
FN6335.1
March 5, 2007
ISL59837
Typical Performance Curves (Continued)
1.6
BACKDRIVE ACROSS 5Ω RESISTOR
TYPICAL CHANNEL
AV = +2
RL = 500Ω
CL = 3.9pF
1.2
1.2
PEAKING (dB)
BACKDRIVE CURRENT (mA)
1.6
0.8
0.4
0.8
0.4
0
0
1
2
3
4
0
2.2
5
2.4
2.6
BACKDRIVE VOLTAGE (V)
3.0
3.2
3.4
3.6
3.8
4.0
SUPPLY VOLTAGE (V)
FIGURE 23. BACKDRIVE VOLTAGE vs CURRENT
FIGURE 24. PEAKING vs SUPPLY VOLTAGE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.8
1.6
1.2
POWER DISSIPATION (W)
POWER DISSIPATION (W)
2.8
1.0
791mW
0.8
QS
OP
16
A=
+1
58
°C
/W
θJ
0.6
0.4
0.2
1.4
1.116W
1.2
θJ
1.0
QS
A=
+
OP
11
0.8
0.6
16
2°C
/W
0.4
0.2
0
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
8
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6335.1
March 5, 2007
ISL59837
Block Diagram
VCC
RIN
+
6dB
ROUT
6dB
GOUT
6dB
BOUT
REF
GIN
+
-
BIN
+
DVCC
CHARGE
PUMP
VEE-OUT
VEE
VOUT = 2VIN - VREFERENCE
Demo Board Schematic
RED_IN
R1
75Ω
RED_OUT
GREEN_IN
R2
75Ω
BLUE_IN
C4
0.1µF
R3
75Ω
VCC
R4
R8
499Ω 1kΩ
OFFSET
CONTROL
9
C2
0.1µF
1 RIN
ROUT 16
2 GIN
GOUT 15
3 BIN
BOUT 14
4 REF
VCC 13
5 VEE
EN 12
6 GND
VCC 11
7 VEEOUT
8 DGND
75Ω
R5
75Ω
R6
75Ω
GREEN_OUT
VCC
C3
0.1µF
BLUE_OUT
VCC
2
PD 10
DVCC 9
R4
C5
0.1µF
1
DISABLE
3
ENABLE
Option: Panasonic 120Ω Bead
EXC3BP121H
Lower Amp output noise from charge pump
FN6335.1
March 5, 2007
ISL59837 + DC-Restore Solution
1 IN1
IN2 16
2 COM1
COM2 15
3 NC1
NC2 14
10
4 V-
R7
2kΩ
V+ 13
5 GND
NC 12
(No Connect)
6 NC4
NC3 11
7 COM4
COM3 10
YO
R1
75Ω
R2
75Ω
IN3 9
ISL43140
C4
0.1µF
C5
0.1µF
C6
0.1µF
Pr
C7
0.1µF
R3
75Ω
R9
2kΩ
CN = Option for lower
charge pump noise
R10
2kΩ
1 RIN
ROUT 16
2 GIN
GOUT 15
3 BIN
BOUT 14
4 REF
VCC 13
5 VEE
EN 12
6 GND
VCC 11
R4
75Ω
R5
75Ω
R6
75Ω
C1
0.1µF
ENABLE
2
1
VCC
C11
0.1µF
OFFSET
CONTROL
NC 10
0.1µF
8 DGND
DVCC 9
ISL59830
C4
0.1µF
1 COMP
VDD 8
2 COMP
OUT 7
SYNC OUT
VIDEO IN
3 VSYNC
OUT
C10
0.1µF
4 GND
RESET 6
BACK
PORCH 5
OUT
EL1881
3
C14
20pF
VCC
YO
Pb
Pr
VCC
+ C16
VCC
1µF
GND
C15
Option: Panasonic 120Ω Bead
EXC3BP121H
Lower Amp output noise from charge pump
C8
0.1µF
C9
0.1µF
C13
20pF
VCC
VEE (-1.6V)
7 VEEOUT
C12
20pF
R13
681kΩ
ISL59837
Pb
8 IN4
FN6335.1
March 5, 2007
ISL59837
Description of Operation and Application
Information
Theory Of Operation
The ISL59837 is a highly practical and robust marriage of
three high bandwidth, high speed, low power, rail-to-rail
voltage feedback amplifiers with a charge pump to provide a
negative rail without an additional power supply. Designed to
operate with a single supply voltage range from 0V to 3.3V,
the ISL59837 eliminates the need for a split supply with the
incorporation of a charge pump capable of generating a
bottom rail as much as 1.6V below ground for a 4.9V range
on a single 3.3V supply. This performance is ideal for NTSC
video with its negative-going sync pulses.
THE AMPLIFIER
The ISL59837 fabricated on a di-electrically isolated high
speed 5V Bi-CMOS process with 4GHz PNPs and NPN
transistor exceeding 20GHz - perfect for low distortion, low
power demand and high frequency circuits. While the
ISL59837 utilizes somewhat standard voltage mode
feedback topologies, there are many non-standard analog
features providing its outstanding bandwidth, rail-to-rail
operation, and output drive capabilities. The input signal
initially passes through a folded cascode, a topology
providing enhanced frequency response by essentially fixing
the base collector voltage at the junction of the input and
gain stage. The collector of each input device looks directly
into an emitter that is tied closely to ground through a
resistor and biased with a very stable DC source. Since the
voltage of this collector is "locked stable," the effective
bandwidth limiting of the Miller capacitance is greatly
reduced. The signal is then passed through a second fullyrealized differential gain stage and finally through a
proprietary common emitter output stage for improved
rail-to-rail output performance. The result is a highly-stable,
IN+
low distortion, low power, and high frequency amplifier
capable of driving moderately capacitive loads with near
rail-to-rail performance.
INPUT OUTPUT RANGE
The three amplifier channels have an input common mode
voltage range from 0.15V below the bottom rail to within
100mV of the positive supply, VS+ pin (Note: bottom rail is
established by the charge pump at negative one half the
positive supply). As the input signal moves outside the
specified range, the output signal will exhibit increasingly
higher levels of harmonic distortion. And of course, as load
resistance becomes lower, the current drive capability of the
device will be challenged and its ability to drive close to each
rail is reduced. For instance, with a load resistance of 1kΩ
the output swing is within 100mV of the rails, while a load
resistance of 150Ω limits the output swing to within around
300mV of the rails.
AMPLIFIER OUTPUT IMPEDANCE
To achieve near rail-to-rail performance, the output stage of
the ISL59837 uses transistors in the common emitter
configuration, typically producing higher output impedance
than the standard emitter follower output stage. The
exceptionally high open loop gain of the ISL59837 and local
feedback reduces output impedance to less than 2Ω at low
frequency. However, since output impedance of the device is
exponentially modulated by the magnitude of the open loop
gain, output impedance increases with frequency as the
open loop gain decreases with frequency. This inductive-like
effect of the output impedance is countered in the ISL59837
with proprietary output stage topology, keeping the output
impedance low over a wide frequency range and making it
possible to easily and effectively drive relatively heavy
capacitive loads (see Figure 10).
INOUT
BIAS
FIGURE 27. SIMPLIFIED SCHEMATIC
11
FN6335.1
March 5, 2007
ISL59837
THE CHARGE PUMP
INPUT, OUTPUT AND SUPPLY VOLTAGE RANGE
The ISL59837 charge pump provides a bottom rail up to
1.6V below ground while operating on a 0V to 3.3V power
supply. The charge pump is internally regulated to one-half
the potential of the positive supply. This internal multi-phase
charge pump is driven by a 110MHz differential ring
oscillator driving a series of inverters and charge storage
circuitry. Each series inverter charges and places parallel
adjoining charge circuitry slightly out of phase with the
immediately preceding block. This generates a negative rail
of about -1.6V with a low amplitude ripple voltage from the
charge pump action. Some of this ripple is coupled into the
output signals at a very low amplitude, as seen in Figure 21.
The ripple on the outputs is typically well below the noise
floor of the signal.
The ISL59837 is designed to operate with a single supply
voltage range of from 0V to 3.3V. The need for a split supply
has been eliminated with the incorporation of a charge pump
capable of generating a bottom rail as much as 1.6V below
ground, for a 4.9V range on a single 3.3V supply. This
performance is ideal for NTSC video with its negative-going
sync pulses.
There are two ways to further reduce the output supply
noise:
• Add a 120Ω bead in series between VCC and DVCC. This
reduces the coupling between the charge pump and the
analog amplifier supplies.
• Add a 20pF capacitor between the back load 75Ω resistor
and ground (see “ISL59837 + DC-Restore Solution” on
page 10). This will attenuate frequencies above 100MHz.
The system operates at sufficiently high frequencies that any
related charge pump noise is far beyond standard video
bandwidth requirements. Still, appropriate bypassing
discipline must be observed, and all pins related to either the
power supply or the charge pump must be properly
bypassed. See “Power Supply Bypassing and Printed Circuit
Board Layout” on page 13.
THE VREF PIN
Applying a voltage to the VREF pin simply places that
voltage on what would usually be the ground side of the gain
resistor of the amplifier, resulting in a DC-level shift of the
output signal. Applying 100mV to the VREF pin would apply
a 100mV DC level shift to the outgoing signal. The charge
pump provides sufficient bottom room to accommodate the
shifted signal.
The ISL59837 buffers the VREF voltage before applying it to
the triple amplifiers, isolating the input from the amplifiers
and allowing it to be driven by moderate-impedance voltage
sources.
THE VEE PIN
The VEE pin is the output pin for the charge pump. A
voltmeter applied to this pin will display the output of the
charge pump. This pin does not affect the functionality of the
part. One may use this pin as an additional voltage source.
Keep in mind that the output of this pin is generated by the
internal charge pump and a fully regulated supply that must
be properly bypassed. We recommend a 0.1µF ceramic
capacitor placed as close to the pin and connected to the
ground plane of the board.
12
VIDEO PERFORMANCE
For good video performance, an amplifier is required to
maintain the same output impedance and the same frequency
and phase response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω because of the change in output current with
changing DC levels. Special circuitry has been incorporated
into the ISL59837 for the reduction of output impedance
variation with the current output. This results in outstanding
differential gain and differential phase specifications of 0.06%
and 0.1°, while driving 150Ω at a gain of +2. Driving higher
impedance loads would result in similar or better differential
gain and differential phase performance.
NTSC
The ISL59837 (generating a negative rail internally) is ideally
suited for NTSC video with its accompanying negative-going
sync signals, which is easily handled by the ISL59837
without the need for an additional supply as the ISL59837
generates a negative rail with an internal charge pump
referenced at negative 1/2 the positive supply.
YPbPr
YPbPr signals originating from a DVD player requiring three
channels of very tightly-controlled amplifier gain accuracy
present no difficulty for the ISL59837. Specifically, this standard
encodes sync on the Y-Channel and it is a negative-going
signal, which is easily handled by the ISL59837 without the
need for an additional supply as the ISL59837 generates a
negative rail placed at negative 1/2 the positive supply.
Additionally, the Pb and Pr are bipolar analog signals and the
video signals are negative-going, and again, easily handled by
the ISL59837.
DRIVING CAPACITIVE LOADS AND CABLES
The ISL59837 (internally-compensated to drive 75Ω cables) will
drive 10pF loads in parallel with 1kΩ with less than 5dB of
peaking. If less peaking is required, a small series resistor,
usually between 5Ω to 50Ω, can be placed in series with the
output. This will reduce peaking at the expense of a slight
closed loop gain reduction. When used as a cable driver,
double termination is always recommended for reflection-free
performance. For those applications, a back-termination series
resistor at the amplifier's output will isolate the amplifier from
the cable and allow extensive capacitive drive. However, other
applications may have high capacitive loads without a backtermination resistor. Again, a small series resistor at the output
can help to reduce peaking. The ISL59837 is a triple amplifier
FN6335.1
March 5, 2007
ISL59837
for sourcing:
designed to drive three channels; simply deal with each
channel separately as described in this section.
V OUT i
PD MAX = V S × I SMAX + ( V S – V OUT i ) × ----------------R i
DC-RESTORE
L
When the ISL59837 is AC-coupled it becomes necessary to
restore the DC reference for the signal. This is accomplished
with a DC-restore system applied between the capacitive
"AC" coupling and the input of the device. Refer to
“ISL59837 + DC-Restore Solution” on page 10.
(EQ. 2)
for sinking:
PD MAX = V S × I SMAX + ( V OUT i – V S ) × I LOAD i
(EQ. 3)
Where:
DISABLE/POWER-DOWN
The ISL59837 can be disabled and its output placed in a
high impedance state. The turn-off time is around 25ns and
the turn-on time is around 200ns. When the PD pin is taken
high, the chip’s total supply current is reduced to 0.1mA
typically, all but eliminating the power used by the part.
Taking the EN pin high powers down the amplifiers, leaving
the charge pump running. Both pins can be controlled by
standard TTL or CMOS signal levels (0.8V VIL, 2.0V VIH
relative to GND).
OUTPUT DRIVE CAPABILITY
The ISL59837 does not have internal short-circuit protection
circuitry. A short-circuit current of 80mA sourcing and 150mA
sinking for the output is connected half way between the rails
with a 10Ω resistor. If the output is shorted indefinitely, the
power dissipation could easily increase such that the part will
be destroyed. Maximum reliability is maintained if the output
current never exceeds ±40mA, after which the electro-migration
limit of the process will be exceeded and the part will be
damaged. This limit is set by the design of the internal metal
interconnections.
POWER DISSIPATION
With the high output drive capability of the ISL59837, it is
possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
PD MAX = --------------------------------------------θ JA
(EQ. 1)
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
i = Number of output channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
Strip line design techniques are recommended for the input
and output signal traces. As with any high frequency device,
a good printed circuit board layout is necessary for optimum
performance. Lead lengths should be as short as possible.
The power supply pin must be well bypassed to reduce the
risk of oscillation. For normal single supply operation, where
the VS- pin is connected to the ground plane, a single 4.7µF
tantalum capacitor in parallel with a 0.1µF ceramic capacitor
from VS+ to GND will suffice. This same capacitor
combination should be placed at each supply pin to ground if
split-internal supplies are to be used. In this case, the VSpin becomes the negative supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is also very important.
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
13
FN6335.1
March 5, 2007
ISL59837
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
-
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6335.1
March 5, 2007
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