DATASHEET

Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs
and GPUs
ISL62882, ISL62882B
Features
The ISL62882 is a multiphase PWM buck regulator for
miroprocessor or graphics processor core power supply. The
multiphase buck converter uses interleaved phases to reduce the
total output voltage ripple with each phase carrying a portion of the
total load current, providing better system performance, superior
thermal management, lower component cost, reduced power
dissipation, and smaller implementation area. The ISL62882 uses
two integrated gate drivers to provide a complete solution. The PWM
modulator is based on Intersil's Robust Ripple Regulator (R3)
technology™. Compared with traditional modulators, the R3™
modulator commands variable switching frequency during load
transients, achieving faster transient response. With the same
modulator, the switching frequency is reduced at light load,
increasing the regulator efficiency.
• Programmable 1- or 2-Phase CPU Mode Operation or 1-Phase
GPU Mode Operation
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
The ISL62882 can be configured as CPU or graphics Vcore controller
and is fully compliant with IMVP-6.5™ specifications. It responds to
PSI# and DPRSLPVR signals by adding or dropping Phase 2,
adjusting overcurrent protection threshold accordingly, and
entering/exiting diode emulation mode. It reports the regulator
output current through the IMON pin. It senses the current by using
either discrete resistor or inductor DCR whose variation over
temperature can be thermally compensated by a single NTC
thermistor. It uses differential remote voltage sensing to accurately
regulate the processor die voltage. The unique split LGATE function
further increases light load efficiency. The adaptive body diode
conduction time reduction function minimizes the body diode
conduction loss in diode emulation mode. User-selectable overshoot
reduction function offers an option to aggressively reduce the output
capacitors as well as the option to disable it for users concerned
about increased system thermal stress. The ISL62882 offers the
FB2 function to optimize 1-phase performance.
The ISL62882B has the same functions as the ISL62882, but
comes in a different package.
• Microprocessor Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Supports PSI# and DPRSLPVR modes
• Superior Noise Immunity and Transient Response
• Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1- or 2-Phase Operation
• Two Integrated Gate Drivers
• Excellent Dynamic Current Balance Between Phases
• Split LGATE1 Drivers Increases Light Load Efficiency
• FB2 Function Optimizes 1-Phase Mode Performance
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN Packages
• Pb-Free (RoHS Compliant)
Applications
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator
June 21, 2011
FN6890.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL62882, ISL62882B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62882IRTZ
62882 IRTZ
-40 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62882HRTZ
62882 HRTZ
-10 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62882BHRTZ
62882 BHRTZ
-10 to +100
48 Ld 6x6 TQFN
L48.6x6
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62882, ISL62882B. For more information on MSL please see techbrief
TB363.
Pin Configurations
30 BOOT2
PSI# 2
29 UGATE2
RBIAS 3
28 PHASE2
VR_TT# 4
27 VSSP2
NTC 5
VW
GND PAD
(BOTTOM)
6
COMP 7
FB
NC
VID0
VID1
VID2
VID4
VID3
VID5
VR_ON
CLK_EN#
PGOOD 2
NC 1
36 BOOT2
35 UGATE2
PSI# 3
34 PHASE2
RBIAS 4
NTC 6
25 VCCP
GND 7
23 LGATE1a
33 VSSP2
VR_TT# 5
26 LGATE2
24 LGATE1b
8
DPRSLPVR
NC
VID1
VID3
VID2
VID4
VID5
VID6
VR_ON
DPRSLPVR
CLK_EN#
VID0
48 47 46 45 44 43 42 41 40 39 38 37
40 39 38 37 36 35 34 33 32 31
PGOOD 1
VID6
ISL62882B
(48 LD TQFN)
TOP VIEW
ISL62882
(40 LD TQFN)
TOP VIEW
32 LGATE2
31 NC
(BOTTOM)
30 VCCP
8
29 LGATE1b
COMP 9
28 LGATE1a
VW
FB 10
2
NC 12
25 UGATE1
BOOT1
NC
NC
IMON
VIN
VDD
ISUM+
RTN
13 14 15 16 17 18 19 20 21 22 23 24
ISUM-
BOOT1
UGATE1
VIN
IMON
VDD
ISUM+
RTN
ISUM-
VSEN
ISEN1
11 12 13 14 15 16 17 18 19 20
26 PHASE1
VSEN
21 PHASE1
ISEN2 10
27 VSSP1
FB2 11
ISEN1
22 VSSP1
9
ISEN2
FB2
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Functional Pin Descriptions
ISL62882
ISL62882B
SYMBOL
-
7
GND
1
2
PGOOD
Power-Good open-drain output indicating when the regulator is able to supply regulated voltage.
Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
2
3
PSI#
Low load current indicator input. When asserted low, indicates a reduced load current condition.
3
4
RBIAS
A resistor to GND sets internal current reference. Use 147kΩ or 47kΩ. The choice of Rbias value,
together with the ISEN2 pin configuration and the external resistance from the COMP pin to GND,
programs the controller to enable/disable the overshoot reduction function and to select the
CPU/GPU mode.
4
5
VR_TT#
Thermal overload output indicator.
5
6
NTC
Thermistor input to VR_TT# circuit.
6
8
VW
A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately
300kHz).
7
9
COMP
8
10
FB
This pin is the inverting input of the error amplifier.
9
11
FB2
There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is
off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation
in 1-phase mode to achieve optimum performance.
10
13
ISEN2
Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will
disable Phase 2.
11
14
ISEN1
Individual current sensing for phase 1.
12
15
VSEN
Remote core voltage sense input. Connect to microprocessor die.
13
16
RTN
Remote voltage sensing return. Connect to ground at microprocessor die.
14, 15
17, 18
ISUM- and ISUM+
16
19
VDD
5V bias power.
17
20
VIN
Battery supply voltage, used for feed-forward.
18
22
IMON
An analog output. IMON outputs a current proportional to the regulator output current.
19
24
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each
time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
20
25
UGATE1
Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the
Phase-1 high-side MOSFET.
21
26
PHASE1
Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.
22
27
VSSP1
Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the
source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1
low-side MOSFETs.
23
28
LGATE1a
Output of the Phase-1 low-side MOSFET gate driver that is always active. Connect the LGATE1a
pin to the gate of the Phase-1 low-side MOSFET that is active all the time.
24
29
LGATE1b
Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will be pulled low
when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to the gate of the Phase-1
low-side MOSFET that is idle in deeper sleep mode.
-
-
LGATE1
Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
3
DESCRIPTION
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the
overcurrent threshold.
Droop current sense input.
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Functional Pin Descriptions (Continued)
ISL62882
ISL62882B
SYMBOL
25
30
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at
least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.
26
32
LGATE2
Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the
Phase-2 low-side MOSFET.
27
33
VSSP2
Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2
pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET.
28
34
PHASE2
Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.
29
35
UGATE2
Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the
Phase-2 high-side MOSFET.
30
36
BOOT2
Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each
time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
31 thru 37
38 thru 44
VID0 thru VID6
38
45
VR_ON
39
46
DPRSLPVR
40
47
CLK_EN#
-
48
NC
pad
pad
BOTTOM
4
DESCRIPTION
VID input with VID0 = LSB and VID6 = MSB.
Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor
is in deeper sleep mode.
Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is
within 10% of Vboot.
No connect.
The bottom pad of ISL62882B is electrically connected to the GND pin inside the IC.
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Block Diagram
VIN
VSEN
ISEN2
ISEN1
PGOOD
6µA
VR_ON
PSI#
VDD
CLK_EN#
MODE
CONTROL
54µA 1.20V
PGOOD &
CLK_EN#
LOGIC
CURRENT
BALANCE
VR_TT#
1.24V
NTC
DPRSLPVR
IBAL
RBIAS
PROTECTION
BOOT2
FLT
VID0
IBAL
VID1
WOC
VIN VDAC
OC
VIN
VID2
VID3
MODULATOR
DAC
AND
SOFTSTART
CLOCK
COMP
VDAC
COMP
VID4
PWM CONTROL LOGIC
DRIVER
UGATE2
PHASE2
SHOOT THROUGH
PROTECTION
DRIVER
VW
LGATE2
VID5
VSSP2
VID6
BOOT1
DRIVER
E/A
FB
IBAL
COMP
VIN VDAC
MODULATOR
VW
IDROOP
PWM CONTROL LOGIC
Σ
RTN
PHASE1
SHOOT THROUGH
PROTECTION
VCCP
DRIVER
FB2
WOC
IMON
IMON
2.5X
ISUM+
CURRENT
SENSE
LGATE1A
COMP
CURRENT
COMPARATORS
OC
UGATE1
VSSP1
60µA
NUMBER OF
PHASES
DRIVER
LGATE1B
ISUMGAIN
SELECT
5
Σ
ADJ. OCP
THRESHOLD
COMP
GND
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE1a and 1b and LGATE2 Voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
LGATE1a and 1b
. . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 2.5µJ) to VDD+0.3V
LGATE1a and 1b
. . . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT#,
CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
40 Ld TQFN Package (Notes 4, 5) . . . . . . .
32
3
48 Ld TQFN Package (Notes 4, 5) . . . . . . .
29
2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V
Ambient Temperature
ISL62882HRTZ, ISL62882BHRTZ . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL62882IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
ISL62882HRTZ, ISL62882BHRTZ . . . . . . . . . . . . . . . . .-10°C to +125°C
ISL62882IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
4
4.6
mA
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
1
µA
Battery Supply Current
IVIN
VR_ON = 0V
1
µA
VIN Input Resistance
RVIN
VR_ON = 3.3V
900
Power-On-Reset Threshold
PORr
VDD rising
4.35
PORf
VDD falling
4.00
kΩ
4.5
4.15
V
V
SYSTEM AND REFERENCES
System Accuracy
HRTZ
No load; closed loop, active mode range
%Error (VCC_CORE) VID = 0.75V to 1.50V,
-0.5
+0.5
%
VID = 0.5V to 0.7375V
-8
+8
mV
VID = 0.3V to 0.4875V
-15
+15
mV
-0.8
+0.8
%
-10
+10
mV
+18
mV
1.1055
V
IRTZ
No load; closed loop, active mode range
%Error (VCC_CORE) VID = 0.75V to 1.50V
VID = 0.5V to 0.7375V
VID = 0.3V to 0.4875V
VBOOT
-18
1.0945
1.100
Maximum Output Voltage
VCC_CORE(max)
VID = [0000000]
1.500
V
Minimum Output Voltage
VCC_CORE(min)
VID = [1100000]
0.300
V
RBIAS Voltage
RBIAS = 147kΩ
6
1.45
1.47
1.49
V
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
fSW(nom)
Rfset = 7kΩ, 2-channel operation, VCOMP = 1V
MIN
(Note 6)
TYP
285
300
MAX
(Note 6)
UNITS
CHANNEL FREQUENCY
Nominal Channel Frequency
Adjustment Range
200
315
kHz
500
kHz
+0.15
mV
AMPLIFIERS
Current-Sense Amplifier Input Offset
IFB = 0A
Error Amp DC Gain
Av0
Error Amp Gain-Bandwidth Product
GBW
-0.15
CL = 20pF
90
dB
18
MHz
ISEN
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
1
Input Bias Current
20
mV
nA
POWER-GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
PGOOD Delay
tpgd
CLK_ENABLE# LOW to PGOOD HIGH
0.26
0.4
1
μA
7.6
8.9
ms
1.5
Ω
-1
6.3
V
GATE DRIVER
UGATE Pull-Up Resistance
RUGPU
200mA Source Current
1.0
UGATE Source Current
IUGSRC
UGATE - PHASE = 2.5V
2.0
UGATE Sink Resistance
RUGPD
250mA Sink Current
1.0
UGATE Sink Current
IUGSNK
UGATE - PHASE = 2.5V
2.0
LGATE1a and 1b Pull-Up Resistance
RLGPU
250mA Source Current
2.0
LGATE1a and 1b Source Current
ILGSRC
LGATE1a and 1b - VSSP1 = 2.5V
1.0
LGATE1a and 1b Sink Resistance
RLGPD
250mA Sink Current
LGATE1a and 1b Sink Current
ILGSNK
LGATE1a and 1b - VSSP1 = 2.5V
2.0
UGATE1 to LGATE1a and 1b Deadtime
tUGFLGR
UGATE1 falling to LGATE1a and 1b rising, no
load
23
LGATE1a and 1b to UGATE1 Deadtime
tLGFUGR
LGATE1a and 1b falling to UGATE1 rising, no
load
28
1
A
1.5
Ω
A
3
Ω
1.8
Ω
A
A
ns
ns
Ω
LGATE Pull-Up Resistance
RLGPU
250mA Source Current
1.0
LGATE Source Current
ILGSRC
LGATE - VSSP = 2.5V
2.0
LGATE Sink Resistance
RLGPD
250mA Sink Current
0.5
LGATE Sink Current
ILGSNK
LGATE - VSSP = 2.5V
4.0
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
23
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
28
ns
1.5
A
0.9
Ω
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
0.58
V
Reverse Leakage
IR
VR = 25V
0.2
µA
PROTECTION
Overvoltage Threshold
OVH
VSEN rising above setpoint for >1ms
Severe Overvoltage Threshold
OVHS
OC Threshold Offset at
Rcomp = Open Circuit
Current Imbalance Threshold
150
195
240
VSEN rising for >2µs
1.525
1.55
1.575
V
2-phase configuration, ISUM- pin current
18.3
20.2
22.1
µA
1-phase configuration, ISUM- pin current
8.2
10.1
12.0
µA
-355
-295
-235
mV
One ISEN above another ISEN for >1.2ms
Undervoltage Threshold
UVf
7
VSEN falling below setpoint for >1.2ms
9
mV
mV
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
0.3
V
LOGIC THRESHOLDS
VR_ON Input Low
VIL(1.0V)
VR_ON Input High
VIH(1.0V)
ISL62882HRTZ
0.7
VIH(1.0V)
ISL62882IRTZ
0.75
VID0-VID6, PSI#, and DPRSLPVR Input
Low
VIL(1.0V)
VID0-VID6, PSI#, and DPRSLPVR Input
High
VIH(1.0V)
V
V
0.3
0.7
V
V
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-Temperature Threshold
V (NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
CLK_EN# Low Output Voltage
VOL
I = 4mA
CLK_EN# Leakage Current
IOH
CLK_EN# = 3.3V
53
60
67
µA
1.18
1.2
1.22
V
6.5
9
Ω
0.26
0.4
V
1
µA
CLK_EN# OUTPUT LEVELS
-1
CURRENT MONITOR
IMON Output Current
IIMON
IMON Clamp Voltage
ISUM- pin current = 20µA
108
120
132
µA
ISUM- pin current = 10µA
51
60
69
µA
ISUM- pin current = 5µA
22
30
37.5
µA
1.1
1.15
VIMONCLAMP
Current Sinking Capability
275
V
µA
INPUTS
VR_ON Leakage Current
IVR_ON
VR_ON = 0V
-1
VR_ON = 1V
VIDx Leakage Current
IVIDx
PSI# Leakage Current
IPSI#
VIDx = 0V
-1
VIDx = 1V
PSI# = 0V
IDPRSLPVR
DPRSLPVR = 0V
DPRSLPVR = 1V
1
µA
µA
1
0
0.45
µA
µA
0
0.45
-1
µA
1
0
0.45
-1
PSI# = 1V
DPRSLPVR Leakage Current
0
0
µA
µA
1
µA
6.5
mV/µs
SLEW RATE
Slew Rate (For VID Change)
SR
5
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tUGFLGR
9
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Simplified Application Circuits
V+5
V+5
Vin
VDD VCCP VIN
Rbias
RBIAS
Rntc
NTC
o
C
PGOOD
VR_TT#
CLK_EN#
VIDs
PSI#
DPRSLPVR
VR_ON
VW
PGOOD
VR_TT#
CLK_EN#
VID<0:6>
PSI#
DPRSLPVR
VR_ON
L2
Vo
PHASE2
LGATE2
VSSP2
Rs2
ISEN2
Cs2
ISL62882
Rfset
BOOT1
UGATE1
PHASE1
LGATE1b
LGATE1a
VSSP1
COMP
FB2
FB
Rdroop
Vin
BOOT2
UGATE2
L1
Rs1
ISEN1
Cs1
VSEN
ISUM+
Rsum2
Rn
Ris
VCCSENSE
VSSSENSE
Cn
RTN
o
C
Rsum1
Cis
Rimon
Ri
IMON
IMON
(Bottom Pad)
VSS
ISUM-
FIGURE 1. TYPICAL CPU APPLICATION CIRCUIT USING DCR SENSING
V+5
V+5
Vin
VDD VCCP VIN
Rbias
RBIAS
Rntc
NTC
o
C
PGOOD
VR_TT#
CLK_EN#
VIDs
PSI#
DPRSLPVR
VR_ON
VW
IMVP6_PWRGD
VR_TT#
CLK_ENABLE
VID<0:6>
#
PSI#
DPRSLPVR
VR_ON
UGATE2
COMP
FB2
FB
L2
Rsen2
L1
Rsen1
PHASE2
LGATE2
VSSP2
Vo
Rs2
ISEN2
Cs2
ISL62882
Rfset
Rdroop
Vin
BOOT2
BOOT1
UGATE1
PHASE1
LGATE1b
LGATE1a
VSSP1
Rs1
ISEN1
Cs1
VSEN
ISUM+
Rsum2
Ris
VCCSENSE
VSSSENSE
Cn
RTN
Cis
Rimon
Ri
IMON
IMON
Rsum1
(Bottom Pad)
VSS
ISUM-
FIGURE 2. TYPICAL CPU APPLICATION CIRCUIT USING RESISTOR SENSING
10
FN6890.4
June 21, 2011
ISL62882, ISL62882B
V+5
V+5
Vin
VDD VCCP VIN
Rbias
RBIAS
Rntc
NTC
o
C
PGOOD
VR_TT#
CLK_EN#
VID<0:6>
PSI#
DPRSLPVR
VR_ON
BOOT2
UGATE2
PGOOD
VR_TT#
CLK_EN#
VIDs
PSI#
DPRSLPVR
VR_ON
VW
PHASE2
LGATE2
VSSP2
ISEN2
ISL62882
Rfset
COMP
FB2
FB
Rdroop
Vin
BOOT1
UGATE1
PHASE1
LGATE1b
LGATE1a
VSSP1
L
Vo
ISEN1
VSEN
ISUM+
Rsum
Rn
Ris
VCCSENSE
VSSSENSE
Cn
RTN
o
C
Cis
Rimon
Ri
IMON
IMON
(Bottom Pad)
VSS
ISUM-
FIGURE 3. TYPICAL GPU APPLICATION CIRCUIT USING DCR SENSING
V+5
V+5
Vin
VDD VCCP VIN
Rbias
RBIAS
Rntc
NTC
o
C
IMVP6_PWRGD
VR_TT#
CLK_ENABLE
VID<0:6>
#
PSI#
DPRSLPVR
VR_ON
BOOT2
PGOOD
VR_TT#
CLK_EN#
VIDs
PSI#
DPRSLPVR
VR_ON
VW
PHASE2
LGATE2
VSSP2
ISEN2
ISL62882
Rfset
COMP
Rdroop
UGATE2
FB2
FB
Vin
BOOT1
UGATE1
PHASE1
LGATE1b
LGATE1a
VSSP1
L
Rsen
Vo
ISEN1
VSEN
ISUM+
Rsum2
Ris
VCCSENSE
VSSSENSE
Cn
RTN
Cis
Rimon
Ri
IMON
IMON
(Bottom Pad)
VSS
ISUM-
FIGURE 4. TYPICAL GPU APPLICATION CIRCUIT USING RESISTOR SENSING
11
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Theory of Operation
VW
Multiphase R3™ Modulator
Master Clock Circuit
Master
COMP
Clock
Phase
Vcrm
Sequencer
COMP
VW
Master
Clock
Vcrm
Clock1
Clock2
Master
Clock
Crm
gmVo
Clock1
VW
VW
Slave Circuit 1
Clock1 S PWM1 Phase1
Q
R
L1
PWM1
Vo
Clock2
IL1
Vcrs1
Co
PWM2
VW
gm
Crs1
VW
Slave Circuit 2
Phase2
S PWM2
Q
R
Clock2
L2
IL2
Vcrs2
Vcrs1
Vcrs2
FIGURE 7. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
gm
Crs2
FIGURE 5. R3™ MODULATOR CIRCUIT
VW
Hysteretic
Window
Vcrm
COMP
The ISL62882 is a multiphase regulator implementing Intel®
IMVP-6.5™ protocol. It can be programmed for 1- or 2-phase
operation for microprocessor core applications. It uses Intersil
patented R3™ (Robust Ripple Regulator™) modulator. The R3™
modulator combines the best features of fixed frequency PWM
and hysteretic PWM while eliminating many of their shortcomings.
Figure 5 conceptually shows the ISL62882 multiphase R3™
modulator circuit, and Figure 6 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Master
Clock
Clock1
PWM1
Clock2
PWM2
VW
Vcrs2
Vcrs1
FIGURE 6. R3™ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
12
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor Crm with a current source equal
to gmVo, where gm is a gain factor. Crm voltage Vcrm is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the ISL62882 is in
2-phase mode, the master clock signal will be distributed to
Phases 1 and 2, and the Clock1 and Clock2 signals will be 180°
out-of-phase. If the ISL62882 is in 1-phase mode, the master
clock signal will be distributed to Phases 1 only and be the
Clock1 signal.
Each slave circuit has its own ripple capacitor Crs, whose voltage
mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge
Crs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges Crs. When Crs
voltage VCrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Since the ISL62882 works with Vcrs, which are large amplitude
and noise-free synthesized signals, the ISL62882 achieves lower
phase jitter than conventional hysteretic mode and fixed PWM
mode controllers. Unlike conventional hysteretic mode
converters, the ISL62882 has an error amplifier that allows the
controller to maintain a 0.5% output voltage accuracy.
Figure 7 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching frequency,
which allows for higher control loop bandwidth than conventional
fixed frequency PWM controllers. The VW voltage rises as the
COMP voltage rises, making the PWM pulses wider. During load
release response, the COMP voltage falls. It takes the master clock
circuit longer to generate the next master clock signal so the PWM
pulse is held off until needed. The VW voltage falls as the VW
voltage falls, reducing the current PWM pulse width. This kind of
behavior gives the ISL62882 excellent response speed.
The fact that both phases share the same VW window voltage
also ensures excellent dynamic current balance between phases.
Figure 9 shows the operation principle in diode emulation mode at
light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor current
triangle the same in the three cases. The ISL62882 clamps the
ripple capacitor voltage Vcrs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit Vcrs,
naturally stretching the switching period. The inductor current
triangles move further apart from each other such that the
inductor current average value is equal to the load current. The
reduced switching frequency helps to increase light load efficiency.
CCM/DCM BOUNDARY
VW
Vcrs
iL
VW
LIGHT DCM
Vcrs
Diode Emulation and Period Stretching
iL
DEEP DCM
PHASE
VW
Vcrs
UGATE
iL
LGATE
FIGURE 9. PERIOD STRETCHING
IL
FIGURE 8. DIODE EMULATION
ISL62882 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and does not
allow reverse current, emulating a diode. As Figure 8 shows,
when LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop
across the ON-resistance. The ISL62882 monitors the current
through monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the
inductor current from reversing the direction and creating
unnecessary power loss.
If the load current is light enough, as Figure 8 shows, the inductor
current will reach and stay at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.
13
Start-up Timing
With the controller's VDD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the 3.3V logic high
threshold. Figure 10 shows the typical start-up timing when the
ISL62882 is configured for CPU VR application. The ISL62882
uses digital soft-start to ramp-up DAC to the boot voltage of 1.1V at
about 2.5mV/µs. Once the output voltage is within 10% of the
boot voltage for 13 PWM cycles (43µs for frequency = 300kHz),
CLK_EN# is pulled low and DAC slews at 5mV/µs to the voltage set
by the VID pins. PGOOD is asserted high in approximately 7ms.
Similar results occur if VR_ON is tied to VDD, with the soft-start
sequence starting 120µs after VDD crosses the POR threshold.
Figure 11 shows the typical start-up timing when the ISL62882 is
configured for GPU VR application. The ISL62882 uses digital
soft start to ramp up DAC to the voltage set by the VID pins. The
slew rate is 5mV/µs when there is DPRSLPVR = 0, and is
doubled when there is DPRSLPVR = 1. Once the output voltage is
within 10% of the target voltage for 13 PWM cycles (43µs for
frequency = 300kHz), CLK_EN# is pulled low. PGOOD is asserted
high in approximately 7ms. Similar results occur if VR_ON is tied
to VDD, with the soft-start sequence starting 120µs after VDD
crosses the POR threshold.
FN6890.4
June 21, 2011
ISL62882, ISL62882B
TABLE 1. VID TABLE (Continued)
VDD
5mV/µs
VR_ON
2.5mV/µs
90% Vboot
800µs
VID
COMMAND
VOLTAGE
DAC
13 SWITCHING
CYCLES
CLK_EN#
~7ms
PGOOD
FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR APPLICATION
VDD
VR_ON
SLEW
RATE
90%
120µs
VID COMMAND
VOLTAGE
DAC
13 SWITCHING
CYCLES
CLK_EN#
~7ms
PGOOD
FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR APPLICATION
Voltage Regulation and Load Line
Implementation
After the start sequence, the ISL62882 regulates the output
voltage to the value set by the VID inputs per Table 1. The
ISL62882 will control the no-load output voltage to an accuracy of
±0.5% over the range of 0.75V to 1.5V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.
TABLE 1. VID TABLE
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
0
0
0
0
0
0
0
1.5000
0
0
0
0
0
0
1
1.4875
0
0
0
0
0
1
0
1.4750
0
0
0
0
0
1
1
1.4625
0
0
0
0
1
0
0
1.4500
0
0
0
0
1
0
1
1.4375
0
0
0
0
1
1
0
1.4250
0
0
0
0
1
1
1
1.4125
0
0
0
1
0
0
0
1.4000
0
0
0
1
0
0
1
1.3875
0
0
0
1
0
1
0
1.3750
0
0
0
1
0
1
1
1.3625
14
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
0
0
0
1
1
0
0
1.3500
0
0
0
1
1
0
1
1.3375
0
0
0
1
1
1
0
1.3250
0
0
0
1
1
1
1
1.3125
0
0
1
0
0
0
0
1.3000
0
0
1
0
0
0
1
1.2875
0
0
1
0
0
1
0
1.2750
0
0
1
0
0
1
1
1.2625
0
0
1
0
1
0
0
1.2500
0
0
1
0
1
0
1
1.2375
0
0
1
0
1
1
0
1.2250
0
0
1
0
1
1
1
1.2125
0
0
1
1
0
0
0
1.2000
0
0
1
1
0
0
1
1.1875
0
0
1
1
0
1
0
1.1750
0
0
1
1
0
1
1
1.1625
0
0
1
1
1
0
0
1.1500
0
0
1
1
1
0
1
1.1375
0
0
1
1
1
1
0
1.1250
0
0
1
1
1
1
1
1.1125
0
1
0
0
0
0
0
1.1000
0
1
0
0
0
0
1
1.0875
0
1
0
0
0
1
0
1.0750
0
1
0
0
0
1
1
1.0625
0
1
0
0
1
0
0
1.0500
0
1
0
0
1
0
1
1.0375
0
1
0
0
1
1
0
1.0250
0
1
0
0
1
1
1
1.0125
0
1
0
1
0
0
0
1.0000
0
1
0
1
0
0
1
0.9875
0
1
0
1
0
1
0
0.9750
0
1
0
1
0
1
1
0.9625
0
1
0
1
1
0
0
0.9500
0
1
0
1
1
0
1
0.9375
0
1
0
1
1
1
0
0.9250
0
1
0
1
1
1
1
0.9125
0
1
1
0
0
0
0
0.9000
0
1
1
0
0
0
1
0.8875
0
1
1
0
0
1
0
0.8750
FN6890.4
June 21, 2011
ISL62882, ISL62882B
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO
(V)
0
1
1
0
0
1
1
0.8625
1
0
1
1
0
1
0
0.3750
0
1
1
0
1
0
0
0.8500
1
0
1
1
0
1
1
0.3625
0
1
1
0
1
0
1
0.8375
1
0
1
1
1
0
0
0.3500
0
1
1
0
1
1
0
0.8250
1
0
1
1
1
0
1
0.3375
0
1
1
0
1
1
1
0.8125
1
0
1
1
1
1
0
0.3250
0
1
1
1
0
0
0
0.8000
1
0
1
1
1
1
1
0.3125
0
1
1
1
0
0
1
0.7875
1
1
0
0
0
0
0
0.3000
0
1
1
1
0
1
0
0.7750
1
1
0
0
0
0
1
0.2875
0
1
1
1
0
1
1
0.7625
1
1
0
0
0
1
0
0.2750
0
1
1
1
1
0
0
0.7500
1
1
0
0
0
1
1
0.2625
0
1
1
1
1
0
1
0.7375
1
1
0
0
1
0
0
0.2500
0
1
1
1
1
1
0
0.7250
1
1
0
0
1
0
1
0.2375
0
1
1
1
1
1
1
0.7125
1
1
0
0
1
1
0
0.2250
1
0
0
0
0
0
0
0.7000
1
1
0
0
1
1
1
0.2125
1
0
0
0
0
0
1
0.6875
1
1
0
1
0
0
0
0.2000
1
0
0
0
0
1
0
0.6750
1
1
0
1
0
0
1
0.1875
1
0
0
0
0
1
1
0.6625
1
1
0
1
0
1
0
0.1750
1
0
0
0
1
0
0
0.6500
1
1
0
1
0
1
1
0.1625
1
0
0
0
1
0
1
0.6375
1
1
0
1
1
0
0
0.1500
1
0
0
0
1
1
0
0.6250
1
1
0
1
1
0
1
0.1375
1
0
0
0
1
1
1
0.6125
1
1
0
1
1
1
0
0.1250
1
0
0
1
0
0
0
0.6000
1
1
0
1
1
1
1
0.1125
1
0
0
1
0
0
1
0.5875
1
1
1
0
0
0
0
0.1000
1
0
0
1
0
1
0
0.5750
1
1
1
0
0
0
1
0.0875
1
0
0
1
0
1
1
0.5625
1
1
1
0
0
1
0
0.0750
1
0
0
1
1
0
0
0.5500
1
1
1
0
0
1
1
0.0625
1
0
0
1
1
0
1
0.5375
1
1
1
0
1
0
0
0.0500
1
0
0
1
1
1
0
0.5250
1
1
1
0
1
0
1
0.0375
1
0
0
1
1
1
1
0.5125
1
1
1
0
1
1
0
0.0250
1
0
1
0
0
0
0
0.5000
1
1
1
0
1
1
1
0.0125
1
0
1
0
0
0
1
0.4875
1
1
1
1
0
0
0
0.0000
1
0
1
0
0
1
0
0.4750
1
1
1
1
0
0
1
0.0000
1
0
1
0
0
1
1
0.4625
1
1
1
1
0
1
0
0.0000
1
0
1
0
1
0
0
0.4500
1
1
1
1
0
1
1
0.0000
1
0
1
0
1
0
1
0.4375
1
1
1
1
1
0
0
0.0000
1
0
1
0
1
1
0
0.4250
1
1
1
1
1
0
1
0.0000
1
0
1
0
1
1
1
0.4125
1
1
1
1
1
1
0
0.0000
1
0
1
1
0
0
0
0.4000
1
1
1
1
1
1
1
0.0000
1
0
1
1
0
0
1
0.3875
15
FN6890.4
June 21, 2011
ISL62882, ISL62882B
VCC SENSE + V
droop
= V DAC + VSS SENSE
(EQ. 3)
Rdroop
Rewriting Equation 3 and substitution of Equation 2 gives:
VCCSENSE
Vdroop
FB
VR LOCAL
“CATCH”
VO
RESISTOR
Idroop
E/A
COMP
Σ VDAC DAC
VIDs
VID<0:6>
VSSSENSE
X1
VSS
“CATCH”
RESISTOR
FIGURE 12. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
Equation 4 is the exact equation required for load line
implementation.
Phase Current Balancing
As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to the
load current to achieve the load line. The ISL62882 can sense
the inductor current through the intrinsic DC Resistance (DCR) of
the inductors as shown in Figure 1 or through resistors in series
with the inductors as shown in Figure 2. In both methods,
capacitor Cn voltage represents the inductor total currents. A
droop amplifier converts Cn voltage into an internal current
source with the gain set by resistor Ri. The current source is used
for load line implementation, current monitor and overcurrent
protection.
Figure 12 shows the load line implementation. The ISL62882
drives a current source Idroop out of the FB pin, described by
Equation 1.
2xV Cn
I droop = ---------------Ri
(EQ. 4)
The VCCSENSE and VSSSENSE signals come from the processor die.
The feedback will be open circuit in the absence of the processor. As
Figure 12 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage
feedback if the system is powered up without a processor installed.
RTN
INTERNAL
TO IC
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
(EQ. 1)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding thus sustaining the load line accuracy with
reduced cost.
L2
RDCR2
RPCB2
PHASE2
RS
ISEN2
CS
INTERNAL TO IC
VO
IL2
L1
RDCR1
RPCB1
PHASE1
RS
ISEN1
IL1
CS
FIGURE 13. CURRENT BALANCING CIRCUIT
The ISL62882 monitors individual phase average current by
monitoring the ISEN1 and ISEN2 voltages. Figure 13 shows the
current balancing circuit recommended for ISL62882. Each
phase node voltage is averaged by a low-pass filter consisting of
Rs and Cs, and presented to the corresponding ISEN pin. Rs
should be routed to inductor phase-node pad in order to
eliminate the effect of phase node parasitic PCB DCR. Equations
5 and 6 give the ISEN pin voltages:
V ISEN1 = ( R dcr1 + R pcb1 ) × I L1
(EQ. 5)
Idroop flows through resistor Rdroop and creates a voltage drop as
shown in Equation 2.
V ISEN2 = ( R dcr2 + R pcb2 ) × I L2
(EQ. 6)
V droop = R droop × I droop
where Rdcr1 and Rdcr2 are inductor DCR; Rpcb1 and Rpcb2 are
parasitic PCB DCR between the inductor output side pad and the
output voltage rail; and IL1 and IL2 are inductor average currents.
(EQ. 2)
Vdroop is the droop voltage required to implement load line.
Changing Rdroop or scaling Idroop can both change the load line
slope. Since Idroop also sets the overcurrent protection level, it is
recommended to first scale Idroop based on OCP requirement,
then select an appropriate Rdroop value to obtain the desired
load line slope.
Differential Sensing
Figure 12 also shows the differential voltage sensing scheme.
VCCSENSE and VSSSENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSSSENSE voltage and add it to the DAC output. The error
amplifier regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 3:
16
The ISL62882 will adjust the phase pulse-width relative to the
other phase to make VISEN1 = VISEN2, thus to achieve IL1 = IL2,
when there are Rdcr1 = Rdcr2 and Rpcb1 = Rpcb2.
Using same components for L1 and L2 will provide a good match
of Rdcr1 and Rdcr2. Board layout will determine Rpcb1 and Rpcb2.
It is recommended to have symmetrical layout for the power
delivery path between each inductor and the output voltage rail,
such that Rpcb1 = Rpcb2 .
FN6890.4
June 21, 2011
ISL62882, ISL62882B
ISEN2
PHASE2
Rs
Cs
INTERNAL
TO IC
Rdcr2
L2
V2p
REP RATE = 10kHz
V2n Rpcb2
IL2
Rs
VO
Rs
Rs
ISEN1
Cs
PHASE1
L1
Rdcr1
V1p
Rpcb1
V1n
IL1
FIGURE 14. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
REP RATE = 25kHz
Sometimes, it is difficult to implement symmetrical layout. For
the circuit Figure 13 shows, asymmetric layout causes different
Rpcb1 and Rpcb2 thus current imbalance. Figure 14 shows a
differential-sensing current balancing circuit recommended for
ISL62882. The current sensing traces should be routed to the
inductor pads so they only pick up the inductor DCR voltage. Each
ISEN pin sees the average voltage of two sources: its own phase
inductor phase-node pad, and the other phase inductor output
side pad. Equations 7 and 8 give the ISEN pin voltages:
V ISEN1 = V 1p + V 2n
(EQ. 7)
V ISEN2 = V 2p + V 1n
(EQ. 8)
REP RATE = 50kHz
The ISL62882 will make VISEN1 = VISEN2. So there are:
V 1p + V 2n = V 2p + V 1n
(EQ. 9)
Rewriting Equation 9 gives:
V 1p – V 1n = V 2p – V 2n
(EQ. 10)
REP RATE = 100kHz
Therefore:
R dcr1 × I L1 = R dcr2 × I L2
(EQ. 11)
Current balancing (IL1 = IL2) will be achieved when there is
Rdcr1 = Rdcr2. Rpcb1 and Rpcb2 will not have any effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, R3™ modulator can naturally achieve excellent current
balancing during steady state and dynamic operations. Figure 15
shows current balancing performance of the ISL62882
evaluation board with load transient of 15A/50A at different rep
rates. The inductor currents follow the load current dynamic
change with the output capacitors supplying the difference. The
inductor currents can track the load current well at a low rep rate,
but cannot keep up when the rep rate gets into the hundred-kHz
range, where it’s out of the control loop bandwidth. The controller
achieves excellent current balancing in all cases.
REP RATE = 200kHz
FIGURE 15. ISL62882 EVALUATION BOARD CURRENT BALANCING
DURING DYNAMIC OPERATION.
Ch1: IL1, Ch2: IIoad, Ch3: IL2
17
FN6890.4
June 21, 2011
ISL62882, ISL62882B
CCM Switching Frequency
The Rfset resistor between the COMP and the VW pins sets the
VW windows size, therefore sets the switching frequency. When
the ISL62882 is in continuous conduction mode (CCM), the
switching frequency is not absolutely constant due to the nature
of the R3™ modulator. As explained in the “Multiphase R3™
Modulator” on page 12, the effective switching frequency will
increase during load insertion and will decrease during load
release to achieve fast response. On the other hand, the
switching frequency is relatively constant at steady state.
Variation is expected when the power stage condition, such as
input voltage, output voltage, load, etc. changes. The variation is
usually less than 15% and doesn’t have any significant effect on
output voltage ripple magnitude. Equation 12 gives an estimate
of the frequency-setting resistor Rfset value. 8kΩ Rfset gives
approximately 300kHz switching frequency. Lower resistance
gives higher switching frequency.
R fset ( kΩ ) = ( Period ( μs ) – 0.29 ) × 2.65
(EQ. 12)
Modes of Operation
TABLE 2. ISL62882 CONFIGURATIONS
Rbias
(kΩ)
ISEN2
CONFIGURATION
Connected to the
Power Stage
147
Tied to 5V
147
1-phase CPU VR
47
1-phase GPU VR
OVERSHOOT
REDUCTION
FUNCTION
2-phase CPU VR
Disabled
47
Enabled
See Table 4
TABLE 3. ISL62882 MODES OF OPERATION
CONFIG.
OPERATIONAL
MODE
PSI#
DPRSLPVR
0
0
1-phase CCM
0
1
1-phase DE
1
0
2-phase CCM
1
1
1-phase DE
1-phase CPU
Configuration
x
0
1-phase CCM
1
1-phase DE
1-phase GPU
Configuration
x
0
1-phase CCM
1
1-phase DE
2-phase CPU
Configuration
VOLTAGE
SLEW
RATE
5mV/µs
Table 3 shows the ISL62882 operational modes, programmed by
the logic status of the PSI# and DPRSLPVR pins.
In 2-phase configuration, the ISL62882 enters 1-phase CCM for
(PSI# = 0 and DPRSLPVR = 0). It drops phase 2 and reduces the
overcurrent and the way-overcurrent protection levels to 1/2 of
the initial values. The ISL62882 enters 1-phase DE mode when
DPRSLPVR = 1 by dropping phase 2.
In 1-phase configuration, the ISL62882 does not change the
operational mode when the PSI# signal changes status. It enters
1-phase DE mode when DLPRSLPVR = 1.
Dynamic Operation
When the ISL62882 is configured for CPU VR application, it
responds to VID changes by slewing to the new voltage at
5mV/µs slew rate. As the output approaches the VID command
voltage, the dv/dt moderates to prevent overshoot. Geyserville-III
transitions commands one LSB VID step (12.5mV) every 2.5µs,
controlling the effective dv/dt at 5mv/µs. The ISL62882 is
capable of 5mV/µs slew rate.
When the ISL62882 is configured for GPU VR application, it
responds to VID changes by slewing to the new voltage at a slew
rate set by the logic status on the DPRSLPVR pin. The slew rate is
5mV/µs when DPRSLPVR = 0 and is doubled when
DPRSLPVR = 1.
When the ISL62882 is in DE mode, it will actively drive the output
voltage up when the VID changes to a higher value. It’ll resume
DE mode operation after reaching the new voltage level. If the
load is light enough to warrant DCM, it will enter DCM after the
inductor current has crossed zero for four consecutive cycles. The
ISL62882 will remain in DE mode when the VID changes to a
lower value. The output voltage will decay to the new value and
the load will determine the slew rate. Over-voltage protection is
blanked during VID down transition in DE mode until the output
voltage is within 60mV of the VID value.
During load insertion response, the Fast Clock function increases
the PWM pulse response speed. The ISL62882 monitors the
VSEN pin voltage and compares it to 100ns-filtered version.
When the unfiltered version is 20mV below the filtered version,
the controller knows there is a fast voltage dip due to load
insertion, hence issues an additional master clock signal to
deliver a PWM pulse immediately.
10mV/µs
The ISL62882 can be configured for 2- or 1-phase operation.
For 1-phase configuration, tie the ISEN2 pin to 5V. In this
configuration, only phase-1 is active.
Table 2 shows the ISL62882 configurations, programmed by the
ISEN2 pin status and the Rbias value.
If the ISEN2 pin is connected to the power stage, the ISL62882 is
in 2-phase CPU VR configuration. Rbias = 147kΩ disables the
overshoot reduction function and Rbias = 47kΩ enables it.
18
If ISEN2 is tied to 5V, the ISL62882 is configured for 1-phase
operation. Rbias = 147kΩ sets 1-phase CPU VR configuration
and Rbias = 47kΩ sets 1-phase GPU configuration.
The R3™ modulator intrinsically has voltage feed-forward. The
output voltage is insensitive to a fast slew rate input voltage
change.
Protections
The ISL62882 provides overcurrent, current-balance,
undervoltage, overvoltage, and over-temperature protections.
The ISL62882 determines overcurrent protection (OCP) by
comparing the average value of the droop current Idroop with an
internal current source threshold. It declares OCP when Idroop is
above the threshold for 120µs. A resistor Rcomp from the COMP
pin to GND programs the OCP current source threshold, as well
FN6890.4
June 21, 2011
ISL62882, ISL62882B
as the overshoot reduction function in 1-phase configuration, as
Table 4 shows. It is recommended to use the nominal Rcomp
value. The ISL62882 detects the Rcomp value at the beginning of
start-up, and sets the internal OCP threshold accordingly. It
remembers the Rcomp value until the VR_ON signal drops below
the POR threshold.
TABLE 4. ISL62882 Rcomp PROGRAMABILITY
2-PHASE
CONFIG.
Rcomp
MIN
(kΩ)
1-PHASE CONFIG.
NOMINAL
(kΩ)
MAX
(kΩ)
none
none
40
20
320
400
480
45.3
22.7
210
235
260
41.3
20.7
155
165
175
36
18
104
120
136
37.33
20
78
85
92
38.7
22.7
62
66
70
42.7
20.7
45
50
55
44
18
OCP THRESHOLD (µA)
OVERSHOOT
REDUCTION
FUNCTION
The second level of overvoltage protection is different. If the output
voltage exceeds 1.55V, the ISL62882 will immediately declare an
OV fault, de-assert PGOOD, and turn on the low-side power
MOSFETs. The low-side power MOSFETs remain on until the output
voltage is pulled down below 0.85V when all power MOSFETs are
turned off. If the output voltage rises above 1.55V again, the
protection process is repeated. This behavior provides the
maximum amount of protection against shorted high-side power
MOSFETs while preventing output ringing below ground. Resetting
VR_ON cannot clear the 1.55V OVP. Only resetting VDD will clear it.
The 1.55V OVP is active all the time when the controller is enabled,
even if one of the other faults have been declared. This ensures
that the processor is protected against high-side power MOSFET
leakage while the MOSFETs are commanded off.
Disabled
The ISL62882 has a thermal throttling feature. If the voltage on
the NTC pin goes below the 1.18V OT threshold, the VR_TT# pin is
pulled low indicating the need for thermal throttling to the
system. No other action is taken within the ISL62882 in response
to NTC pin voltage.
Enabled
Table 5 summarizes the fault protections.
The default OCP threshold is the value when Rcomp is not populated.
It is recommended to scale the droop current Idroop such that the
default OCP threshold gives approximately the desired OCP level,
then use Rcomp to fine tune the OCP level if necessary.
For overcurrent conditions above 2.5x the OCP level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection. This protection is also referred to as wayovercurrent protection or fast-overcurrent protection, for shortcircuit protections.
TABLE 5. FAULT PROTECTION SUMMARY
FAULT TYPE
Overcurrent
120µs
Way-Overcurrent
(2.5xOC)
<2µs
Overvoltage +200mV
1ms
PROTECTION
ACTION
PWM tri-state,
PGOOD latched
low
FAULT
RESET
VR_ON
toggle or
VDD toggle
Undervoltage -300mV
Phase Current
Unbalance
Overvoltage 1.55V
The ISL62882 monitors the ISEN pin voltages to determine
current-balance protection. If the ISEN pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
latch off.
The ISL62882 will declare undervoltage (UV) fault and latch off if
the output voltage is less than the VID set value by 300mV or
more for 1ms. It’ll turn off the PWM outputs and de-assert
PGOOD.
FAULT DURATION
BEFORE
PROTECTION
Over-Temperature
Immediately
Low-side MOSFET VDD toggle
on until VCORE
<0.85V, then
PWM tri-state,
PGOOD latched
low.
1ms
N/A
The ISL62882 has two levels of overvoltage protections. The first
level of overvoltage protection is referred to as PGOOD
overvoltage protection. If the output voltage exceeds the VID set
value by +200mV for 1ms, the ISL62882 will declare a fault and
de-assert PGOOD.
The ISL62882 takes the same actions for all of the above fault
protections: de-assertion of PGOOD and turn-off of the high-side
and low-side power MOSFETs. Any residual inductor current will
decay through the MOSFET body diodes. These fault conditions
can be reset by bringing VR_ON low or by bringing VDD below the
POR threshold. When VR_ON and VDD return to their high
operating levels, a soft-start will occur.
19
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Current Monitor
The ISL62882 provides the current monitor function. The IMON
pin outputs a high-speed analog current source that is 3 times of
the droop current flowing out of the FB pin. Thus Equation 13:
I IMON = 3 × I droop
(EQ. 13)
As Figures 1 and 2 show, a resistor Rimon is connected to the
IMON pin to convert the IMON pin current to voltage. A capacitor
can be paralleled with Rimon to filter the voltage information. The
IMVP-6.5™ specification requires that the IMON voltage
information be referenced to VSSSENSE.
Overshoot Reduction Function
The IMON pin voltage range is 0V to 1.1V. A clamp circuit
prevents the IMON pin voltage from going above 1.1V.
The ISL62882 has an optional overshoot reduction function.
Tables 2 and 4 show to enable and disable it.
FB2 Function
The FB2 function is only available when the ISL62882 is in 2phase configuration.
C1 R2
CONTROLLER IN
2-PHASE MODE
C1 R2
CONTROLLER IN
1-PHASE MODE
C3.1
C2 R3
VSEN
FB2
C3.1
C2 R3
C3.2
R1
FB2
C3.2
R1
VSEN
FB
VREF
E/A
FB
COMP
E/A
VREF
COMP
FIGURE 16. FB2 FUNCTION IN 2-PHASE MODE
Figure 16 shows the FB2 function. A switch (called FB2 switch)
turns on to short the FB and the FB2 pins when the controller is in
2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving
as part of the compensator. When the controller enters 1-phase
mode, the FB2 switch turns off, removing C3.2 and leaving only
C3.1 in the compensator. The compensator gain will increase
with the removal of C3.2. By properly sizing C3.1 and C3.2, the
compensator cab be optimal for both 2-phase mode and 1-phase
mode.
When the FB2 switch is off, C3.2 is disconnected from the FB pin.
However, the controller still actively drives the FB2 pin voltage to
follow the FB pin voltage such that C3.2 voltage always follows
C3.1 voltage. When the controller turns on the FB2 switch, C3.2
will be reconnected to the compensator smoothly.
The FB2 function ensures excellent transient response in both
2-phase mode and 1-phase mode. If one decides not to use the
FB2 function, simply populate C3.1 only.
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative and the amount is the
MOSFET rDS(ON) voltage drop, which is proportional to the
inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the
zero-crossing point of the inductor current. If the inductor current
20
has not reached zero when the low-side MOSFET turns off, it’ll
flow through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it’ll flow through the
high-side MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET and
adjusts the phase comparator threshold voltage accordingly in
iterative steps such that the low-side MOSFET body diode
conducts for approximately 40ns to minimize the body
diode-related loss.
When a load release occurs, the energy stored in the inductors
will dump to the output capacitor, causing output voltage
overshoot. The inductor current freewheels through the low-side
MOSFET during this period of time. The overshoot reduction
function turns off the low-side MOSFET during the output voltage
overshoot, forcing the inductor current to freewheel through the
low-side MOSFET body diode. Since the body diode voltage drop
is much higher than MOSFET Rdson voltage drop, more energy is
dissipated on the low-side MOSFET therefore the output voltage
overshoot is lower.
If the overshoot reduction function is enabled, the ISL62882
monitors the COMP pin voltage to determine the output voltage
overshoot condition. The COMP voltage will fall and hit the clamp
voltage when the output voltage overshoots. The ISL62882 will
turn off LGATE1 and LGATE2 when COMP is being clamped. All
the low-side MOSFETs in the power stage will be turned off. When
the output voltage has reached its peak and starts to come
down, the COMP voltage starts to rise and is no longer clamped.
The ISL62882 will resume normal PWM operation.
When PSI# is low, indicating a low power state of the CPU, the
controller will disable the overshoot reduction function as large
magnitude transient event is not expected and overshoot is not a
concern.
While the overshoot reduction function reduces the output voltage
overshoot, energy is dissipated on the low-side MOSFET, causing
additional power loss. The more frequent transient event, the more
power loss dissipated on the low-side MOSFET. The MOSFET may
face severe thermal stress when transient events happen at a high
repetitive rate. User discretion is advised when this function is
enabled.
Key Component Selection
RBIAS
The ISL62882 uses a resistor (1% or better tolerance is
recommended) from the RBIAS pin to GND to establish highly
accurate reference current sources inside the IC. Refer to Table 2
to select the resistance according to desired configuration. Do not
connect any other components to this pin. Do not connect any
capacitor to the RBIAS pin as it will create instability.
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Care should be taken in layout that the resistor is placed very
close to the RBIAS pin and that a good quality signal ground is
connected to the opposite side of the RBIAS resistor.
Ris and Cis
As Figures 1 thru 4 show, the ISL62882 needs the Ris - Cis
network across the ISUM+ and the ISUM- pins to stabilize the
droop amplifier. The preferred values are Ris = 82.5Ω and
Cis = 0.01µF. Slight deviations from the recommended values
are acceptable. Large deviations may result in instability.
Inductor DCR Current-Sensing Network
Phase1
Phase2
Rsum
ISUM+
Rsum
L
L
Rntcs
Rp
DCR
DCR
Cn Vcn
Rntc
Ro
Ri
ISUM-
( R ntcs + R ntc ) × R p
R ntcnet = --------------------------------------------------R ntcs + R ntc + R p
(EQ. 15)
s
1 + -----ωL
A cs ( s ) = ---------------------s
1 + -----------ω sns
(EQ. 16)
DCR
ω L = -----------L
(EQ. 17)
1
ω sns = -----------------------------------------------------R sum
R ntcnet × -------------N
----------------------------------------- × C n
R sum
R ntcnet + -------------N
(EQ. 18)
where N is the number of phases.
Transfer function Acs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC Rntc
values decreases as its temperature decreases. Proper
selections of Rsum, Rntcs, Rp and Rntc parameters ensure that
VCn represent the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC network
and the Rsum resistors form a voltage divider, Vcn is always a
fraction of the inductor DCR voltage. It is recommended to have a
higher ratio of Vcn to the inductor DCR voltage, so the droop circuit
has higher signal level to work with.
Ro
Io
FIGURE 17. DCR CURRENT-SENSING NETWORK
Figure 17 shows the inductor DCR current-sensing network for a
2-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in Rsum and
Ro connected to the pads to accurately sense the inductor current by
sensing the DCR voltage drop. The Rsum and Ro resistors are
connected in a summing network as shown, and feed the total
current information to the NTC network (consisting of Rntcs, Rntc
and Rp) and capacitor Cn. Rntc is a negative temperature coefficient
(NTC) thermistor, used to temperature-compensate the inductor
DCR change.
The inductor output side pads are electrically shorted in the
schematic, but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10Ω Ro to create quality signals. Since Ro value is much
smaller than the rest of the current sensing circuit, the following
analysis will ignore it for simplicity.
The summed inductor current information is presented to the
capacitor Cn. Equations 14 thru 18 describe the
frequency-domain relationship between inductor total current
Io(s) and Cn voltage VCn(s).
⎛
⎞
R ntcnet
⎜
DCR⎟
-------------------------------------------------V Cn ( s ) = ⎜
×
⎟ × I ( s ) × A cs ( s )
N ⎟ o
R sum
⎜
⎝ R ntcnet + ------------⎠
N
21
A typical set of parameters that provide good temperature
compensation are: Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ
and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
VCn(s) also needs to represent real-time Io(s) for the controller to
achieve good transient response. Transfer function Acs(s) has a
pole ωsns and a zero ωL. One needs to match ωL and ωsns so
Acs(s) is unity gain at all frequencies. By forcing ωL equal to ωsns
and solving for the solution, Equation 19 gives Cn value.
L
C n = -----------------------------------------------------------R sum
R ntcnet × -------------N
----------------------------------------- × DCR
R sum
R ntcnet + -------------N
(EQ. 19)
(EQ. 14)
FN6890.4
June 21, 2011
ISL62882, ISL62882B
io
io
iL
Vo
Vo
RING
BACK
FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM
io
ISUM+
Vo
Rntcs
Cn.1
Cn.2 Vcn
Rp
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
Rntc
Rn
OPTIONAL
ISUM-
Ri
io
Rip
Cip
OPTIONAL
Vo
FIGURE 20. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
For example, given N = 2, Rsum = 3.65kΩ, Rp = 11kΩ,
Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.88mΩ and L = 0.36µH,
Equation 19 gives Cn = 0.294µF.
Assuming the compensator design is correct, Figure 18 shows the
expected load transient response waveforms if Cn is correctly
selected. When the load current Icore has a square change, the
output voltage Vcore also has a square response.
If Cn value is too large or too small, VCn(s) will not accurately
represent real-time Io(s) and will worsen the transient response.
Figure 19 shows the load transient response when Cn is too
small. Vcore will sag excessively upon load insertion and may
create a system failure. Figure 20 shows the transient response
when Cn is too large. Vcore is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
22
FIGURE 22. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 21 shows the output voltage ring back problem during load
transient response. The load current io has a fast step change, but
the inductor current iL cannot accurately follow. Instead, iL
responds in first order system fashion due to the nature of current
loop. The ESR and ESL effect of the output capacitors makes the
output voltage Vo dip quickly upon load current change. However,
the controller regulates Vo according to the droop current idroop,
which is a real-time representation of iL; therefore it pulls Vo back
to the level dictated by iL, causing the ring back problem. This
phenomenon is not observed when the output capacitor have very
low ESR and ESL, such as all ceramic capacitors.
Figure 22 shows two optional circuits for reduction of the ring back.
Cn is the capacitor used to match the inductor time constant. It
usually takes the parallel of two (or more) capacitors to get the
desired value. Figure 22 shows that two capacitors Cn.1 and Cn.2
are in parallel. Resistor Rn is an optional component to reduce
the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired
Cn capacitance. At the beginning of io change, the effective
capacitance is less because Rn increases the impedance of the
Cn.1 branch. As Figure 19 explains, Vo tends to dip when Cn is too
small, and this effect will reduce the Vo ring back. This effect is
more pronounced when Cn.1 is much larger than Cn.2. It is also
more pronounced when Rn is bigger. However, the presence of
Rn increases the ripple of the Vn signal if Cn.2 is too small. It is
recommended to keep Cn.2 greater than 2200pF. Rn value
usually is a few ohms. Cn.1, Cn.2 and Rn values should be
determined through tuning the load transient response
waveforms on an actual board.
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Rip and Cip form an R-C branch in parallel with Ri, providing a
lower impedance path than Ri at the beginning of io change. Rip
and Cip do not have any effect at steady state. Through proper
selection of Rip and Cip values, idroop can resemble io rather than
iL, and Vo will not ring back. The recommended value for Rip is
100Ω. Cip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for Cip is 100pF~2000pF. However, it
should be noted that the Rip -Cip branch may distort the idroop
waveform. Instead of being triangular as the real inductor
current, idroop may have sharp spikes, which may adversely
affect idroop average value detection and therefore may affect
OCP accuracy. User discretion is advised.
Resistor Current-Sensing Network
PHASE1
Overcurrent Protection
Refer to Equation 1 on page 16 and Figures 12, 17 and 23;
resistor Ri sets the droop current Idroop. Table 4 shows the
internal OCP threshold. It is recommended to design Idroop
without using the Rcomp resistor.
For example, the OCP threshold is 40µA for 2-phase solution. We
will design Idroop to be 34.3µA at full load, so the OCP trip level is
1.16x of the full load current.
For inductor DCR sensing, Equation 23 gives the DC relationship
of Vcn(s) and Io(s).
⎛
⎞
R ntcnet
⎜
DCR⎟
V Cn = ⎜ ----------------------------------------- × ------------⎟ × I o
R sum
N ⎟
⎜
⎝ R ntcnet + ------------⎠
N
(EQ. 23)
PHASE2
Substitution of Equation 23 into Equation 1 gives Equation 24:
L
L
DCR
DCR
R ntcnet
2
DCR
I droop = ----- × ----------------------------------------- × ------------ × I o
R sum
Ri
N
R ntcnet + -------------N
Therefore:
RSUM
ISUM+
RSUM
RSEN
(EQ. 24)
RSEN
VCN
RO
CN
RI
ISUM-
2R ntcnet × DCR × I o
R i = -------------------------------------------------------------------------------R sum
N × ⎛ R ntcnet + --------------⎞ × I droop
⎝
N ⎠
Substitution of Equation 15 and application of the OCP condition
in Equation 25 gives Equation 26:
( R ntcs + R ntc ) × R p
2 × --------------------------------------------------- × DCR × I omax
R ntcs + R ntc + R p
R i = ------------------------------------------------------------------------------------------------------------------------(
R
⎛ ntcs + R ntc ) × R p R sum⎞
N × ⎜ --------------------------------------------------- + --------------⎟ × I droopmax
N ⎠
⎝ R ntcs + R ntc + R p
RO
IO
FIGURE 23. RESISTOR CURRENT-SENSING NETWORK
Figure 23 shows the resistor current-sensing network for a
2-phase solution. Each inductor has a series current-sensing
resistor Rsen. Rsum and Ro are connected to the Rsen pads to
accurately capture the inductor current information. The Rsum
and Ro resistors are connected to capacitor Cn. Rsum and Cn
form a filter for noise attenuation. Equations 20 thru 22 give
VCn(s) expression
R sen
V Cn ( s ) = ------------ × I o ( s ) × A Rsen ( s )
N
1
A Rsen ( s ) = ---------------------s
1 + -----------ω sns
(EQ. 25)
(EQ. 26)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given N = 2,
Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ,
DCR = 0.88mΩ, Iomax = 51A and Idroopmax = 34.3µA,
Equation 26 gives Ri = 998Ω.
For resistor sensing, Equation 27 gives the DC relationship of
Vcn(s) and Io(s).
R sen
V Cn = ------------ × I o
N
(EQ. 27)
(EQ. 20)
Substitution of Equation 27 into Equation 1 gives Equation 28:
(EQ. 21)
2 R sen
I droop = ----- × ------------ × I o
N
Ri
(EQ. 28)
Therefore
1
ω Rsen = --------------------------R sum
-------------- × C n
N
(EQ. 22)
Transfer function ARsen(s) always has unity gain at DC. Currentsensing resistor Rsen value will not have significant variation
over-temperature, so there is no need for the NTC network.
The recommended values are Rsum = 1kΩ and Cn = 5600pF.
23
2R sen × I o
R i = --------------------------N × I droop
(EQ. 29)
Substitution of Equation 29 and application of the OCP condition
in Equation 25 gives Equation 30:
2R sen × I omax
R i = -------------------------------------N × I droopmax
(EQ. 30)
FN6890.4
June 21, 2011
ISL62882, ISL62882B
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given N = 2,
Rsen = 1mΩ, Iomax = 51A and Idroopmax = 34.3µA, Equation 30
gives Ri = 1.487kΩ.
A resistor from COMP to GND can adjust the internal OCP
threshold, providing another dimension of fine-tune flexibility.
Table 4 shows the detail. It is recommended to scale Idroop such
that the default OCP threshold gives approximately the desired
OCP level, then use Rcomp to fine tune the OCP level if necessary.
Load Line Slope
Refer to Figure 12.
For inductor DCR sensing, substitution of Equation 24 into
Equation 2 gives the load line slope expression:
2R droop
R ntcnet
V droop
DCR
LL = ------------------ = ---------------------- × ----------------------------------------- × -----------N
Io
Ri
R sum
R ntcnet + -------------N
(EQ. 31)
For resistor sensing, substitution of Equation 28 into Equation 2
gives the load line slope expression:
2R sen × R droop
V droop
LL = ------------------ = ----------------------------------------N × Ri
Io
V Rimon × R droop
R imon = -------------------------------------------3I o × LL
(EQ. 37)
For example, given LL = 1.9mΩ, Rdroop = 2.825kΩ,
VRimon = 963mV at Iomax = 51A, Equation 37 gives
Rimon = 9.358kΩ.
A capacitor Cimon can be paralleled with Rimon to filter the IMON
pin voltage. The RimonCimon time constant is the user’s choice. It
is recommended to have a time constant long enough such that
switching frequency ripples are removed.
Compensator
Figure 18 shows the desired load transient response waveforms.
Figure 24 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Zout(s). If Zout(s) is equal to the
load line slope LL, i.e., constant output impedance, in the entire
frequency range, Vo will have square response when Io has a
square change.
(EQ. 32)
Zout(s) = LL
Substitution of Equation 25 and rewriting Equation 31, or
substitution of Equation 29 and rewriting Equation 32 give the
same result in Equation 33:
Io
R droop = ---------------- × LL
I droop
Rewriting Equation 36 and application of full load condition gives
Equation 37:
VID
VR
i
o
LOAD
V
o
(EQ. 33)
One can use the full load condition to calculate Rdroop. For
example, given Iomax = 51A, Idroopmax = 34.3µA and
LL = 1.9mΩ, Equation 33 gives Rdroop = 2.825kΩ.
It is recommended to start with the Rdroop value calculated by
Equation 33, and fine tune it on the actual board to get accurate
load line slope. One should record the output voltage readings at
no load and at full load for load line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Current Monitor
Refer to Equation 13 for the IMON pin current expression.
Refer to Figures 1 and 2, the IMON pin current flows through
Rimon. The voltage across Rimon is expressed in Equation 34:
V Rimon = 3 × I droop × R imon
(EQ. 34)
Rewriting Equation 33 gives Equation 35:
Io
I droop = ------------------ × LL
R droop
(EQ. 35)
Substitution of Equation 35 into Equation 34 gives Equation 36:
3I o × LL
V Rimon = --------------------- × R imon
R droop
(EQ. 36)
FIGURE 24. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network, so the
VR achieves constant output impedance as a stable system.
Figure 27 shows a screenshot of the spreadsheet.
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 25 conceptually
shows T1(s) measurement set-up and Figure 26 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
current, multiplies it by a gain of the load line slope, then adds it
on top of the sensed output voltage and feeds it to the
compensator. T(1) is measured after the summing node, and T2(s)
is measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can be actually measured on an ISL62882 regulator.
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s) and has
more meaning of system stability.
T2(s) is the voltage loop gain with closed droop loop. It has more
meaning of output voltage response.
Design the compensator to get stable T1(s) and T2(s) with
sufficient phase margin, and output impedance equal or smaller
than the load line slope.
24
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Vo
L
Q1
Vin
Q1
GATE Q2
DRIVER
io
Cout
VIN
GATE Q2
DRIVER
COUT
Ω
20
Ω
COMP
COMP
VID
CHANNEL B
CHANNEL A
ISOLATION
TRANSFORMER
CHANNEL A
CHANNEL B
NETWORK
ANALYZER EXCITATION OUTPUT
FIGURE 25. LOOP GAIN T1(s) MEASUREMENT SET-UP
25
20
EA
MOD.
EA
MOD.
I
O
LOAD LINE SLOPE
LOAD LINE SLOPE
LOOP GAIN =
VO
L
CHANNEL B
LOOP GAIN =
CHANNEL A
VID
ISOLATION
TRANSFORMER
CHANNEL A
CHANNEL B
NETWORK
ANALYZER EXCITATION OUTPUT
FIGURE 26. LOOP GAIN T2(s) MEASUREMENT SET-UP
FN6890.4
June 21, 2011
Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators for IMVP-6.5
Jia Wei, [email protected], 919-405-3605
Attention: 1. "Analysis ToolPak" Add-in is required. To turn on, go to Tools--Add-Ins, and check "Analysis ToolPak".
2. Green cells require user input
Compensator Parameters
Operation Parameters
Controller Part Number: ISL6288x
§
s · §
s ·
¸ ˜ ¨1 ¸
KZi ˜ Zi ˜ ¨¨1 Phase Number:
2
2Sf z1 ¸¹ ¨©
2Sf z 2 ¸¹
©
AV ( s )
Vin:
12 volts
§
s ·¸ §¨
s ·¸
Vo:
1.15 volts
s ˜ ¨1 ˜ 1
¨
2Sf p1 ¹¸ ©¨
2Sf p 2 ¹¸
©
Full Load Current:
50 Amps
26
87
3
470
4.5
0.6
30
10
3
3
300
0.36
0.9
1.9
33.1
%
uF
m:
nH
Recommended Value
R1
2.870 k :
R2
387.248 k :
R3
0.560 k :
C1
188.980 pF
C2
498.514 pF
C3
32.245 pF
uF
m:
nH
kHz
uH
m:
m:
uA
User-Selected Value
R1
2.87 k :
R2
412 k :
R3
0.562 k :
C1
150 pF
C2
390 pF
C3
32 pF
Use User-Selected Value (Y/N)?
N
Performance and Stability
T1 Bandwidth: 190kHz
T2 Bandwidth: 52kHz
T1 Phase Margin: 63.4°
T2 Phase Margin: 94.7°
Changing the settings in red requires deep understanding of control loop design
Place the 2nd compensator pole fp2 at:
1.9 xfs (Switching Frequency)
Tune Ki to get the desired loop gain bandwidth
Tune the compensator gain factor Ki:
(Recommended Ki range is 0.8~2)
Loop Gain, Gain Curve
7V
7V
Recommended Value
Cn
0.294 uF
Ri 1014.245 :
(
(
(
)UHTXHQF\+]
(
Loop Gain, Phase Curve
7V
7V
(
(
(
)UHTXHQF\+]
(
(
(
(
(
)UHTXHQF\+]
(
(
(
(
(
3KDVHGHJUHH
(
3KDVHGHJUHH
Output Impedance, Gain Curve
0DJQLWXGHPRKP
*DLQG%
1.15
Output Impedance, Phase Curve
(
(
(
(
)UHTXHQF\+]
(
Operation Parameters
Inductor DCR
0.88 m :
Rsum
3.65 k :
Rntc
10 k :
Rntcs
2.61 k :
Rp
11 k :
(
FN6890.4
June 21, 2011
FIGURE 27. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET
User Selected Value
Cn
0.294 uF
Ri
1000 :
ISL62882, ISL62882B
Estimated Full-Load Efficiency:
Number of Output Bulk Capacitors:
Capacitance of Each Output Bulk Capacitor:
ESR of Each Output Bulk Capacitor:
ESL of Each Output Bulk Capacitor:
Number of Output Ceramic Capacitors:
Capacitance of Each Output Ceramic Capacitor:
ESR of Each Output Ceramic Capacitor:
ESL of Each Output Ceramic Capacitor:
Switching Frequency:
Inductance Per Phase:
CPU Socket Resistance:
Desired Load-Line Slope:
Desired ISUM- Pin Current at Full Load:
(This sets the over-current protection level)
Current Sensing Network Parameters
ISL62882, ISL62882B
Optional Slew Rate Compensation Circuit For
1-Tick VID Transition
where Cout is the total output capacitance.
In the mean time, the Rvid-Cvid branch current Ivid time domain
expression is:
–t
------------------------------⎞
dV fb ⎛
R
×C
I vid ( t ) = C vid × ------------ × ⎜ 1 – e vid vid⎟
⎜
⎟
dt
⎝
⎠
Rdroop
Vcore
Rvid Cvid
OPTIONAL
FB
It is desired to let Ivid(t) cancel Idroop_vid(t). So there are:
Ivid
dV fb
C out × LL dV core
C vid × ------------ = ------------------------ × -----------------dt
dt
R droop
Idroop_vid
E/A
COMP
Σ VDACDAC
VIDs
VID<0:6>
RTN
X1
INTERNAL
TO IC
(EQ. 39)
VSSSENSE
VSS
(EQ. 40)
and:
(EQ. 41)
R vid × C vid = C out × LL
The result is expressed in Equation 42:
(EQ. 42)
R vid = R droop
and:
VID<0:6>
dV core
C out × LL ----------------dt
C vid = ------------------------ × -----------------R droop
dV fb
-----------dt
Vfb
(EQ. 43)
Ivid
For example: given LL = 1.9mΩ, Rdroop = 2.87kΩ, Cout = 1710µF,
dVcore/dt = 5mV/µs and dVfb/dt = 15mV/µs, Equation 42 gives
Rvid = 2.87kΩ and Equation 43 gives Cvid = 377pF.
Vcore
It’s recommended to select the calculated Rvid value and start
with the calculated Cvid value and tweak it on the actual board to
get the best performance.
Idroop_vid
FIGURE 28. OPTIONAL SLEW RATE COMPENSATION CIRCUIT
FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate. For example, the DAC may change a tick
(12.5mV) per 2.5µs per, controlling output voltage Vcore slew
rate at 5mV/µs.
Figure 28 shows the waveforms of 1-tick VID transition. During
1-tick VID transition, the DAC output changes at approximately
15mV/µs slew rate, but the DAC cannot step through multiple
VIDs to control the slew rate. Instead, the control loop response
speed determines Vcore slew rate. Ideally, Vcore will follow the FB
pin voltage slew rate. However, the controller senses the inductor
current increase during the up transition, as the Idroop_vid
waveform shows, and will droop the output voltage Vcore
accordingly, making Vcore slew rate slow. Similar behavior occurs
during the down transition.
To control Vcore slew rate during 1-tick VID transition, one can
add the Rvid-Cvid branch, whose current Ivid cancels Idroop_vid.
When Vcore increases, the time domain expression of the
induced Idroop change is
–t
-------------------------⎞
C out × LL dV core ⎛
C
× LL⎟
⎜
out
I droop ( t ) = ------------------------ × ------------------ × 1 – e
⎜
⎟
dt
R droop
⎝
⎠
27
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
Rvid - Cvid network is between the virtual ground and the real
ground, and hence has no effect on transient response.
Voltage Regulator Thermal Throttling
54µA
64µA
VR_TT#
SW1
NTC
+
VNTC
-
+
RNTC
Rs
1.24V
SW2
1.20V
INTERNAL TO
ISL62882
FIGURE 29. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE OF THE ISL62882
(EQ. 38)
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Figure 29 shows the thermal throttling feature with hysteresis.
An NTC network is connected between the NTC pin and GND. At
low temperature, SW1 is on and SW2 connects to the 1.20V side.
The total current flowing out of the NTC pin is 60µA. The voltage
on NTC pin is higher than threshold voltage of 1.20V and the
comparator output is low. VR_TT# is pulled up by the external
resistor.
When temperature increases, the NTC thermistor resistance
decreases so the NTC pin voltage drops. When the NTC pin
voltage drops below 1.20V, the comparator changes polarity and
turns SW1 off and throws SW2 to 1.24V. This pulls VR_TT# low
and sends the signal to start thermal throttle. There is a 6µA
current reduction on NTC pin and 40mV voltage increase on
threshold voltage of the comparator in this state. The VR_TT#
signal will be used to change the CPU operation and decrease
the power consumption. When the temperature drops down, the
NTC thermistor voltage will go up. If NTC voltage increases to
above 1.24V, the comparator will flip back. The external
resistance difference in these two conditions is shown in
Equation 44:
Current Balancing
Refer to Figures 1 and 2. The ISL62882 achieves current
balancing through matching the ISEN pin voltages. Rs and Cs
form filters to remove the switching ripple of the phase node
voltages. It is recommended to use rather long RsCs time
constant such that the ISEN voltages have minimal ripple and
represent the DC current flowing through the inductors.
Recommended values are Rs = 10kΩ and Cs = 0.22µF.
Layout Guidelines
Table 6 shows the layout considerations. The designators refer to
the reference design shown in Figure 31.
TABLE 6. LAYOUT CONSIDERATION
PIN
NAME
LAYOUT CONSIDERATION
EP
GND
Create analog ground plane underneath the
controller and the analog signal processing
components. Don’t let the power ground plane
overlap with the analog ground plane. Avoid noisy
planes/traces (e.g.: phase node) from crossing
over/overlapping with the analog plane.
1
PGOOD
No special consideration
One needs to properly select the NTC thermistor value such that
the required temperature hysteresis correlates to 2.96kΩ
resistance change. A regular resistor may need to be in series with
the NTC thermistor to meet the threshold voltage values.
2
PSI#
No special consideration
3
RBIAS
Place the RBIAS resistor (R16) in general proximity
of the controller. Low impedance connection to the
analog ground plane.
For example, given Panasonic NTC thermistor with B = 4700, the
resistance will drop to 0.03322 of its nominal at +105°C, and
drop to 0.03956 of its nominal at +100°C. If the required
temperature hysteresis is +105°C to +100°C, the required
resistance of NTC will be as shown in Equation 45:
4
VR_TT#
No special consideration
5
NTC
The NTC thermistor (R9) needs to be placed close
to the thermal source that is monitor to determine
thermal throttling. Usually it’s placed close to
phase-1 high-side MOSFET.
6
VW
Place the capacitor (C4) across VW and COMP in
close proximity of the controller
Therefore, a larger value thermistor such as 470k NTC should be
used.
7
COMP
8
FB
Place the compensator components (C3, C5, C6
R7, R11, R10 and C11) in general proximity of the
controller.
At +105°C, 470kΩ NTC resistance becomes
(0.03322 × 470kΩ) = 15.6kΩ. With 60µA on the NTC pin, the
voltage is only (15.6kΩ × 60µA) = 0.937V. This value is much
lower than the threshold voltage of 1.20V. Therefore, a regular
resistor needs to be in series with the NTC. The required
resistance can be calculated by Equation 46:
9
FB2
10
ISEN2
A capacitor (C9) decouples it to VSUM-. Place it in
general proximity of the controller.
11
ISEN1
A capacitor (C10) decouples it to VSUM-. Place it in
general proximity of the controller.
12
VSEN
13
RTN
Place the VSEN/RTN filter (C12, C13) in close
proximity of the controller for good decoupling.
1.24V 1.20V
--------------- – --------------- = 2.96k
54μA 60μA
(EQ. 44)
2.96kΩ
------------------------------------------------------- = 467kΩ
( 0.03956 – 0.03322 )
(EQ. 45)
1.20V
--------------- – 15.6kΩ = 4.4kΩ
60μA
(EQ. 46)
4.42k is a standard resistor value. Therefore, the NTC branch
should have a 470k NTC and 4.42k resistor in series. The part
number for the NTC thermistor is ERTJ0EV474J. It is a 0402
package. NTC thermistor will be placed in the hot spot of the
board.
28
FN6890.4
June 21, 2011
ISL62882, ISL62882B
TABLE 6. LAYOUT CONSIDERATION (Continued)
TABLE 6. LAYOUT CONSIDERATION (Continued)
PIN
NAME
LAYOUT CONSIDERATION
PIN
NAME
LAYOUT CONSIDERATION
14
ISUM-
26
LGATE2
15
ISUM+
Place the current sensing circuit in general
proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to phase-1
inductor (L1) so it senses the inductor temperature
correctly.
Each phase of the power stage sends a pair of
VSUM+ and VSUM- signals to the controller. Run
these two signals traces in parallel fashion with
decent width (>20mil).
IMPORTANT: Sense the inductor current by routing
the sensing circuit to the inductor pads.
Route R63 and R71 to the phase-1 side pad of
inductor L1. Route R88 to the output side pad of
inductor L1.
Route R65 and R72 to the phase-2 side pad of
inductor L2. Route R90 to the output side pad of
inductor L2.
If possible, route the traces on a different layer
from the inductor pad layer and use vias to
connect the traces to the center of the pads. If no
via is allowed on the pad, consider routing the
traces into the pads from the inside of the inductor.
The following drawings show the two preferred
ways of routing current sensing traces.
27
VSSP2
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing VSSP2 to the phase-2 lowside MOSFET (Q5 and Q1) source pins instead of
general power ground plane for better
performance.
28
PHASE2
29
UGATE2
30
BOOT2
Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing over or
getting close.
31~37
VID0~6
No special consideration.
38
VR_ON
No special consideration.
Inductor
Inductor
39
40
Current-Sensing
Traces
DPRSLPVR No special consideration.
CLK_EN#
No special consideration.
Other Phase Node Minimize phase node copper area. Don’t let the
phase node copper overlap with/getting close to
other sensitive traces. Cut the power ground plane
to avoid overlapping with phase node copper.
Other
Vias
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing PHASE2 trace to the phase-2
high-side MOSFET (Q4 and Q10) source pins
instead of general phase-2 node copper.
Minimize the loop consisting of input capacitor,
high-side MOSFETs and low-side MOSFETs
(e.g., C27, C33, Q2, Q8, Q3 and Q9).
Current-Sensing
Traces
16
VDD
A capacitor (C16) decouples it to GND. Place it in
close proximity of the controller.
17
VIN
A capacitor (C17) decouples it to GND. Place it in
close proximity of the controller.
18
IMON
Place the filter capacitor (C21) close to the CPU.
19
BOOT1
Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing over or
getting close.
20
UGATE1
21
PHASE1
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing PHASE1 trace to the phase-1
high-side MOSFET (Q2 and Q8) source pins instead
of general phase-1 node copper.
22
VSSP1
23
LGATE1a
24
LGATE1b
25
VCCP
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing VSSP1 to the phase-1
low-side MOSFET (Q3 and Q9) source pins instead
of general power ground plane for better
performance.
A capacitor (C22) decouples it to GND. Place it in
close proximity of the controller.
29
FN6890.4
June 21, 2011
8
7
IN
C3
R10
15PF
100PF
10UF
C27
10UF
C33
C54
VCORE
22UF
C55
22UF
C56
22UF
C40
22UF
C41
22UF
C59
C60
22UF
OUT
22UF
C61
Q9
0.88UH
2.3MOHM
22UF
Q3
+5V
IRF7832
C52
IN
VCCP
ISL62882HRZ
COMP
1UF
LGATE2
IRF7832
470UF
4MOHM
VW
L1
VSSP2
U6
NTC
C
LGATE1B
LGATE1A
FB2
VSSP1
ISEN2
2.37K 270PF
R7
C24
PHASE2
VR_TT#
C11
56UF
UGATE2
RBIAS
DNP DNP
------------
Q2
BOOT2
PSI#
R16
----
R12
499
-------
------------
C4
1000PF
C6
IRF7821
PGOOD
47.5K
------R8
R9
IN
PHASE1
R11
422K
6.98K
EP
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT
UGATE1
C83 R110
DNP DNP
--------
--------
----
IN
VIN
C22
OUT
IN
FB
OPTIONAL
----
1
R20
0
R37
+5V
VIN
IN
R40
IN
0
0.22UF
R18
1UF
C17
IN
1
C16
VSSSENSE
C13
----
B
R56
C30
0
0.22UF
OUT
IMON
IN
VSSSENSE
0.01UF
IN
OPTIONAL
----
C21
10
R50
VCCSENSE
R17
22.6K
IN
330PF
1000PF -----
VCORE
----C12
B
LAYOUT
R63
10K 2.61K
NTC
R41
-----> R42
11K
R38
DNP DNP
-----------OPTIONAL
0.1UF
----
C20
R30
3.01K
-----------C81 R109
----
0.15UF
C18
0.056UF
C82
R26
C15
A
0.01UF 82.5
10
3.65K
ROUTE LGATE TRACE IN PARALLEL
WITH THE VSSP TRACE GOING TO
THE SOURCE OF Q3
PLACE NEAR L1
TITLE: ISL62881
DATE:
ENGINEER:
PAGE:
GPU REFERENCE DESIGN
1-PHASE, DCR SENSING
FIGURE 30. 1-PHASE GPU APPLICATON REFERENCE DESIGN
8
7
6
5
NOTE:
ROUTE UGATE TRACE IN PARALLEL
WITH THE PHASE TRACE GOING TO
THE SOURCE OF Q2
4
3
JIA WEI
2
3/16/2009
1 OF 1
1
A
ISL62882, ISL62882B
----
10K
DNP
------R6
------R4
C
2
D
OPTIONAL ----OPTIONAL
---- VR_TT#
3
IN
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
30
PGOOD
+1.1V
4
IN
R19
D
5
IN
IN
IN
IN
IN
IN
IN
1.91K
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VR_ON
DPRSLPVR
+3.3V
6
FN6890.4
June 21, 2011
5
4
VIN
0.1UF
----
1200PF 100
----------OPTIONAL
IMON
C44
DNP
C57
470UF
C52
470UF
C39
470UF
10UF
10UF
10UF
10UF
C56
C64
C55
C63
C48
10UF
10UF
10UF
10UF
C54
C62
C47
10UF
10UF
10UF
10UF
C53
C61
C43
10UF
10UF
10UF
10UF
C50
C60
C42
10UF
10UF
10UF
10UF
C41
C40
10UF
C49
10UF
C59
10UF
C65
10UF
1
VSUM-
C70
C78
10UF
C69
C75
C68
C74
10UF
C67
C73
10UF
C66
C72
10UF
VSUM-
C71
ISEN1
10UF
10K
R90
ISEN2
R72
R65
3.65K
VSUM+
VSUM+
1
C
B
IN
VSSSENSE
IN
VSUM+
ROUTE UGATE1 TRACE IN PARALLEL
WITH THE PHASE1 TRACE GOING TO
THE SOURCE OF Q2 AND Q8
ROUTE LGATE1 TRACE IN PARALLEL
WITH THE VSSP1 TRACE GOING TO
THE SOURCE OF Q3 AND Q9
SAME RULE APPLIES TO OTHER PHASES
IN
VSUM-
PLACE NEAR L1
TITLE:
ISL62882 REFERENCE DESIGN
2-PHASE, DCR SENSING
ENGINEER:
8
10UF
10UF
10UF
10UF
C33
C27
OUT
0.01UF
R50
R41
-----> R42
R38
11K
1UF
C17
0
+5V
VIN
C20
R26
IN
R30
1K
----------C81 R109
----
10
C82
C16
IN
R18
C15
----
0.01UF 82.5
----C12
10
IN
C13
VSSSENSE
OPTIONAL
----
R17
IN
R40
0.22UF
1
0.33UF
R20
1000PF 330PF
---------
IN
VCCSENSE
Q9
VCORE
LAYOUT NOTE:
R37
0
VCORE
Q3
1UF
EP
C18
C10
C9
OPTIONAL
----ISEN2 IN
ISEN1 IN
0.22UF
0.36UH
IRF7832
PHASE1
C22
2.87K
0
IRF7832
VSSP1
ISEN2
R11
412K
C30
LGATE1A
FB2
10K 2.61K
NTC
390PF
+5V
LGATE1B
C21
562
IN
VCCP
ISL62882HRZ
R56
10K
R88
VW
L1
VSSP2
LGATE2
9.31K
C11
0.22UF
R7
R10
0.22UF
10PF
NTC
R71
DNP
PHASE2
U6
R63
DNP
IRF7821
Q8
3.65K
VR_TT#
RBIAS
0.047UF
C4
1000PF
8.06K
DNP
------R6
------R4
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
R19
R12
499
147K
R9
IRF7821
Q2
OUT
560PF 2.87K
-------------
0.36UH
IRF7832
Q11
OUT
------------C83 R110
IRF7832
Q5
OUT
7
6
5
4
FIGURE 31. 2-PHASE CPU APPLICATION REFERENCE DESIGN
3
JIA WEI
2
DATE:
JULY 2009
PAGE:
1 OF 1
1
A
ISL62882, ISL62882B
R8
BOOT2
FB
C6
A
0.22UF
UGATE2
COMP
22PF
C3
C31
0
OUT
R16
PSI#
C5
150PF
R57
OUT
B
D
OUT
PGOOD
VR_TT# OUT
---- OPTIONAL
----
IRF7821
Q10
OUT
IN
IN
C
----
IRF7821
Q4
1.91K
PGOOD OUT
PSI#
+1.1V
C28
R23
IN
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT
UGATE1
31
+3.3V
1
L2
1.91K
D
2
IN
C24
VID0 IN
VID1 IN
VID2 IN
VID3 IN
VID4 IN
VID5 IN
VID6 IN
VR_ON IN
DPRSLPVR IN
CLK_EN# OUT
3
10UF
C34
6
56UF
7
56UF
C25
8
FN6890.4
June 21, 2011
ISL62882, ISL62882B
1-Phase GPU Application Reference Design Bill of Materials
QTY
REFERENCE
VALUE
DESCRIPTION
MANUFACTURER
1
C11
270pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00271-16V10
SM0603
1
C12
330pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00331-16V10
SM0603
1
C13
1000pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00102-16V10
SM0603
1
C15
0.01µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00103-16V10
SM0603
2
C16,C22
1µF
Multilayer Cap, 16V, 20%
GENERIC
H1045-00105-16V20
SM0603
1
C18
0.15µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00154-16V10
SM0603
1
C20
0.1µF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00104-16V10
SM0603
3
C17, C21, C30
0.22µF
Multilayer Cap, 25V, 10%
GENERIC
H1045-00224-25V10
SM0603
1
C24
56µF
Radial SP Series Cap, 25V, 20%
SANYO
25SP56M
CASE-CC
2
C27,C33
10µF
Multilayer Cap, 25V, 20%
GENERIC
H1065-00106-25V20
SM1206
1
C3
100pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00101-16V10
SM0603
1
C52
470µF
SPCAP, 2V, 4MΩ
POLYMER CAP, 2.5V, 4.5MΩ
PANASONIC
EEXSX0D471E4
T520V477M2R5A(1)E4R5-6666
1
C4
1000pF Multilayer Cap, 16V, 10%
8
C40, C41, C54-C56,
C59-C61
10µF
1
C6
15pF
1
C82
0
C81, C83
1
L1
KEMET
PART NUMBER
PACKAGE
GENERIC
H1045-00102-16V10
SM0603
Multilayer Cap, 6.3V, 20%
MURATA
PANASONIC
TDK
GRM21BR61C106KE15L
ECJ2FB0J106K
C2012X5R0J106K
SM0805
Multilayer Cap, 16V, 10%
GENERIC
H1045-00150-16V10
SM0603
0.056µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00563-16V10
SM0603
MPC1040LR88
10mmx10mm
DNP
0.88µH Inductor, Inductance 20%,
DCR 7%
NEC-TOKIN
1
Q2
N-Channel Power MOSFET
IR
IRF7821
PWRPAKSO8
2
Q3, Q9
N-Channel Power MOSFET
IR
IRF7832
PWRPAKSO8
1
R10
2.37k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02371-1/16W1
SM0603
1
R11
6.98k
Thick Film Chip Resistor, 1%
GENERIC
H2511-06981-1/16W1
SM0603
1
R16
47.5k
Thick Film Chip Resistor, 1%
GENERIC
H2511-04752-1/16W1
SM0603
2
R17, R18
10
Thick Film Chip Resistor, 1%
GENERIC
H2511-00100-1/16W1
SM0603
1
R19
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R26
82.5
Thick Film Chip Resistor, 1%
GENERIC
H2511-082R5-1/16W1
SM0603
3
R20, R40, R56
0
Thick Film Chip Resistor, 1%
GENERIC
H2511-00R00-1/16W1
SM0603
1
R30
3.01k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03011-1/16W1
SM0603
1
R37
1
Thick Film Chip Resistor, 1%
GENERIC
H2511-01R00-1/16W1
SM0603
1
R38
11k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01102-1/16W1
SM0603
1
R41
2.61k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02611-1/16W1
SM0603
1
R42
PANASONIC
ERT-J1VR103J
SM0603
1
R50
GENERIC
H2511-02262-1/16W1
SM0603
10k NTC Thermistor, 10k NTC
22.6k
32
Thick Film Chip Resistor, 1%
FN6890.4
June 21, 2011
ISL62882, ISL62882B
1-Phase GPU Application Reference Design Bill of Materials (Continued)
QTY
REFERENCE
VALUE
DESCRIPTION
MANUFACTURER
PART NUMBER
PACKAGE
1
R6
10k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01002-1/16W1
SM0603
1
R63
3.65k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03651-1/16W1
SM0805
1
R7
412k
Thick Film Chip Resistor, 1%
GENERIC
H2511-04123-1/16W1
SM0603
0
R109, R110, R4, R8, R9
DNP
1
U6
IMVP-6.5 PWM Controller
INTERSIL
ISL62882HRTZ
QFN-40
2-Phase CPU Application Reference Design Bill of Materials
QTY
REFERENCE
VALUE
1
C11
390pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00391-16V10
SM0603
1
C12
330pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00331-16V10
SM0603
1
C13
1000pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00102-16V10
SM0603
2
C15, C21
0.01µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00103-16V10
SM0603
2
C16,C22
Multilayer Cap, 16V, 20%
GENERIC
H1045-00105-16V20
SM0603
1
C18
0.33µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00334-16V10
SM0603
1
C20
Multilayer Cap, 16V, 10%
GENERIC
H1045-00104-16V10
SM0603
5
C9, C10, C17, C30, C31
0.22µF Multilayer Cap, 25V, 10%
GENERIC
H1045-00224-25V10
SM0603
2
C24,C25
56µF
Radial SP Series Cap, 25V, 20%
SANYO
25SP56M
CASE-CC
4
C27,C28,C33,C34
10µF
Multilayer Cap, 25V, 20%
GENERIC
H1065-00106-25V20
SM1206
1
C3
150pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00151-16V10
SM0603
3
C39, C52, C57
470µF SPCAP, 2V, 4MΩ
POLYMER CAP, 2.5V, 4.5MΩ
PANASONIC
KEMET
EEXSX0D471E4
T520V477M2R5A(1)E4R5-6666
1
C4
1000pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00102-16V10
SM0603
30
C40-C43, C47-C50,
C53-C56, C59-C75, C78
10µF
Multilayer Cap, 6.3V, 20%
MURATA
PANASONIC
TDK
GRM21BR61C106KE15L
ECJ2FB0J106K
C2012X5R0J106K
SM0805
1
C5
22pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00220-16V10
SM0603
1
C6
10pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00100-16V10
SM0603
1
C81
1200pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00122-16V10
SM0603
1
C82
0.047µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00473-16V10
SM0603
1
C83
560pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00561-16V10
SM0603
2
L1, L2
0.36µH Inductor, Inductance 20%,
DCR 7%
NEC-TOKIN
PANASONIC
MPCH1040LR36
ETQP4LR36AFC
10mmx10mm
4
Q2, Q4, Q8, Q10
N-Channel Power MOSFET
IR
IRF7821
PWRPAKSO8
4
Q3, Q5, Q9, Q11
N-Channel Power MOSFET
IR
IRF7832
PWRPAKSO8
1µF
0.1µF
DESCRIPTION
MANUFACTURER
PART NUMBER
PACKAGE
1
R10
562
Thick Film Chip Resistor, 1%
GENERIC
H2511-05620-1/16W1
SM0603
1
R109
100
Thick Film Chip Resistor, 1%
GENERIC
H2511-01000-1/16W1
SM0603
1
R11
2.87k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02871-1/16W1
SM0603
1
R110
2.87k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02871-1/16W1
SM0603
1
R12
499
Thick Film Chip Resistor, 1%
GENERIC
H2511-04990-1/16W1
SM0603
1
R16
147k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01473-1/16W1
SM0603
33
FN6890.4
June 21, 2011
ISL62882, ISL62882B
2-Phase CPU Application Reference Design Bill of Materials (Continued)
QTY
REFERENCE
VALUE
DESCRIPTION
2
R17, R18
10
Thick Film Chip Resistor, 1%
GENERIC
H2511-00100-1/16W1
SM0603
3
R19, R71, R72
10k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01002-1/16W1
SM0603
1
R23
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R26
82.5
Thick Film Chip Resistor, 1%
GENERIC
H2511-082R5-1/16W1
SM0603
4
R20, R40, R56, R57
0
Thick Film Chip Resistor, 1%
GENERIC
H2511-00R00-1/16W1
SM0603
1
R30
1k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01001-1/16W1
SM0603
3
R37, R88, R90
1
Thick Film Chip Resistor, 1%
GENERIC
H2511-01R00-1/16W1
SM0603
1
R38
11k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01102-1/16W1
SM0603
1
R4
DNP
1
R41
2.61k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02611-1/16W1
SM0603
1
R42
PANASONIC
ERT-J1VR103J
SM0603
1
R50
9.31k
Thick Film Chip Resistor, 1%
GENERIC
H2511-09311-1/16W1
SM0603
1
R6
8.06k
Thick Film Chip Resistor, 1%
GENERIC
H2511-08061-1/16W1
SM0603
2
R63, R65
3.65k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03651-1/16W1
SM0805
2
R8, R9
DNP
1
R7
412k
Thick Film Chip Resistor, 1%
GENERIC
H2511-04123-1/16W1
SM0603
1
U6
IMVP-6.5 PWM Controller
INTERSIL
ISL62882HRTZ
QFN-40
10k NTC Thermistor, 10k NTC
34
MANUFACTURER
PART NUMBER
PACKAGE
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Typical Performance
92
1.10
90
1.08
1.06
86
1.04
84
VIN = 8V
82
VOUT (V)
EFFICIENCY (%)
88
VIN = 12V
80
78
VIN = 19V
1.02
1.00
0.98
76
0.96
74
0.94
72
70
0.92
0
5
10
15
20
25
30
IOUT (A)
35
40
45
50
0
55
FIGURE 32. 2-PHASE CCM EFFICIENCY, VID = 1.075V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
5
10
15
20
25
30 35
IOUT (A)
40
45
50
55
60
65
FIGURE 33. 2-PHASE CCM LOAD LINE, VID = 1.075V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
90
85
0.885
VIN = 8V
VIN = 12V
VOUT (V)
EFFICIENCY (%)
0.875
80
75
VIN = 19V
70
0.865
0.855
65
0.845
60
0.835
55
0.1
0.825
1
10
100
IOUT (A)
0
1
2
3
4
5
6
7 8 9
IOUT (A)
10 11 12 13 14 15
FIGURE 34. 1-PHASE DEM EFFICIENCY, VID = 0.875V,
DPRSLPVR IS ASSERTED FOR IOUT < 3A, VIN1 = 8V,
VIN2 = 12.6V AND VIN3 = 19V. SOLID LINES:
ISL62882 EFFICIENCY, DOTTED LINES: WOULD-BE
EFFICIENCY IF LGATE1b WAS NOT TURNED OFF IN
DPRSLPVR MODE
FIGURE 35. 1-PHASE DEM LOAD LINE, VID = 0.875V, DPRSLPVR
IS ASSERTED FOR IOUT < 3A
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 36. 2-PHASE CPU MODE SOFT-START, VIN = 19V,
IO = 0A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3:
PHASE2
FIGURE 37. 2-PHASE CPU MODESHUT DOWN, VIN = 19V,
IO = 1A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3:
PHASE2
35
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Typical Performance (Continued)
FIGURE 38. 2-PHASE CPU MODE CLK_EN# DELAY, VIN = 19V,
IO = 2A, VID = 1.5V, Ch1: PHASE1, Ch2: VO,
Ch4: CLK_EN#
FIGURE 39. 2-PHASE CPU MODE PRE-CHARGED START UP,
VIN = 19V, VID = 0.95V, Ch1: PHASE1, Ch2: VO,
Ch4: VR_ON
FIGURE 40. STEADY STATE, VIN = 19V, IO = 0A, VID = 1.075V,
Ch1: PHASE1, Ch2: VO, Ch3: PHASE2
FIGURE 41. STEADY STATE, VIN = 19V, IO = 35A, VID = 1.075V,
Ch1: PHASE1, Ch2: VO, Ch3: PHASE2
FIGURE 42. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, VIN = 19V,
VID = 1.075V, IO = 15A/50A, di/dt = “FASTEST”
FIGURE 43. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, VIN = 19V,
VID = 1.075V, IO = 15A/50A, di/dt = “FASTEST”
36
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Typical Performance (Continued)
FIGURE 44. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, VIN = 19V,
VID = 1.075V, IO = 15A/50A, di/dt = “FASTEST”
FIGURE 45. LOAD TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED, VIN = 19V,
VID = 1.075V, IO = 15A/50A, di/dt = “FASTEST”
FIGURE 46. 2-PHASE CPU MODE DEEPER SLEEP MODE
ENTRY/EXIT, IO = 1.5A, HFM VID = 1.075V, LFM
VID = 0.875V, DEEPER SLEEP VID = 0.875V,
Ch1: PHASE1, Ch2: VO, Ch3: PHASE2,
CH4: DPRSLPVR
FIGURE 47. 2-PHASE CPU MODE VID ON THE FLY,
1.075V/0.875V, 2-PHASE CONFIGURATION,
PSI# = 1, DPRSLPVR = 0, Ch1: PHASE1, Ch2: VO,
Ch3: PHASE2
FIGURE 48. PHASE ADDING (PSI# TOGGLE), IO = 15A,
VID = 1.075V, Ch1: PHASE1, Ch2: VO,
Ch3: PHASE2, Ch4: N/A
FIGURE 49. PHASE DROPPING (PSI# TOGGLE), IO = 15A,
VID = 1.075V, Ch1: PHASE1, Ch2: VO,
Ch3: PHASE2, Ch4: N/A
37
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Typical Performance (Continued)
Phase Margin
Gain
FIGURE 51. 2-PHASE CPU MODE REFERENCE DESIGN LOOP
GAIN T2(s) MEASUREMENT RESULT
1000
5.0
900
4.5
800
4.0
700
3.5
Z(f) (mΩ)
IMON-VSSSENSE (mV)
FIGURE 50. TRANSIENT RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION ENABLED, VIN = 19V,
VID = 0.95V, IO = 12A/51A, di/dt = “FASTEST”,
Ch1: PHASE1, Ch2: VO, Ch3: N/A, Ch4: LGATE1
600
500
VIN = 12V
SPEC
400
VIN = 8V
300
PSI# = 1, DPRSLPVR = 0, 2-Phase CCM
2.5
2.0
1.5
VIN = 19V
200
3.0
1.0
100
0.5
0
0
5
10
15
20
25
30
IOUT (A)
35
40
45
FIGURE 52. IMON, VID = 1.075
FIGURE 54. 1-PHASE GPU MODE SOFT-START, DPRSLPVR=0,
VIN = 8V, IO = 0A, VID = 1.2375V, Ch1: PHASE1,
Ch2: VO
38
50
0.0
PSI# = 0, DPRSLPVR = 0, 1-Phase DE
1k
1M
100k
10k
FREQUENCY (Hz)
FIGURE 53. REFERENCE DESIGN FDIM RESULT
FIGURE 55. 1-PHASE GPU MODE SHUT DOWN, VIN = 8V, IO = 1A,
VID = 1.2375V, Ch1: PHASE1, Ch2: VO
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Typical Performance (Continued)
FIGURE 56. 1-PHASE GPU MODE VID TRANSITION,
DPRSLPVR = 0, IO = 2A, VID = 1.2375V/1.0375V,
Ch2: VO, Ch3: VID4
39
FIGURE 57. 1-PHASE GPU MODE VID TRANSITION,
DPRSLPVR = 1, IO = 2A, VID = 1.2375V/1.0375V,
Ch2: VO, Ch3: VID4
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
CHANGE
5/6/11
FN6890.4
Updated to most current Intersil template.
Page 8, Electrical Spec table: Added min and max limits for IMON Output Current, Condition ISUM – pin current = 5µA, Min: 22
Max: 37.5
Page 8, Note 6: Updated over temp note in Min Max column of spec tables from "Compliance to datasheet limits is assured by
one or more methods: production test, characterization and/or design." To: "Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested."
2/10/11
FN6890.3
Page 7, Electrical Spec table: removed min and max limits for IMON Output Current, Condition ISUM – pin current = 5µA
Pg 2 - Updated Tape & Reel note in Ordering Information from "Add “-T” suffix for tape and reel." to new standard "Add “-T*” suffix
for tape and reel." The "*" covers all possible tape and reel options.
Removed -T FGs that are covered by "-T*" note (IRTZ-T, HRTZ-T, BHRTZ-T)
Updated Intersil Trademark statement at bottom of page 1 per directive from Legal.
Updated over temp note in Min Max column of spec tables from "Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested." to new
standard "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design."
Electrical Spec table: Removed Note 7 "Limits established by characterization and are not production tested." and references to
it in the table.
Updated L40.5x5 POD to rev .1. Changes from rev 0:
Added Note 7 (JEDEC reference drawing: MO-220WHHE-1)
Added Note 4 callout to Dimension b in bottom view
12/3/09
FN6890.2
Removed ISL62882A device from data sheet.
11/4/09
FN6890.2
Converted to new Intersil template. On page 19, Modes of Operation section last paragraph Changed from "Rbias =
147kohm enables the overshoot reduction function and Rbias = 47kohm disables it" to "Rbias = 147kohm disables the
overshoot reduction function and Rbias = 47kohm enables it". Applied Intersil Standards as follows: Ordering information
with notes and links, Added bold verbiage to Electrical spec conditions for over-temp and bolded min and max value
columns. Pin Descriptions placed in Table.
8/24/09
FN6890.1
8/18/09 - See attached .doc file for changes.
7/10/09: Updated Figures 1, 2, 10, 11 and 27. Per Jia, “All the drawings have updated the way ISEN capacitors are
connected. They used to be connected to from ISEN to GND, now they are connected from ISEN to Vo. It’s an application
patch that helps to avoid false IBAL fault during phase dropping due to an IC design error.”
Changed “GND” to “VSUM-“ for pins 10 and 11 in table 5. Pin 10 now reads “A capacitor (C9) decouples it to VSUM-. Place
it in general proximity of the controller.” Pin 11 now reads “A capacitor (C10) decouples it to VSUM-. Place it in general
proximity of the controller.”
5/19/09: Changed under Recommended Operating Conditions- Battery Voltage VIN from "+5V to 21V" to "+5V to 25V"
04/01/09
FN6890.0
Initial Release to web
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL62882, ISL62882B
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
40
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 9/10
4X 3.60
5.00
A
B
36X 0.40
6
PIN #1 INDEX AREA
3.50
5.00
6
PIN 1
INDEX AREA
0.15
(4X)
40X 0.4± 0 .1
BOTTOM VIEW
TOP VIEW
0.20
b
4
0.10 M C A B
PACKAGE OUTLINE
0.40
0.750
SEE DETAIL “X”
SIDE VIEW
3.50
5.00
0.050
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
(36X 0.40
0.2 REF
(40X 0.20)
C
(40X 0.60)
5
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
7.
JEDEC reference drawing: MO-220WHHE-1
either a mold or mark feature.
41
FN6890.4
June 21, 2011
ISL62882, ISL62882B
Package Outline Drawing
L48.6x6
48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
4X 4.4
6.00
44X 0.40
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
37
1
6.00
36
4 .40 ± 0.15
25
12
0.15
(4X)
13
24
0.10 M C A B
0.05 M C
TOP VIEW
48X 0.45 ± 0.10
4 48X 0.20
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
BASE PLANE
MAX 0.80
(
SEATING PLANE
0.08 C
( 44 X 0 . 40 )
( 5. 75 TYP )
C
SIDE VIEW
4. 40 )
C
0 . 2 REF
5
( 48X 0 . 20 )
0 . 00 MIN.
0 . 05 MAX.
( 48X 0 . 65 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
42
FN6890.4
June 21, 2011
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