DATASHEET

Multiphase PWM Regulator for AMD Fusion™ Mobile
CPUs
ISL6267
Features
The ISL6267 is designed to be completely compliant with AMD
Fusion™ specifications. The ISL6267 controls two Voltage
Regulators (VRs), with three integrated gate drivers. The first
VR can be configured as 3-, 2-, or 1-phase VR, while the second
output can be configured as 2- or 1-phase VR, providing
maximum flexibility. The two VRs share the serial control bus
to communicate with the CPU and achieve lower cost and
smaller board area compared with two-chip solutions.
• Supports AMD SVI 1.0 serial data bus interface
The PWM modulator of the ISL6267 is based on Intersil’s R3
(Robust Ripple Regulator) Technology™. Compared with the
traditional multi-phase buck regulator, the R3 modulator
commands variable switching frequency during load
transients, achieving faster transient response. With the same
modulator, it naturally goes into pulse frequency modulation in
light load conditions, which achieves higher light load
efficiency and extends battery life.
The ISL6267 has several other key features. Both outputs
support DCR current sensing with a single NTC thermostat for
DCR temperature compensation or accurate resistor current
sensing. Both of the outputs utilize remote voltage sense,
adjustable switching frequency, current monitor, OC
protection, independent power-good indicators, temperature
monitors, and a common thermal alert.
• Dual output controller with integrated drivers
- Core VR configurable 3-, 2-, 1-phase with two integrated
drivers
- Northbridge VR configurable 2- or 1-phase with one
integrated driver
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0V to 1.55V in 12.5mV steps
- Enhanced load line accuracy
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1-, 2- or 3-phase for the core output and 1- or
2-phase for the northbridge output
• Adaptive body diode conduction time reduction
• Superior noise immunity and transient response
• Output current monitor and thermal monitor
• Differential remote voltage sensing
Applications
• High efficiency across entire load range
• AMD fusion CPU/GPU core power
• Programmable switching frequency for both outputs
• Notebook computer
• Excellent dynamic current balance between phases
• Programmable +VID offset for both core and NB
• OCP/WOC, OVP, PGOOD, and thermal monitor
• Small footprint 48 Ld 6x6 QFN package
• Pb-free (RoHS compliant)
Core Performance on ISL6267EVAL1Z
100
1.12
90
1.10
VIN = 8V
70
1.08
VIN = 12V
60
VOUT (A)
EFFICIENCY (%)
80
VIN = 19V
50
40
30
10
VIN = 12V
1.02
5
10
15
20
25 30 35
IOUT (A)
40
45
1
50
VIN = 19V
0.98
VOUT CORE = 1.1V
FIGURE 1. EFFICIENCY vs LOAD
FN7801.1
January 8, 2013
VIN = 8V
1.04
1.00
20
0
0
1.06
55
0.96
VOUT CORE = 1.1V
0
5
10
15
20
25
30
35
40
45
50
55
IOUT (A)
FIGURE 2. VOUT vs LOAD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6267
VCCP
ENABLE
VDD
NB_PH2
NB_PH1
Simplified Application Circuit For High Power CPU Core
BOOT_NB
VIN
UG1_NB
VNB
ISEN1_NB
PH1_NB
ISEN2_NB
VNB1
LG1_NB
ISUMN_NB
NB_PH1
VNB1
VNB2
VW_NB
PWM2_NB
ISL6208
NB_PH2
NB_PH1
ISUMP_NB
NB_PH2
COMP_NB
VNB_SENSE
FB_NB
NTC_NB
FB2_NB
PROG1
VSEN_NB
PROG2
VR_HOT
RTN_NB
ISL6267
THERMAL INDICATOR
NTC
VIN
PWROK
µP
VNB2
SVD
PWM3
VW
ISL6208
SVC
PH3
VO3
COMP
UG2
VSEN
RTN
PH1
LG2
BOOT1
ISEN1
UG1
VO2
VO3
PH2
VO2
VIN
PH1
LG1
PH1
VO1
PH3
PH2
PH1
ISUMP
PGOOD
VO1
VIN
ISUMN
PGOOD_NB
ISEN3
ISEN2
GND PAD
PH2
VCORE
PH2
VCORE_SENSE
PH3
VIN
BOOT2
FB
FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
2
January 8, 2013
FN7801.1
ISL6267
VCCP
ENABLE
VDD
NB_PH2
NB_PH1
Simplified Application Circuit For AMD Torpedo Platform
NTC_NB
ISEN1_NB
UG1_NB
ISUMN_NB
VNB1
VIN
BOOT_NB
ISEN2_NB
VNB
VNB2
PH1_NB
LG1_NB
NB_PH1
VIN
VW_NB
COMP_NB
PWM2_NB
FB_NB
NB_PH2
FB2_NB
VSEN_NB
VNB_SENSE
VNB2
NTC
RTN_NB
VR_HOT
ISL6267
THERMAL INDICATOR
PROG1
PWROK
µP
VNB1
ISL6208
NB_PH2
NB_PH1
ISUMP_NB
PROG2
SVD
SVC
PWM3
+5V
VW
VIN
BOOT2
COMP
UG2
FB
PH2
VCORE
ISEN3/FB2
LG2
PH2
VO2
VSEN
RTN
VIN
BOOT1
PH1
PH2
VCORE_SENSE
UG1
PH1
ISEN2
LG1
VO1
PGOOD
VO1
PH2
PH1
ISUMP
VIN
VO2
GND PAD
ISUMN
PH1
PGOOD_NB
ISEN1
FIGURE 4. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
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FN7801.1
ISL6267
Simplified Application Circuit For Low Power CPU Core And NB
ISEN1_NB
VCCP
OPEN
VDD
ISEN2_NB
ENABLE
+5V
UG1_NB
ISUMN_NB
VNB1
VIN
BOOT_NB
VNB
PH1_NB
NB_PH1
ISUMP_NB
LG1_NB
NB_PH1
VNB1
NTC_NB
VW_NB
optional
PWM2_NB
OPEN
COMP_NB
FB_NB
PROG1
VSEN_NB
PROG2
VNB_SENSE
RTN_NB
NTC
VR_HOT
THERMAL INDICATOR
PWROK
µP
SVD
ISL6267
SVC
OPEN
+5V
PWM3
ISEN1
+5V
BOOT2
OPEN
UG2
OPEN
PH2
OPEN
LG2
OPEN
PGND2
OPEN
ISEN2
OPEN
ISEN3
VW
optional
COMP
VIN
BOOT1
FB
UG1
VCORE
VSEN
VCORE_SENSE
PH1
RTN
VO1
LG1
PH1
VO1
PGOOD_NB
PGOOD
VIN
PH1
ISUMP
GND PAD
ISUMN
FIGURE 5. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
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FN7801.1
ISL6267
OPEN
VCCP
ISEN2_NB
VDD
+5V
ENABLE
Simplified Application Circuit Showing Resistor Sensing
ISEN1_NB
VIN
BOOT_NB
UG1_NB
ISUMN_NB
NB_N
VNB
PH1_NB
NB_P
ISUMP_NB
LG1_NB
NB_P
NB_N
NTC_NB
VW_NB
optional
PWM2_NB
OPEN
COMP_NB
FB_NB
PROG1
VSEN_NB
VNB_SENSE
PROG2
RTN_NB
NTC
VR_HOT
THERMAL INDICATOR
PWROK
µP
SVD
ISL6267
SVC
OPEN
+5V
PWM3
ISEN1
+5V
BOOT2
OPEN
UG2
OPEN
PH2
OPEN
LG2
OPEN
PGND2
OPEN
ISEN2
OPEN
ISEN3
VW
optional
COMP
BOOT1
VIN
FB
UG1
VCORE
VSEN
VCORE_SENSE
PH1
RTN
PGOOD
VIN
VON
VOP
ISUMP
GND PAD
ISUMN
VOP
PGOOD_NB
VON
LG1
FIGURE 6. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
5
January 8, 2013
FN7801.1
ISL6267
PGOOD_NB
ISEN1_NB
ISEN2_NB
ISUMN_NB
ISUMP_NB
COMP_NB
FB_NB
FB2_NB
VW_NB
VSEN_NB
RTN_NB
VIN
ENABLE
Block Diagram
SVD
SERIAL
VID
INTERFACE
SVC
PWROK
PROG1
PROG2
VCORE
VNB
A/D
BOOT_NB
DAC1
NORTHBRIDGE
CONTROLLER AND DRIVER
UG_NB
(SIMILAR ARCHITECTURE TO
PH_NB
CORE SECTION)
SLEEP
LG_NB
D/A
MODE
DAC2
(PSI_L)
PWM2_NB
VDD
IBAL
PROG1
OFFSET
VOLTAGE
PROG2
PHASE
CURRENT
BALANCE
ISEN1
ISEN2
ISEN3/FB2
PWM3
NTC_NB
T_MONITOR
TEMP
NTC
BOOT2
MONITOR
DRIVER
UG2
VR_HOT
PH2
VW
DAC1
+
RTN
DRIVER
LG2
Σ
+
+
MODULATOR
BOOT1
E/A
DRIVER
-
FB
UG1
PH1
COMP
VCCP
DRIVER
+
ISUMP
-
ISUMN
CURRENT
OC AND WOC
SENSE
PROTECTION
LG1
PGOOD
OV
PROTECTION
VSEN
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January 8, 2013
FN7801.1
ISL6267
Pin Configuration
LG1_NB
PH1_NB
BOOT1_NB
UG1_NB
PROG2
ISUMN_NB
NTC_NB
ISUMP_NB
RTN_NB
ISEN2_NB
VSEN_NB
ISEN1_NB
ISL6267
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
36 PWM2_NB
FB2_NB 1
35 BOOT2
FB_NB 2
COMP_NB 3
34 UG2
VW_NB 4
33 PH2
32 LG2
PGOOD_NB 5
SVD 6
GND PAD
31 VCCP
PWROK 7
(BOTTOM)
30 PWM3
SVC 8
29 LG1
ENABLE 9
28 PH1
VDD 23
VIN 24
ISUMN 21
ISUMP 22
VSEN 19
RTN 20
37
ISEN2 17
ISEN1 18
25 PROG1
FB 15
ISEN3/FB2 16
NTC 12
VW 13
27 UG1
26 BOOT1
COMP 14
PGOOD 10
VR_HOT 11
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
FB2_NB
The components connecting to FB2_NB are used to adjust the compensation in 1-phase mode to achieve
optimum performance.
2
FB_NB
Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
3
COMP_NB
4
VW_NB
5
PGOOD_NB
6
SVD
7
PWROK
8
SVC
Serial VID clock input from the CPU processor master device.
9
ENABLE
Enable input. A high level logic on this pin enables both VRs.
10
PGOOD
Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull-up
externally to VCCP or 3.3V.
11
VR_HOT
Thermal overload open drain output indicator active LOW.
12
NTC
Thermistor input to VR_HOT circuit to monitor Core VR temperature.
13
VW
Window voltage set pin used to set the switching frequency for the Core controller. A resistor from this
pin to COMP programs the switching frequency (8kΩ gives approximately 300kHz).
14
COMP
15
FB
Northbridge VR error amplifier output.
Window voltage set pin used to set the switching frequency for the Northbridge controller. A resistor from
this pin to COMP_NB programs the switching frequency (8kΩ gives approximately 300kHz).
Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage.
Pull-up externally to VCCP or 3.3V.
Serial VID data bi-directional signal from the CPU processor master device to the VR.
System power good input. When this pin is high, the SVI interface is active and the I2C protocol is running.
While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must
be low prior to the ISL6267 PGOOD output going high per the AMD SVI Controller Guidelines.
Error amplifier output.
Output voltage feedback to the inverting input of the Core controller error amplifier.
7
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FN7801.1
ISL6267
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
16
ISEN3/FB2
When the Core VR of ISL6267 is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual
current sensing for Channel 3. When the Core VR of ISL6267 is configured in 2-phase mode, this pin is
FB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is off
in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase
mode to achieve optimum performance.
17
ISEN2
Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to 5V VDD, the controller
disables Channel 2, and the Core VR runs in single-phase mode.
18
ISEN1
Individual current sensing for Channel 1 of the Core output.
19
VSEN
Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.
20
RTN
Output voltage sense return pin for the Core controller. Connect to the -sense pin of the microprocessor
die.
21
ISUMN
Inverting input of the transconductance amplifier for current monitor and load line of Core output.
22
ISUMP
Non-inverting input of the transconductance amplifier for current monitor and load line of Core output.
23
VDD
5V bias power.
24
VIN
Battery supply voltage, used for feed-forward.
25
PROG1
Program pin for setting output voltage offset for Core VR.
26
BOOT1
Connect an MLCC capacitor across the BOOT1 and the phase (PH1) pin. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PH1 pin
drops below VCCP minus the voltage dropped across the internal boot diode.
27
UG1
Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UG1 pin to the gate of
the Phase 1 high-side MOSFET.
28
PH1
Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PH1 pin to the node
consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of
Phase 1.
29
LG1
Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LG1 pin to the gate of the
Phase 1 low-side MOSFET.
30
PWM3
PWM output for Channel 3 of the Core VR. When PWM3 is pulled to 5V VDD, the controller disables Phase
3 and runs in 2-phase mode.
31
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1µF
of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.
32
LG2
Output of the Phase 2 low-side MOSFET gate driver of VR1. Connect the LG2 pin to the gate of the
Phase 2 low-side MOSFET.
33
PH2
Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PH2 pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor
of Phase 2.
34
UG2
Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UG2 pin to the gate of
the Phase 2 high-side MOSFET.
35
BOOT2
Connect an MLCC capacitor across the BOOT2 and PH2 pins. The boot capacitor is charged through an
internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PH2 pin drops below
VCCP minus the voltage dropped across the internal boot diode.
36
PWM2_NB
37
LG1_NB
Output of the low-side MOSFET gate driver of the Northbridge VR. Connect the LG1_NB pin to the gate of
the low-side MOSFET of VR2.
38
PH1_NB
Current return path for the high-side MOSFET gate driver of the Northbridge VR. Connect the PH1_NB pin
to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of the Northbridge VR.
39
UG1_NB
Output of the high-side MOSFET gate driver of the Northbridge VR. Connect the UG1_NB pin to the gate
of the high-side MOSFET.
8
PWM output for Channel 2 of the Northbridge VR.
January 8, 2013
FN7801.1
ISL6267
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
40
BOOT1_NB
Connect an MLCC capacitor across the BOOT1_NB and the PH1_NB pins. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT1_NB pin, each time the
PH1_NB pin drops below VCCP minus the voltage dropped across the internal boot diode.
41
PROG2
Program pin for setting output voltage offset for Northbridge VR.
42
NTC_NB
Thermistor input to VR_HOT circuit to monitor Northbridge VR temperature.
43
ISUMN_NB
Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.
44
ISUMP_NB
Non-inverting input of the transconductance amplifier for current monitor and load line of the
Northbridge VR.
45
RTN_NB
Output voltage sense return pin for the Northbridge controller. Connect to the -sense pin of the
microprocessor die.
46
VSEN_NB
Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor
die.
47
ISEN2_NB
Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2 is pulled to 5V VDD, the
controller will disable Channel 2 and the Northbridge VR will run single-phase.
48
ISEN1_NB
Individual current sensing for Channel 1 of the Northbridge VR.
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6267HRZ
ISL6267 HRZ
-10 to +100
48 Ld 6x6 QFN
L48.6x6B
ISL6267IRZ
ISL6267 IRZ
-40 to +100
48 Ld 6x6 QFN
L48.6x6B
ISL6267EVAL1Z
Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6267. For more information on MSL please see tech brief TB363.
9
January 8, 2013
FN7801.1
ISL6267
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Gate Driver Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Multiphase R3™ Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial VID Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pre-PWROK Metal VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
VFIX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SVI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SVI WIRE Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SVI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Differential Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Dynamic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Adaptive Body Diode Conduction Time Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Inductor DCR Current-Sensing Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
NTC Thermal Monitors and VR_HOT Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10
January 8, 2013
FN7801.1
ISL6267
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . .PHASE - 0.3V (DC) to BOOTPHASE - 5V
. . . . . . . . . . . . . . . . . (<20ns Pulse Width, 10µJ) to BOOT LGATE Voltage
. . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, VR_HOT. . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
48 Ld QFN Package (Notes 4, 5) . . . . . . . .
28
1
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 25V
Ambient Temperature
HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +100°C (IRZ), fSW = 300kHz,
unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
9
10.5
mA
INPUT POWER SUPPLY
+5V Supply Current
IVDD
ENABLE = 1V
ENABLE = 0V
1
µA
Battery Supply Current
IVIN
ENABLE = 0V
1
µA
VIN Input Resistance
RVIN
ENABLE = 1V
550
kΩ
POWER-ON-RESET THRESHOLDS
VDD POR Threshold
VIN POR Threshold
VDD_PORr
VDD rising
VDD_PORf
VDD falling
VIN_PORr
VIN rising
VIN_PORf
4.35
4.00
4.15
VIN falling
2.8
3.30
No load; closed loop, active mode range
VID = 0.75V to 1.55V
-0.5
4.00
4.5
V
V
4.35
V
V
SYSTEM AND REFERENCES
System Accuracy
HRZ% Error
(VCC_CORE)
IRZ% Error
(VCC_CORE)
+0.5
%
VID = 0.50V to 0.7375V
-8
+8
mV
VID = 0.25V to 0.4875V
-15
+15
mV
No load; closed loop, active mode range
VID = 0.75V to 1.55V
-0.8
+0.8
%
VID = 0.50V to 0.7375V
-10
+10
mV
VID = 0.25V to 0.4875V
-18
+18
mV
Maximum Output Voltage
VCC_CORE(max)
VID = [0000000]
1.55
V
Minimum Output Voltage
VCC_CORE(min)
VID = [1111111]
0.0
V
11
January 8, 2013
FN7801.1
ISL6267
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +100°C (IRZ), fSW = 300kHz,
unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
280
300
320
kHz
275
300
CHANNEL FREQUENCY
Nominal Channel Frequency
HRZ, fSW(nom)
IRZ, fSW(nom)
Adjustment Range
325
kHz
200
500
kHz
-0.15
+0.15
mV
AMPLIFIERS
IFB = 0A
Current-Sense Amplifier Input Offset
Error Amp DC Gain
Av0
Error Amp Gain-Bandwidth Product
GBW
CL = 20pF
90
dB
18
MHz
ISEN
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
1
Input Bias Current
20
mV
nA
POWER-GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
PGOOD Delay
0.26
-1
0.4
V
1
µA
460
tPGD
µs
GATE DRIVER
1.5
Ω
UGATE Pull-Up Resistance
RUGPU
200mA Source Current
1.0
UGATE Source Current
IUGSRC
UGATE - PHASE = 2.5V
2.0
UGATE Sink Resistance
RUGPD
250mA Sink Current
1.0
UGATE Sink Current
IUGSNK
UGATE - PHASE = 2.5V
2.0
LGATE Pull-Up Resistance
RLGPU
250mA Source Current
1.0
LGATE Source Current
ILGSRC
LGATE - VSSP = 2.5V
2.0
LGATE Sink Resistance
RLGPD
250mA Sink Current
0.5
LGATE Sink Current
ILGSNK
LGATE - VSSP = 2.5V
4.0
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
23
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
28
ns
A
1.5
Ω
1.5
Ω
0.9
Ω
A
A
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
0.58
V
Reverse Leakage
IR
VR = 25V
0.2
µA
PROTECTION
Overvoltage Threshold
OVH
VSEN rising above setpoint for > 1ms
Severe Overvoltage Threshold
OVHS
VO rising above threshold > 0.5 µs
Undervoltage Threshold
OVH
VSEN falls below setpoint for > 1ms
Current Imbalance Threshold
200
HRZ
IRZ
Northbridge OCP Current Threshold
mV
400
mV
1.800
V
330
3-Phase CCM, 2-Phase CCM, 1-Phase
50
60
3-Phase DE
16
20
24
μA
2-Phase DE
24
30
36
μA
9
mV
70
μA
49.5
60
70
μA
3-Phase DE
16
20
24
μA
2-Phase DE
23.5
30
36
μA
50
60
70
μA
3-Phase CCM, 2-Phase CCM, 1-Phase
HRZ
2-Phase CCM, 1-Phase
24
30
36
μA
IRZ
2-Phase CCM, 1-Phase
49.5
60
70
μA
2-Phase DE
23.5
30
36
μA
2-Phase DE
12
330
260
One ISEN above another ISEN for > 1.2ms
Core OCP Current Threshold
270
January 8, 2013
FN7801.1
ISL6267
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C (HRZ), TA = -40°C to +100°C (IRZ), fSW = 300kHz,
unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
0.3
V
LOGIC THRESHOLDS
ENABLE Input Low
VIL
ENABLE Input High
VIH
0.7
V
PWM
PWM Output Low
V0L
Sinking 5mA
PWM Output High
V0H
Sourcing 5mA
PWM Tri-State Leakage
1.0
3.5
PWM = 2.5V
V
V
2
µA
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
57
67
µA
NTC_NB Source Current
NTC_NB = 1.3V
57
67
µA
Thermal Monitor Trip Voltage
Falling Threshold
0.87
0.88
0.89
V
Thermal Monitor Reset Voltage
Rising Threshold
0.91
0.92
0.93
V
-1
0
INPUTS
ENABLE Leakage Current
IENABLE
EN = 0V
EN = 1V
µA
18
36
µA
Slew Rate (for VID Change)
SR
5
7.5
10
mV/µs
Soft-Start Slew Rate
SSR
1.25
1.875
2.5
mV/µs
PWROK, SVC, SVD Input Logic High
VIH
0.798
PWROK, SVC, SVD Input Logic Low
VIL
SVI INTERFACE
SVC, SVD Leakage
V
0.57
V
EN = 0V, SVC and SVD = 0V
1
µA
EN = 5V, SVC and SVD = 1.8V
1
µA
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tUGFLGR
13
January 8, 2013
FN7801.1
ISL6267
Theory of Operation
out-of-phase. If VR1 is in 1-phase mode, the master clock signal
will be distributed to Phase 1 only and be the Clock1 signal.
Multiphase R3™ Modulator
The ISL6267 is a multiphase regulator implementing two voltage
regulators, VDD and VDDNB, on one chip controlled by AMD’s™
SVI1™ protocol. VDD can be programmed for 1-, 2- or 3-phase
operation. VDDNB can be configured for 1-phase or 2-phase
operation. Both regulators use the Intersil patented R3™ (Robust
Ripple Regulator) modulator. The R3™ modulator combines the
best features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 7 conceptually
shows the multiphase R3™ modulator circuit, and Figure 8 shows
the operation principles.
MASTER CLOCK CIRCUIT
MASTER
CLOCK
COMP
PHASE
VCRM
SEQUENCER
VW
MASTER
CLOCK
GMVO
VW
HYSTERETIC
WINDOW
VCRM
COMP
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
CLOCK1
CLOCK2
CLOCK3
PWM2
CRM
CLOCK3
SLAVE CIRCUIT 1
VW
VCRS1
CLOCK1
S
R
Q
PWM1
PHASE1
L1
PWM3
VO
VW
IL1
CO
GM
CRS1
VCRS2
VCRS3
VCRS1
SLAVE CIRCUIT 2
VW
VCRS2
CLOCK2
S
R
Q
PWM2
PHASE2
L2
IL2
GM
CRS2
SLAVE CIRCUIT 3
VW
VCRS3
CLOCK3
S
R
Q
PWM3
PHASE3
L3
IL3
GM
CRS3
FIGURE 7. R3™ MODULATOR CIRCUIT
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called “VW window” in the following
discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor Crm with a current source equal
to gmVo, where gm is a gain factor. Crm voltage VCRM is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If VDD is in 3-phase
mode, the master clock signal is distributed to the three phases,
and the Clock 1~3 signals will be 120° out-of-phase. If VR1 is in
2-phase mode, the master clock signal is distributed to Phases 1
and 2, and the Clock1 and Clock2 signals will be 180°
14
FIGURE 8. R3™ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
Each slave circuit has its own ripple capacitor Crs, whose voltage
mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge
Crs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges Crs. When Crs
voltage VCrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
Since the controller works with Vcrs, which are large amplitude
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL6267 to maintain a 0.5% output
voltage accuracy.
Figure 9 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL6267 excellent response
speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
January 8, 2013
FN7801.1
ISL6267
VW
PHASE
COMP
VCRM
UG ATE
MASTER
CLOCK
LG ATE
CLOCK1
PWM1
IL
CLOCK2
FIGURE 10. DIODE EMULATION
PWM2
CLOCK3
PWM3
VW
VW
CCM/DCM
BOUNDARY
V CRS
IL
VCRS1
VCRS3
VCRS2
VW LIGHT DCM
V CRS
FIGURE 9. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
Diode Emulation and Period Stretching
The ISL6267 can operate in diode emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
conducts when the current is flowing from source to drain and
does not allow reverse current, thus emulating a diode. As
Figure 10 shows, when LGATE is on, the low-side MOSFET carries
current, creating negative voltage on the phase node due to the
voltage drop across the ON-resistance. The ISL6267 monitors the
current by monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the inductor
current from reversing the direction and creating unnecessary
power loss. If the load current is light enough, (see Figure 10). The
inductor current reaches and stays at zero before the next phase
node pulse, and the regulator is in discontinuous conduction
mode (DCM). If the load current is heavy enough, the inductor
current will never reaches 0A, and the regulator is in CCM,
although the controller is in DE mode.
Figure 11 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL6267 clamps
the ripple capacitor voltage VCRS in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit VCRS,
naturally stretching the switching period. The inductor current
triangles move farther apart such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
15
IL
DEEP DCM
VW
V CRS
IL
FIGURE 11. PERIOD STRETCHING
Start-up Timing
With the controller's VDD and VIN voltages above their POR
threshold, the start-up sequence begins when ENABLE exceeds the
logic high threshold. Figure 12 shows the typical start-up timing of
VR1 and VR2. The ISL6267 uses digital soft-start to rampup DAC
to the voltage programmed by the Metal VID. PGOOD is asserted
high and low at the end of the rampup. Similar results occur if
ENABLE is tied to VDD, with the soft-start sequence starting
800µs after VDD crosses the POR threshold.
January 8, 2013
FN7801.1
ISL6267
Hysteresis between the rising and the falling thresholds assure
the ISL6267 does not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical Specifications” on
page 11).
VDD
SLEW RATE
1.875mV/µs
MetalVID VID COMMAND
ENABLE
Serial VID Interface
VOLTAGE
800µs
DAC
The on-board Serial VID Interface (SVI) circuitry allows the
processor to directly control the Core and Northbridge voltage
reference levels within the ISL6267. The SVC and SVD states are
decoded according to the PWROK inputs as described in the
following sections. The ISL6267 uses a digital-to-analog
converter (DAC) to generate a reference voltage based on the
decoded SVI value. See Figure 13 for a simple SVI interface
timing diagram.
PGOOD
PWROK
VIN
FIGURE 12. TYPICAL SOFT-START WAVEFORMS
Power-On Reset
Pre-PWROK Metal VID
Before the controller has sufficient bias to guarantee proper
operation, the ISL6267 requires both a +5V input supply tied to
VCC and PVCC, as well as a battery or other input supply tied to
VIN, to exceed their respective rising power-on reset (POR)
thresholds. Once these thresholds are reached or exceeded, the
ISL6267 has enough bias to begin checking SVI inputs.
1
2
3
4
5
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 1). Once the ENABLE input exceeds the rising
threshold, the ISL6267 decodes and locks the decoded value in
an on-board hold register.
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
METAL_VID
V_SVI
METAL_VID
V_SVI
VCORE/ VNB
PGOOD
Interval 1 to 2: ISL6267 waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: ENABLE locks pre-Metal VID code. All outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.
Interval 5 to 6: CPU detects PGOOD high, and drives PWROK high, to allow ISL6267 to prepare for SVI commands.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6267 responds to VID-ON-THE-FLY code change.
Interval 8 to 9: PWROK is driven low, and ISL6267 returns all outputs to pre-PWROK Metal VID level.
Interval 9 to 10: PWROK driven high once again by CPU, and ISL6267 prepares for SVI commands.
Interval 10 to 11: SVC and SVD data lines communicate new VID code.
Interval 11 to 12: ISL6267 drives outputs to new VID code level.
Post 12: Enable falls, all internal drivers are tri-stated, and PGOOD is driven low.
FIGURE 13. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
16
January 8, 2013
FN7801.1
ISL6267
TABLE 1. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE
(V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
The internal DAC circuitry begins to ramp Core and Northbridge
VRs to the decoded pre-PWROK Metal VID output level. The
digital soft-start circuitry ramps the internal reference to the
target gradually at a fixed rate of approximately 2mV/µs. The
controlled ramp of all output voltage planes reduces in-rush
current during the soft-start interval. At the end of the soft-start
interval, the PGOOD output transitions high, indicating all output
planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL6267 tri-states both outputs. PGOOD is pulled low with the
loss of ENABLE. The Core and Northbridge planes decay, based
on output capacitance and load leakage resistance. If bias to VCC
falls below the POR level, the ISL6267 responds in the manner
previously described. Once VCC and ENABLE rise above their
respective rising thresholds, the internal DAC circuitry reacquires
a pre-PWROK metal VID code, and the controller soft-starts.
VFIX Mode
The ISL6267 does not support VFIX Mode. In the event a CPU is
not present on a motherboard and the ISL6267 is powered on,
the state of SVC and SVD sets the pre-PWROK metal VID as the
“Pre-PWROK Metal VID” on page 16 and begins soft-starting.
SVI Mode
Once the controller has successfully soft-starts and PGOOD and
PGOOD_NB transition high, the processor can assert PWROK to
signal the ISL6267 to prepare for SVI commands. The controller
actively monitors the SVI interface for set VID commands to
move the plane voltages to start-up VID values. Details of the SVI
Bus protocol are provided in the “AMD Design Guide for Voltage
Regulator Controllers Accepting Serial VID Codes” specification.
Once a set VID command is received, the ISL6267 decodes the
information to determine which VR is affected and which VID
target is required (see Table 2). The internal DAC circuitry steps
the output voltage of the VR commanded to the new VID level.
During this time, one or more of the VR outputs could be
targeted. In the event either VR is commanded to power-off by
serial VID commands, the PGOOD signal remains asserted.
17
If the PWROK input is de-asserted, then the controller steps both
the Core and the Northbridge VRs back to the stored pre-PWROK
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this time.
If PWROK is re-asserted, then the on-board SVI interface waits for
a set VID command.
If ENABLE goes low during normal operation, all internal drivers
are tri-stated and PGOOD is pulled low. This event clears the
pre-PWROK metal VID code and forces the controller to check
SVC and SVD upon restart.
A POR event on either VCC or VIN during normal operation shuts
down both regulators, and both PGOOD outputs are pulled low.
The pre-PWROK metal VID code is not retained.
VID-on-the-Fly Transition
Once PWROK is high, the ISL6267 detects this flag and begins
monitoring the SVC and SVD pins for SVI instructions. The
microprocessor follows the protocol outlined in the following
sections to send instructions for the VID-on-the-fly transitions.
The ISL6267 decodes the instruction and acknowledges the new
VID code. For the VID codes higher than the current VID level, the
ISL6267 begins stepping the commanded VR outputs to the new
VID target with a typical slew rate of 7.5mV/µs, which meets the
AMD requirements.
When the VID codes are lower than the current VID level, the
ISL6267 checks the state of PSI_L. If PSI_L is high, the controller
begins stepping the regulator output to the new VID target with a
typical slew rate of -7.5mV/µs. If PSI_L is low, the controller
allows the output voltage to decay and slowly steps the DAC
down with the natural decay of the output. This allows the
controller to quickly recover and move to a high VID code if
commanded. AMD requirements under these conditions do not
require the regulator to meet the minimum slew rate
specification of -5mV/µs. In either case, the slew rate is not
allowed to exceed 10mV/µs. The ISL6267 does not change the
state of PGOOD (VCCPWRGD in AMD specifications), when a
VID-on-the-fly transition occurs.
SVI WIRE Protocol
The SVI WIRE protocol is based on the I2C bus concept. Two wires
[serial clock (SVC) and serial data (SVD)], carry information
between the AMD processor (master) and the VR controller
(slave) on the bus. The master initiates and terminates SVI
transactions and drives the clock, SVC, during a transaction. The
AMD processor is always the master, and the voltage regulators
are the slaves. The slave receives the SVI transactions and acts
accordingly. Mobile SVI WIRE protocol timing is based on
high-speed mode I2C. See AMD publication #40182 for
additional details.
January 8, 2013
FN7801.1
ISL6267
.
TABLE 2. SERIAL VID CODES
SVID
[6:0]
VOLTAGE
(V)
SVID
[6:0]
VOLTAGE
(V)
SVID
[6:0]
VOLTAGE
(V)
SVID
[6:0]
VOLTAGE
(V)
000_0000b
1.5500
010_0000b
1.1500
100_0000b
0.7500
110_0000b
0.3500*
000_0001b
1.5375
010_0001b
1.1375
100_0001b
0.7375
110_0001b
0.3375*
000_0010b
1.5250
010_0010b
1.1250
100_0010b
0.7250
110_0010b
0.3250*
000_0011b
1.5125
010_0011b
1.1125
100_0011b
0.7125
110_0011b
0.3125*
000_0100b
1.5000
010_0100b
1.1000
100_0100b
0.7000
110_0100b
0.3000*
000_0101b
1.4875
010_0101b
1.0875
100_0101b
0.6875
110_0101b
0.2875*
000_0110b
1.4750
010_0110b
1.0750
100_0110b
0.6750
110_0110b
0.2750*
000_0111b
1.4625
010_0111b
1.0625
100_0111b
0.6625
110_0111b
0.2625*
000_1000b
1.4500
010_1000b
1.0500
100_1000b
0.6500
110_1000b
0.2500*
000_1001b
1.4375
010_1001b
1.0375
100_1001b
0.6375
110_1001b
0.2375*
000_1010b
1.4250
010_1010b
1.0250
100_1010b
0.6250
110_1010b
0.2250*
000_1011b
1.4125
010_1011b
1.0125
100_1011b
0.6125
110_1011b
0.2125*
000_1100b
1.4000
010_1100b
1.0000
100_1100b
0.6000
110_1100b
0.2000*
000_1101b
1.3875
010_1101b
0.9875
100_1101b
0.5875
110_1101b
0.1875*
000_1110b
1.3750
010_1110b
0.9750
100_1110b
0.5750
110_1110b
0.1750*
000_1111b
1.3625
010_1111b
0.9625
100_1111b
0.5625
110_1111b
0.1625*
001_0000b
1.3500
011_0000b
0.9500
101_0000b
0.5500
111_0000b
0.1500*
001_0001b
1.3375
011_0001b
0.9375
101_0001b
0.5375
111_0001b
0.1375*
001_0010b
1.3250
011_0010b
0.9250
101_0010b
0.5250
111_0010b
0.1250*
001_0011b
1.3125
011_0011b
0.9125
101_0011b
0.5125
111_0011b
0.1125*
001_0100b
1.3000
011_0100b
0.9000
101_0100b
0.5000
111_0100b
0.1000*
001_0101b
1.2875
011_0101b
0.8875
101_0101b
0.4875*
111_0101b
0.0875*
001_0110b
1.2750
011_0110b
0.8750
101_0110b
0.4750*
111_0110b
0.0750*
001_0111b
1.2625
011_0111b
0.8625
101_0111b
0.4625*
111_0111b
0.0625*
001_1000b
1.2500
011_1000b
0.8500
101_1000b
0.4500*
111_1000b
0.0500*
001_1001b
1.2375
011_1001b
0.8375
101_1001b
0.4375*
111_1001b
0.0375*
001_1010b
1.2250
011_1010b
0.8250
101_1010b
0.4250*
111_1010b
0.0250*
001_1011b
1.2125
011_1011b
0.8125
101_1011b
0.4125*
111_1011b
0.0125*
001_1100b
1.2000
011_1100b
0.8000
101_1100b
0.4000*
111_1100b
OFF
001_1101b
1.1875
011_1101b
0.7875
101_1101b
0.3875*
111_1101b
OFF
001_1110b
1.1750
011_1110b
0.7750
101_1110b
0.3750*
111_1110b
OFF
001_1111b
1.1625
011_1111b
0.7625
101_1111b
0.3625*
111_1111b
OFF
NOTE:
*Indicates a VID not required for AMD Family 10h processors.
18
January 8, 2013
FN7801.1
PSI_L
ISL6267
6
5
4
3
2
1
7
0
See Table 3
SVID
6
4
5
3
2
1
0
SVC
STOP
ACK
DATA PHASE
ACK
SLAVE ADDRESS PHASE
WRITE
START
SVD
FIGURE 14. SEND BYTE EXAMPLE
SVI Bus Protocol
VR Offset Programming
The AMD processor bus protocol is compliant with SMBus send
byte protocol for VID transactions (see Figure 14). During a send
byte transaction, the processor sends the start sequence
followed by the slave address of the VR for which the VID
command applies. The address byte must be configured
according to Table 3. The processor then sends the write bit. After
the write bit, if the ISL6267 receives a valid address byte, it
sends the acknowledge bit. The processor then sends the PSI-L
bit and VID bits during the data phase. The Serial VID 8-bit data
field encoding is outlined in Table 4. If the ISL6267 receives a
valid 8-bit code during the data phase, it sends the acknowledge
bit. Finally, the processor sends the stop sequence. After the
ISL6267 has detected the stop, it can then proceed with the
VID-on-the-fly transition.
A positive or negative offset is programmed for the Core VR using
a resistor to ground from the PROG1 pin and the Northbridge in a
similar manner from the PROG2 pin. Table 5 provides the resistor
value to select the desired output voltage offset
TABLE 3. SVI SEND BYTE ADDRESS DESCRIPTION
BITS
6:4
DESCRIPTION
Always 110b
3
Reserved by AMD for future use
2
VDD1; if set, then the following data byte contains the VID for
VDD1 [Note: The ISL6267 does not support VDD1]
1
VDD0; if set, then the following data byte contains the VID for
VID0
0
VDDNB; if set then the following data byte contains the VID for
VIDNB
TABLE 4. SERIAL VID 8-BIT DATA FIELD ENCODING
TABLE 5. PROGx PIN RESISTOR VALUE
RESISTOR
VALUE
[Ω]
PROG1
VCORE OFFSET
[mV]
PROG1
VNBOFFSET
[mV]
0
50
50
590
43.75
43.75
1100
37.50
37.50
1690
31.25
31.25
2260
25.00
25.00
3160
18.75
18.75
4320
12.50
12.50
5620
6.25
6.25
6650
0.00
0.00
7870
-6.25
-6.25
9530
-12.50
-12.50
11500
-18.75
-18.75
14000
-25.00
-25.00
16500
-31.25
-31.25
BITS
DESCRIPTION
18700
-37.50
-37.50
7
PSI_L:
=0 means the processor is at an optimal load for the regulators
to enter power-saving mode
=1 means the processor is not at an optimal load for the
regulators to enter power-saving mode
OPEN
-43.75
-43.75
6:0
SVID[6:0] as defined in Table 2.
Operation
After the start-up sequence, the ISL6267 begins regulating the
Core and Northbridge output voltages to the pre-PWROK metal
VID programmed. The controller monitors SVI commands to
determine when to enter power-saving mode, implement
dynamic VID changes, and shut down individual outputs.
19
Voltage Regulation and Load Line
Implementation
After the start sequence, the ISL6267 regulates the output voltage
to the value set by the VID information, per Table 2. The ISL6267
controls the no-load output voltage to an accuracy of ±0.5% over
the range of 0.75V to 1.55V. A differential amplifier allows
voltage sensing for precise voltage regulation at the
microprocessor die.
January 8, 2013
FN7801.1
ISL6267
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 3:
Rdroop
+
FB
VCCSENSE
Vdroop
VCC SENSE + V
VR LOCAL VO
“CATCH” RESISTOR
Idroop
COMP
-
Σ
+
VDAC
INTERNAL TO IC
VIDs
DAC
RTN
X1
+
-
VSSSENSE
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
As the load current increases from zero, the output voltage
droops from the VID table value by an amount proportional to the
load current, to achieve the load line. The ISL6267 can sense the
inductor current through the intrinsic DC Resistance (DCR) of the
inductors, as shown in Figures 15 and 16, or through resistors in
series with the inductors as shown in Figure 17. In both methods,
capacitor Cn voltage represents the inductor total currents. A
droop amplifier converts Cn voltage into an internal current
source with the gain set by resistor Ri. The current source is used
for load line implementation, current monitoring and overcurrent
protection.
Figure 15 shows the load-line implementation. The ISL6267
drives a current source (Idroop) out of the FB pin, as described by
Equation 1.
(EQ. 1)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load-line accuracy with
reduced cost.
Idroop flows through resistor Rdroop and creates a voltage drop as
shown in Equation 2.
(EQ. 2)
Vdroop is the droop voltage required to implement load line.
Changing Rdroop or scaling Idroop can change the load line slope.
Since Idroop sets the overcurrent protection level, it is
recommended to first scale Idroop based on OCP requirement,
then select an appropriate Rdroop value to obtain the desired
load line slope.
Differential Sensing
Figure 15 shows the differential voltage sensing scheme.
VCCSENSE and VSSSENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSSSENSE voltage and adds it to the DAC output. The error
20
(EQ. 4)
VSS
FIGURE 15. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
V droop = R droop × I droop
(EQ. 3)
VID<0:7>
“CATCH” RESISTOR
2xV Cn
I droop = ---------------Ri
= V DAC + VSS SENSE
Rewriting Equation 3 and substituting Equation 2 gives
Equation 4 is the exact equation required for load-line
implementation.
+
E/A
droop
The VCCSENSE and VSSSENSE signals come from the processor die.
The feedback is an open circuit in the absence of the processor. As
Figure 15 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and to add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
Rdcr3
L3
Rpcb3
PHASE3
Risen
ISEN3
INTERNAL
INTERNAL
TO IC
IL3
Cisen
Rdcr2
L2
Rpcb2
VO
PHASE2
Risen
IL2
ISEN2
Cisen
Rdcr1
L1
Rpcb1
PHASE1
Risen
IL1
ISEN1
Cisen
FIGURE 16. CURRENT BALANCING CIRCUIT
The ISL6267 monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 16
shows the current balancing circuit recommended for the
ISL6267. Each phase node voltage is averaged by a low-pass
filter consisting of Risen and Cisen, and is presented to the
corresponding ISEN pin. Risen should be routed to the inductor
phase-node pad in order to eliminate the effect of phase node
parasitic PCB DCR. Equations 5 through 7 give the ISEN pin
voltages:
V ISEN1 = ( R dcr1 + R pcb1 ) × I L1
(EQ. 5)
V ISEN2 = ( R dcr2 + R pcb2 ) × I L2
(EQ. 6)
V ISEN3 = ( R dcr3 + R pcb3 ) × I L3
(EQ. 7)
where Rdcr1, Rdcr2 and Rdcr3 are inductor DCR; Rpcb1, Rpcb2
and Rpcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and IL1, IL2 and IL3 are
inductor average currents.
January 8, 2013
FN7801.1
ISL6267
The ISL6267 adjusts the phase pulse-width relative to the other
phases to make VISEN1 = VISEN2 = VISEN3, thus to achieve
IL1 = IL2 = IL3, when Rdcr1 = Rdcr2 = Rdcr3 and
Rpcb1 = Rpcb2 = Rpcb3.
Rewriting Equation 11 gives Equation 13:
Using the same components for L1, L2 and L3 provides a good
match of Rdcr1, Rdcr2 and Rdcr3. Board layout determines Rpcb1,
Rpcb2 and Rpcb3. It is recommended to have symmetrical layout
for the power delivery path between each inductor and the output
voltage rail, such that Rpcb1 = Rpcb2 = Rpcb3.
V 2p – V 2n = V 3p – V 3n
PHASE3
R isen
ISEN3
Cisen
INTERNAL
TO IC
ISEN2
C isen
R dcr3
L3
V3p
IL3
R pcb2
Vo
V2n
R isen
ISEN1
Cisen
R dcr1
L1
PHASE1 V1p
R isen
IL1
R isen
Rpcb1
V1n
R isen
FIGURE 17. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
Sometimes, it is difficult to implement symmetrical layout. For
the circuit shown in Figure 16, asymmetric layout causes
different Rpcb1, Rpcb2 and Rpcb3 values, thus creating a current
imbalance. Figure 17 shows a differential sensing current
balancing circuit recommended for the ISL6267. The current
sensing traces should be routed to the inductor pads so they only
pick up the inductor DCR voltage. Each ISEN pin sees the average
voltage of three sources: its own, phase inductor phase-node
pad, and the other two phases inductor output side pads.
Equations 8 through 10 give the ISEN pin voltages:
V ISEN1 = V 1p + V 2n + V 3n
(EQ. 8)
V ISEN2 = V 1n + V 2p + V 3n
(EQ. 9)
V ISEN3 = V 1n + V 2n + V 3p
(EQ. 10)
The ISL6267 will make VISEN1 = VISEN2 = VISEN3 as shown in
Equations 11 and 12:
V 1p + V 2n + V 3n = V 1n + V 2p + V 3n
(EQ. 11)
V 1n + V 2p + V 3n = V 1n + V 2n + V 3p
(EQ. 12)
21
(EQ. 14)
Combining Equations 13 and 14 gives:
V 1p – V 1n = V 2p – V 2n = V 3p – V 3n
R dcr1 × I L1 = R dcr2 × I L2 = R dcr3 × I L3
R dcr2
IL2
R isen
Rewriting Equation 12 gives Equation 14:
(EQ. 15)
(EQ. 16)
V3n
R isen
L2
(EQ. 13)
Therefore:
Rpcb3
R isen
V2p
PHASE2
R isen
V 1p – V 1n = V 2p – V 2n
Current balancing (IL1 = IL2 = IL3) is achieved when
Rdcr1 = Rdcr2 = Rdcr3. Rpcb1, Rpcb2 and Rpcb3 do not have any
effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, the R3™ modulator can naturally achieve excellent
current balancing during steady state and dynamic operations.
Figure 18 shows the current balancing performance of the
evaluation board with load transient of 12A/51A at different rep
rates. The inductor currents follow the load current dynamic
change with the output capacitors supplying the difference. The
inductor currents can track the load current well at a low
repetition rate, but cannot keep up when the repetition rate gets
into the hundred-kHz range, where it is out of the control loop
bandwidth. The controller achieves excellent current balancing in
all cases installed.
CCM Switching Frequency
The Rfset resistor between the COMP and the VW pins sets the
VW windows size and therefore sets the switching frequency.
When the ISL6267 is in continuous conduction mode (CCM), the
switching frequency is not absolutely constant due to the nature
of the R3™ modulator. As explained in the “Multiphase R3™
Modulator” on page 14, the effective switching frequency
increases during load insertion and decreases during load
release to achieve fast response. Thus, the switching frequency is
relatively constant at steady state. Variation is expected when
the power stage condition, such as input voltage, output voltage,
load, etc. changes. The variation is usually less than 15% and
does not have any significant effect on output voltage ripple
magnitude. Equation 17 gives an estimate of the
frequency-setting resistor (Rfset) value. A value of 8kΩ Rfset gives
approximately 300kHz switching frequency. Lower resistance
gives higher switching frequency.
R fset ( kΩ ) = ( Period ( μs ) – 0.29 ) × 2.65
(EQ. 17)
January 8, 2013
FN7801.1
ISL6267
Modes of Operation
REP RATE = 10kHz
TABLE 6. CORE VR MODES OF OPERATION
PWM3
ISEN2
To
External
Driver
PSL_L
MODE
To Power 3-phase
Stage
CPU VR
Config.
1
3-phase CCM
60
0
1-phase DE
20
2-phase
CPU VR
Config.
1
2-phase CCM
60
0
1-phase DE
30
1-phase
CPU VR
Config.
X
1-phase DE
60
Tied to 5V
Tied to
5V
REP RATE = 25kHz
CONFIG.
OCP
THRESHOLD
(µA)
The Core VR can be configured for 3, 2- or 1-phase operation.
Table 6 shows Core VR configurations and operational modes,
programmed by the PWM3 and ISEN2 pin status and the PS
command. For 2-phase configuration, tie the PWM3 pin to 5V. In
this configuration, phases 1 and 2 are active. For 1-phase
configuration, tie the PWM3 pin and the ISEN2 pin to 5V. In this
configuration, only phase-1 is an active, the controller operates in
DE mode and the PSI_L input been ignored.
REP RATE = 50kHz
In 3-phase configuration, Core VR operates in 3-phase CCM, with
PSI_L high. It enters 1-phase DE mode when PSI_L is low,
dropping phases 3 and 2, and reduces the overcurrent and the
way-overcurrent protection levels to one-third of the initial values.
In 2-phase configuration, Core VR operates in 2-phase CCM with
PSI_L high. It enters 1-phase DE mode with PSI_L low, by
dropping phase 2 and reduces the overcurrent and the way
overcurrent protection levels to one-half of the initial values.
REP RATE = 100kHz
In 1-phase configuration, the Core VR operates in 1-phase DE and
ignores the PSI_L input. If a resistor is placed from COMP pin to
GND with a value less than 150kΩ, then the Core VR operates in
1-phase CCM with PSI_L high and enters 1-phase DE mode when
PSI_L is low. A resistor value of 100kΩ is recommended.
TABLE 7. NORTHBRIDGE VR MODES OF OPERATION
ISEN2_NB
CONFIG.
PSL_L
MODE
OCP
THRESHOLD
(µA)
To Power
Stage
2-phase NB
VR Config.
1
2-phase CCM
60
0
1-phase DE
30
Tied to 5V
1-phase NB
VR Config.
X
1-phase DE
60
REP RATE = 200kHz
FIGURE 18. CURRENT BALANCING DURING DYNAMIC
OPERATION. CH1: IL1 , CH2: ILOAD, CH3: IL2, CH4:
IL3
22
ISL6267 Northbridge (NB) VR can be configured for 2- or 1-phase
operation. Table 7 shows the Northbridge VR configurations and
operational modes, which are programmed by the ISEN2 pin
status and the PSI_L command. For 1-phase configuration, tie
the ISEN2_NB pin to 5V. In 1-phase configuration, the
Northbridge VR operates in 1-phase DE and ignores the PSI_L
input. If a resistor is placed from COMP_NB pin to GND with a
value less than 150kΩ, then the Northbridge VR operates in 1phase CCM with PSI_L high and enters 1-phase DE mode when
PSI_L is low. A resistor value of 100kΩ is recommended.
The Northbridge VR can be disabled completely by tying
ISUMN_NB to 5V.
January 8, 2013
FN7801.1
ISL6267
Dynamic Operation
Core VR and Northbridge VR behave the same during dynamic
operation. The controller responds to VID-on-the-fly changes by
slewing to the new voltage at the fixed 7.5mV/µs slew rate.
During negative VID transitions, the output voltage decays to the
lower VID value at the slew rate determined by the load.
SVI_L low command prompts the controller to enter DE mode.
Overvoltage protection is blanked during VID down transition in
DE mode until the output voltage is within 60mV of the VID value.
During load insertion response, the Fast Clock function increases
the PWM pulse response speed. The controller monitors the
VSEN pin voltage and compares it to 100ns-filtered version.
When the unfiltered version is 20mV below the filtered version,
the controller knows there is a fast voltage dip due to load
insertion, and it issues an additional master clock signal to
deliver a PWM pulse immediately.
The R3™ modulator intrinsically has voltage feed-forward. The
output voltage is insensitive to a fast slew rate input voltage
change.
threshold. When ENABLE and VDD return to their high operating
levels, a soft-start occurs.
Table 8 summarizes the fault protections.
TABLE 8. FAULT PROTECTION SUMMARY
FAULT DURATION
BEFORE
PROTECTION
FAULT TYPE
Overcurrent
120µs
Phase Current
Unbalance
FAULT
RESET
ENABLE
toggle or
VDD toggle
PWM tri-state,
PGOOD latched
low
1ms
Way-Overcurrent
(1.5xOC)
PROTECTION
ACTION
Immediately
Overvoltage +200mV
PGOOD latched
low. Actively pulls
the output
voltage to below
VID value, then
tri-state.
Over-Temperature
400µs
N/A
Protections
FB2 Function
Core VR and Northbridge VR both provide overcurrent,
current-balance and overvoltage fault protections. The controller
also provides over-temperature protection. The following
discussion is based on Core VR and also applies to Northbridge VR.
The FB2 function is only available for Core VR or Northbridge VR
in 2-phase configuration.
The controller determines overcurrent protection (OCP) by
comparing the average value of the droop current (Idroop) with an
internal current source threshold as Table 6 shows. It declares OCP
when Idroop is above the threshold for 120µs.
For overcurrent conditions above 1.5x the OCP level, the PWM
outputs immediately shuts off and PGOOD goes low to maximize
protection. This protection is also referred to as way-overcurrent
protection or fast overcurrent protection for short-circuit
protections.
The controller monitors the ISEN pin voltages to determine
current-balance protection. If the ISEN pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
latch off.
The controller takes the same actions for all of the previously
describe fault protections: de-assertion of PGOOD and turn-off of
the high-side and low-side power MOSFETs. Any residual inductor
current decays through the MOSFET body diodes.
The controller declares an overvoltage fault and de-asserts PGOOD if
the output voltage exceeds the VID set value by +250mV. The
ISL6267 immediately declares an OV fault, de-asserts PGOOD,
and turn on the low-side power MOSFETs. The low-side power
MOSFETs remain on until the output voltage is pulled down below
the VID set value when all power MOSFETs are turned off. If the
output voltage rises above the VID set value +250mV again, the
protection process is repeated. This behavior provides the
maximum amount of protection against shorted high-side power
MOSFETs while preventing output ringing below ground.
All of the previously described fault conditions can be reset by
bringing ENABLE low or by bringing VDD below the POR
23
C1 R2
CONTROLLER
IN
2-PHASE MODE
C2 R3
VSEN
C3.1
CONTROLLER
IN
1-PHASE MODE
FB2 C3.2
C2 R3
R1
C1 R2
C3.1
FB2 C3.2
R1
FB
VREF
E/A
VSEN
FB
COMP
E/A
COMP
VREF
FIGURE 19. FB2 FUNCTION
Figure 19 shows the FB2 function. A switch (called FB2 switch)
turns on to short the FB and the FB2 pins when the controller is in
2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving
as part of the compensator. When the controller enters 1-phase
mode, the FB2 switch turns off, removing C3.2 and leaving only
C3.1 in the compensator. The compensator gain increases with
the removal of C3.2. By properly sizing C3.1 and C3.2, the
compensator can be optimal for both 2-phase mode and 1-phase
mode.
When the FB2 switch is off, C3.2 is disconnected from the FB pin.
However, the controller still actively drives the FB2 pin voltage to
follow the FB pin voltage such that C3.2 voltage always follows
C3.1 voltage. When the controller turns on the FB2 switch, C3.2
is reconnected to the compensator smoothly.
The FB2 function ensures excellent transient response in both
2-phase and 1-phase mode. If the FB2 function is not used,
populate C3.1 only.
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative, and the amount is the
January 8, 2013
FN7801.1
ISL6267
MOSFET rDS(ON) voltage drop, which is proportional to the
inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the zero
crossing point of the inductor current. If the inductor current has
not reached zero when the low-side MOSFET turns off, it will flow
through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it will flow through the
high-side MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET. To
minimize the body diode-related loss, the controller also adjusts
the phase comparator threshold voltage accordingly in iterative
steps such that the low-side MOSFET body diode conducts for
approximately 40ns.
Key Component Selection
Inductor DCR Current-Sensing Network
PHASE1 PHASE2 PHASE3
RSUM
RSUM
ISUM+
RSUM
L
L
L
RNTCS
+
RP
DCR
DCR
DCR
RNTC
RO
CNVCN
RI
ISUM-
RO
RO
IO
FIGURE 20. DCR CURRENT-SENSING NETWORK
Figure 20 shows the inductor DCR current-sensing network for a
3-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in Rsum
and Ro connected to the pads to accurately sense the inductor
current by sensing the DCR voltage drop. The Rsum and Ro
resistors are connected in a summing network as shown, and feed
the total current information to the NTC network (consisting of
Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative
temperature coefficient (NTC) thermistor, used to temperature
compensate the inductor DCR change.
The inductor output side pads are electrically shorted in the
schematic but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10Ω Ro to create quality signals. Since Ro value is much
smaller than the rest of the current sensing circuit, the following
analysis ignores it.
domain relationship between inductor total current Io(s) and Cn
voltage VCn(s):
⎛
⎞
R ntcnet
⎜
DCR⎟
V Cn ( s ) = ⎜ ----------------------------------------- × ------------⎟ × I o ( s ) × A cs ( s )
N ⎟
R sum
⎜
⎝ R ntcnet + ------------⎠
N
(EQ. 18)
( R ntcs + R ntc ) × R p
R ntcnet = --------------------------------------------------R ntcs + R ntc + R p
(EQ. 19)
s
1 + -----ωL
A cs ( s ) = ---------------------s
1 + -----------ω sns
(EQ. 20)
DCR
ω L = -----------L
(EQ. 21)
1
ω sns = -----------------------------------------------------R sum
R ntcnet × -------------N
----------------------------------------- × C n
R sum
R ntcnet + -------------N
(EQ. 22)
where N is the number of phases.
Transfer function Acs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC Rntc
value decrease as its temperature decreases. Proper selection of
Rsum, Rntcs, Rp and Rntc parameters ensures that VCn
represents the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly temperature
compensate the DCR change. Since the NTC network and the Rsum
resistors form a voltage divider, Vcn is always a fraction of the
inductor DCR voltage. It is recommended to have a higher ratio of
Vcn to the inductor DCR voltage so the droop circuit has a higher
signal level to work with.
A typical set of parameters that provide good temperature
compensation are: Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ
and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current sensing network parameters to minimize engineering
time.
VCn(s) also needs to represent real-time Io(s) for the controller to
achieve good transient response. Transfer function Acs(s) has a
pole wsns and a zero wL. One needs to match wL and wsns so
Acs(s) is unity gain at all frequencies. By forcing wL equal to wsns
and solving for the solution. Equation 23 gives Cn value.
The summed inductor current information is presented to the
capacitor Cn. Equations 18 thru 22 describe the frequency
24
January 8, 2013
FN7801.1
ISL6267
L
C n = -----------------------------------------------------------R sum
R ntcnet × -------------N
----------------------------------------- × DCR
R sum
R ntcnet + -------------N
(EQ. 23)
io
For example, given N = 3, Rsum = 3.65kΩ, Rp = 11kΩ,
Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.88mΩ and L = 0.36µH,
Equation 23 gives Cn = 0.406µF.
Assuming the compensator design is correct, Figure 21 shows the
expected load transient response waveforms if Cn is correctly
selected. When the load current Icore has a square change, the
output voltage Vcore also has a square response.
If Cn value is too large or too small, VCn(s) does not accurately
represent real-time Io(s) and worsens the transient response.
Figure 22 shows the load transient response when Cn is too
small. Vcore sags excessively upon load insertion and may create
a system failure. Figure 23 shows the transient response when
Cn is too large. Vcore is sluggish in drooping to its final value.
There is excessive overshoot if load insertion occurs during this
time, which may negatively affect the CPU reliability.
iL
Vo
RING
BACK
FIGURE 24. OUTPUT VOLTAGE RING-BACK PROBLEM
ISUM+
Rntcs
Cn.1
Cn.2 Vcn
Rp
Rntc
Rn
OPTIONAL
ISUM-
Ri
io
Rip
Cip
OPTIONAL
Vo
FIGURE 21. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
io
Vo
FIGURE 22. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
SMALL
io
Vo
FIGURE 23. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
LARGE
25
FIGURE 25. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION
Figure 24 shows the output voltage ring-back problem during
load transient response. The load current io has a fast step
change, but the inductor current iL cannot accurately follow.
Instead, iL responds in first-order system fashion due to the
nature of the current loop. The ESR and ESL effect of the output
capacitors makes the output voltage Vo dip quickly upon load
current change. However, the controller regulates Vo according to
the droop current idroop, which is a real-time representation of iL;
therefore, it pulls Vo back to the level dictated by iL, causing the
ring-back problem. This phenomenon is not observed when the
output capacitor has very low ESR and ESL, as is the case with all
ceramic capacitors.
Figure 25 shows two optional circuits for reduction of the
ring-back. Cn is the capacitor used to match the inductor time
constant. It usually takes the parallel of two (or more) capacitors
to get the desired value. Figure 25 shows that two capacitors
(Cn.1 and Cn.2) are in parallel. Resistor Rn is an optional
component to reduce the Vo ring-back. At steady state,
Cn.1 + Cn.2 provides the desired Cn capacitance. At the beginning
of io change, the effective capacitance is less because Rn
increases the impedance of the Cn.1 branch. As Figure 22 shows,
Vo tends to dip when Cn is too small, and this effect reduces the
Vo ring-back. This effect is more pronounced when Cn.1 is much
larger than Cn.2. It is also more pronounced when Rn is bigger.
However, the presence of Rn increases the ripple of the Vn signal
if Cn.2 is too small. It is recommended to keep Cn.2 greater than
2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values
should be determined through tuning the load transient response
January 8, 2013
FN7801.1
ISL6267
waveforms on an actual board. Rip and Cip form an R-C branch in
parallel with Ri, providing a lower impedance path than Ri at the
beginning of io change. Rip and Cip do not have any effect at
steady state. Through proper selection of Rip and Cip values,
idroop can resemble io rather than iL, and Vo will not ring back.
The recommended value for Rip is 100Ω. Cip should be
determined through tuning the load transient response
waveforms on an actual board. The recommended range for Cip
is 100pF~2000pF. However, it should be noted that the Rip -Cip
branch may distort the idroop waveform. Instead of being
triangular as the real inductor current, idroop may have sharp
spikes, which may adversely affect idroop average value
detection and therefore may affect OCP accuracy. User discretion
is advised.
Resistor Current-Sensing Network
L
L
DCR
DCR
DCR
For inductor DCR sensing, Equation 27 gives the DC relationship
of Vcn(s) and Io(s):
⎛
⎞
R ntcnet
⎜
DCR⎟
V Cn = ⎜ ----------------------------------------- × ------------⎟ × I o
N ⎟
R sum
⎜
⎝ R ntcnet + ------------⎠
N
(EQ. 27)
(EQ. 28)
Therefore:
RSUM
ISUM+
RSUM
RSEN
For example, the OCP threshold is 60µA for 3-phase solution.
Idroop is designed to be 40.9µA at full load. Therefore the OCP
trip level is 1.5x of the full load current.
R ntcnet
DCR
2
I droop = ----- × ----------------------------------------- × ------------ × I o
R sum
N
Ri
R ntcnet + -------------N
RSUM
RSEN
Refer to Equation 1 on page 20 and Figures 20, 24 and 26;
resistor Ri sets the droop current, Idroop. Tables 6 and 7 show the
internal OCP threshold. It is recommended to design Idroop
without using the Rcomp resistor.
Substitution of Equation 27 into Equation 1 gives Equation 28:
PHASE1 PHASE2 PHASE3
L
Overcurrent Protection
+
VCN
RSEN
RO
-
CN
RI
ISUM-
RO
IO
FIGURE 26. RESISTOR CURRENT-SENSING NETWORK
Figure 26 shows the resistor current-sensing network for a
2-phase solution. Each inductor has a series current sensing
resistor, Rsen. Rsum and Ro are connected to the Rsen pads to
accurately capture the inductor current information. The Rsum
and Ro resistors are connected to capacitor Cn. Rsum and Cn
form a filter for noise attenuation. Equations 24 thru 26 give the
VCn(s) expression.
1
A Rsen ( s ) = ---------------------s
1 + -----------ω sns
(EQ. 29)
Substitution of Equation 19 and application of the OCP condition
in Equation 29 gives Equation 30:
RO
R sen
V Cn ( s ) = ------------ × I o ( s ) × A Rsen ( s )
N
2R ntcnet × DCR × I o
R i = -------------------------------------------------------------------------------R sum
N × ⎛ R ntcnet + --------------⎞ × I droop
⎝
N ⎠
(EQ. 24)
(EQ. 25)
( R ntcs + R ntc ) × R p
2 × --------------------------------------------------- × DCR × I omax
R ntcs + R ntc + R p
R i = ------------------------------------------------------------------------------------------------------------------------⎛ ( R ntcs + R ntc ) × R p R sum⎞
N × ⎜ --------------------------------------------------- + --------------⎟ × I droopmax
N ⎠
⎝ R ntcs + R ntc + R p
(EQ. 30)
where Iomax is the full load current and Idroopmax is the
corresponding droop current. For example, given N = 3,
Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ,
DCR = 0.88mΩ, Iomax = 51A and Idroopmax = 40.9µA.
Equation 30 gives Ri = 606Ω.
For resistor sensing, Equation 31 gives the DC relationship of
Vcn(s) and Io(s).
R sen
V Cn = ------------ × I o
N
(EQ. 31)
Substitution of Equation 31 into Equation 1 gives Equation 32:
2 R sen
I droop = ----- × ------------ × I o
N
Ri
(EQ. 32)
Therefore:
1
ω Rsen = --------------------------R sum
-------------- × C n
N
(EQ. 26)
Transfer function ARsen(s) always has unity gain at DC.
Current-sensing resistor Rsen value does not have significant
variation over-temperature, so there is no need for the NTC
network. The recommended values are Rsum = 1kΩ and
Cn = 5600pF.
26
2R sen × I o
R i = --------------------------N × I droop
(EQ. 33)
Substitution of Equation 33 and application of the OCP condition
in Equation 29 gives Equation 34:
2R sen × I omax
R i = -------------------------------------N × I droopmax
(EQ. 34)
where Iomax is the full load current and Idroopmax is the
corresponding droop current. For example, given N = 3,
Rsen = 1mΩ, Iomax = 51A and Idroopmax = 40.9µA, Equation 34
gives Ri = 831Ω.
January 8, 2013
FN7801.1
ISL6267
Load Line Slope
See Figure 15 for load-line implementation.
For inductor DCR sensing, substitution of Equation 28 into
Equation 2 gives the load-line slope expression in Equation 35:
2R droop
R ntcnet
V droop
DCR
LL = ------------------ = ---------------------- × ----------------------------------------- × -----------Io
Ri
R sum
N
R ntcnet + -------------N
of the sensed output voltage, and then feeds it to the
compensator. T1 is measured after the summing node, and T2 is
measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can actually be measured on an ISL6267 regulator.
(EQ. 35)
VO
L
Q1
For resistor sensing, substitution of Equation 32 into Equation 2
gives the load line slope expression in Equation 36:
2R sen × R droop
V droop
LL = ------------------ = ----------------------------------------Io
N × Ri
VIN
Q2
GATE
DRIVER
iO
COUT
(EQ. 36)
LOAD LINE SLOPE
Substitution of Equation 29 and rewriting Equation 35, or
substitution of Equation 33 and rewriting Equation 36, gives the
same result as in Equation 37:
Io
R droop = ---------------- × LL
I droop
+
20
Ω
+
EA
MOD.
+
COMP
VID
ISOLATION
TRANSFORMER
(EQ. 37)
CHANNEL B
LOOP GAIN =
One can use the full-load condition to calculate Rdroop. For
example, given Iomax = 51A, Idroopmax = 40.9µA and
LL = 1.9mΩ, Equation 37 gives Rdroop = 2.37kΩ.
It is recommended to start with the Rdroop value calculated by
Equation 37 and fine-tune it on the actual board to get accurate
load-line slope. One should record the output voltage readings at
no load and at full load for load-line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Compensator
Figure 21 shows the desired load transient response waveforms.
Figure 27 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Zout(s). If Zout(s) is equal to the
load-line slope LL, i.e., a constant output impedance, then in the
entire frequency range, Vo will have a square response when Io
has a square change.
CHANNEL A
NETWORK
ANALYZER
i
CHANNEL B
EXCITATION OUTPUT
FIGURE 28. LOOP GAIN T1(s) MEASUREMENT SET-UP
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s), therefore
has a higher impact on system stability.
T2(s) is the voltage loop gain with closed droop loop, thus having
a higher impact on output voltage response.
Design the compensator to get stable T1(s) and T2(s) with sufficient
phase margin and an output impedance equal to or smaller than
the load-line slope.
L
VO
Q1
VIN
Zout(s) = LL
CHANNEL A
GATE Q2
DRIVER
IO
CO
o
LOAD LINE SLOPE
VID
VR
LOAD
V
o
EA
MOD.
+
COMP
+
+
VID
20
Ω
ISOLATION
TRANSFORMER
CHANNEL B
FIGURE 27. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
LOOP GAIN =
CHANNEL A
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network so that
VR achieves constant output impedance as a stable system.
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop, which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 28 conceptually
shows T1(s) measurement set-up, and Figure 29 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
current, multiplies it by a gain of the load-line slope, adds it on top
27
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
EXCITATION OUTPUT
FIGURE 29. LOOP GAIN T2(s) MEASUREMENT SET-UP
Current Balancing
Refer to Figures 16 through 20 for information on current
balancing. The ISL6267 achieves current balancing through
matching the ISEN pin voltages. Risen and Cisen form filters to
remove the switching ripple of the phase node voltages. It is
recommended to use a rather long RisenCisen time constant such
January 8, 2013
FN7801.1
ISL6267
that the ISEN voltages have minimal ripple and represent the DC
current flowing through the inductors. Recommended values are
Rs = 10kΩ and Cs = 0.22µF.
NTC Thermal Monitors and VR_HOT Function
The ISL6267 features three pins (NTC, NTC_NB, and VR_HOT)
which are allow the IC to monitor board temperature and alert
the AMD CPU of a thermal issue. Figure 30 shows the thermal
monitor feature of the ISL6267. An NTC network is connected
between the NTC and NTC_NB pins and GND. The controller
drives a 60µA current source out of the NTC pin and the NTC_NB
pin alternatively at 1kHz frequency with 50% duty cycle. The
pulsed current flows through the respective NTC resistor network
on the pins and creates a voltage that is compared to an
over-temperature trip threshold. If the voltage on both NTC pins is
higher than the over-temperature trip threshold, then VR_HOT is
pulled up by an external resistor on the pin.
the state of VR_HOT, is defined in Equation 38.
0.88V
--------------- = 14.7k
60μA
(EQ. 38)
The equivalent resistance at the typical reset threshold voltage of
0.92V required to change the state of VR_HOT back low, is
defined in Equation 39
0.92V
--------------- = 15.3k
60μA
(EQ. 39)
The NTC thermistor value correlates this resistance change to the
required temperature hysteresis. A standard 1% resistor is
typically needed to meet the NTC pin threshold voltage.
For example, a Panasonic NTC thermistor with B = 4700 has a
resistance ratio of 0.03322 of its nominal value at +105°C and
0.03956 of its nominal value at +100°C. The required resistance
of the NTC is defined in Equation 40.
( 15.3kΩ – 14.7kΩ )
------------------------------------------------------- = 94.6kΩ
( 0.03956 – 0.03322 )
(EQ. 40)
NTC
+V
Rp
+
VNTC
-
60µA
RNTC
VR_HOT
R
SW1
Rs
MONITOR
SW2
SW1 SW2
NTC_NB
Rp
+
VNTC
-
INTERNAL TO
ISL6267
RNTC
The closest, larger thermistor value for B = 4700 is 100kΩ. The
NTC thermistor part number is ERTJ1VV104.
At +105°C, a 100kΩ NTC resistance drops to
(0.03322 x 100kΩ) = 3.322kΩ. With a 60µA current flowing out
of the NTC pin, the voltage drop across the resistor is only
(3.322kΩ x 60µA) = 0.199V. This value is much lower than the
threshold voltage of 0.88V. A standard resistor, 1% tolerance,
added in series with the thermistor is required to raise the
voltage on the pin. The resistance required to meet the trip
threshold is calculated in Equation 41.
0.88V
--------------- – 3.322kΩ = 11.34kΩ
60μA
Rs
(EQ. 41)
The closest, standard 1% tolerance resistor is 11.3kΩ.
FIGURE 30. CIRCUITRY ASSOCIATED WITH THE THERMAL
MONITOR FEATURE OF THE ISL6267
As the board temperature rises, the NTC thermistor resistance
decreases and the voltage at the NTC pin drops. When the
voltage on the NTC pin drops below the over-temperature trip
threshold, then VR_HOT is pulled low. The VR_HOT signal is used
to change the CPU operation and decrease power consumption.
With the reduction in power consumption by the CPU, the board
temperature decreases and the NTC thermistor voltage rises.
Once the over-temperature threshold is tripped and VR_HOT is
taken low, the over-temperature threshold changes to the reset
level. The addition of hysteresis to the over-temperature
threshold prevents nuisance trips. Once both pin voltages exceed
the over-temperature reset threshold, the pull-down on VR_HOT
is released. The signal changes state and the CPU resumes
normal operation. The over-temperature threshold returns to the
trip level.
The NTC thermistor is placed in a hot spot on the board, typically
near the upper MOSFET of channel 1 of the respective output.
The standard resistor is placed next to the controller.
Selection of the NTC components can vary depending on how the
resistor network is configured. The equivalent resistance at the
typical over-temperature threshold voltage of 0.88V, to change
28
January 8, 2013
FN7801.1
ISL6267
Layout Guidelines
Table 9 shows layout considerations for the ISL6267 controller. Refer to the reference designators shown in Figure 31.
TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER
ISL6267
SYMBOL
LAYOUT GUIDELINES
BOTTOM PAD
GND
Create analog ground plane underneath the controller and the analog signal processing components. Do not let
the power ground plane overlap with the analog ground plane. Avoid allowing noisy planes/traces (e.g., phase
node) to crossover/overlap the analog plane.
1
FB2_NB
2
FB_NB
3
COMP_NB
4
VW_NB
5
PGOOD_NB
6, 7, 8
SVD, PWROK, SVC
9
ENABLE
No special consideration.
10
PGOOD
No special consideration.
11
VR_HOT
No special consideration.
12
NTC
Place the NTC thermistor (R46) close to the thermal source that is monitored to determine CPU VCORE thermal
throttling. Usually it is placed close to Core VR phase-1 high-side MOSFET.
13
VW
Place the capacitor (C4) across VW and COMP close to the controller.
14
COMP
15
FB
16
FB2
Place the compensator components (R25, R9, R24, C88, C51, C86, and C153) close to the controller.
Place the capacitor (C85) across VW, and place COMP close to the controller.
ISEN2
18
ISEN1
Use good signal integrity practices.
Place the compensator components (R7, R10, R11, C3, C6, C11 and C5) in general proximity to the controller.
ISEN3
17
No special consideration.
Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN and then through another capacitor (Cvsumn) to
GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small:
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops to be minimized.
Phase1
L3
Ro
Risen
ISEN3
Cisen
Phase2
Vo
L2
Ro
Risen
ISEN2
Cisen
Phase3
Risen
ISEN1
GND
19
VSEN
20
RTN
L1
Ro
Vsumn
Cisen
Cvsumn
Place the VSEN/RTN filter (C12, C13) close to the controller for good decoupling.
29
January 8, 2013
FN7801.1
ISL6267
TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER (Continued)
ISL6267
SYMBOL
LAYOUT GUIDELINES
21
ISUMN
22
ISUMP
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to VR1 phase-1 inductor (L1) so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71
to Core VR phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and
R72 to Core VR phase-2 side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible,
route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center
of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the
inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
23
VDD
A capacitor (C16) decouples it to GND. Place it in close proximity to the controller.
24
VIN
A capacitor (C17) decouples it to GND. Place it in close proximity to the controller.
25
PROG1
No special consideration.
26
BOOT1
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
27
UGATE1
28
PHASE1
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1 trace to VR1 phase-1 high-side MOSFET (Q2 and
Q8) source pins instead of general copper.
29
LGATE1
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
30
PWM3
No special consideration.
31
VCCP
A capacitor (C22) decouples it to GND. Place it in close proximity to the controller.
32
LGATE2
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
33
PHASE2
34
UGATE2
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE2 trace to VR1 phase-2 high-side MOSFET (Q4 and
Q10) source pins instead of general copper.
35
BOOT2
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
36
PWM2_NB
No special consideration.
37
LGATE1_NB
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
38
PHASE1_NB
39
UGATE1_NB
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1G trace to VR2 phase-1 high-side MOSFET source
pins instead of general copper.
40
BOOT1_NB
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
41
PROG2
No special consideration.
42
NTC_NB
Place the NTC thermistor close to the thermal source that is monitored to determine GT VCORE thermal
throttling. Usually it is placed close to Northbridge VR phase-1 high-side MOSFET.
43
ISUMN_NB
44
ISUMP_NB
30
Place the current sensing circuit in general proximity to the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Northbridge VR phase-1 inductor (L1) so it senses the inductor temperature
correctly.
See ISUMN and ISUMP pins for layout guidelines of current-sensing trace routing.
January 8, 2013
FN7801.1
ISL6267
TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER (Continued)
ISL6267
SYMBOL
LAYOUT GUIDELINES
45
RTN_NB
46
VSEN_NB
47
ISEN2_NB
48
ISEN1_NB
Place the VSEN/RTN filter (C89, C90) in close proximity to the controller for good decoupling.
See ISEN1, ISEN2 and ISEN3 pins for layout guidelines of current-balancing circuit trace routing.
FIGURE 31. PORTION OF ISL6267EVAL1Z EVALUATION BOARD SCHEMATIC
31
January 8, 2013
FN7801.1
ISL6267
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
1/31/11
FN7801.0
Initial Release.
November 5, 2012
FN7801.1
Page 9: Added IRZ parts to ordering information table.
About Intersil
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For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
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32
January 8, 2013
FN7801.1
ISL6267
Package Outline Drawing
L48.6x6B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/09
4X 4.4
6.00
44X 0.40
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
37
1
6.00
36
4 .40 ± 0.15
25
12
0.15
(4X)
13
24
0.10 M C A B
0.05 M C
TOP VIEW
48X 0.45 ± 0.10
4 48X 0.20
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
BASE PLANE
MAX 1.00
(
SEATING PLANE
0.08 C
( 44 X 0 . 40 )
( 5. 75 TYP )
C
SIDE VIEW
4. 40 )
C
0 . 2 REF
5
( 48X 0 . 20 )
0 . 00 MIN.
0 . 05 MAX.
( 48X 0 . 65 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
33
January 8, 2013
FN7801.1
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